- Email: [email protected]
Novel polysilicon gate engineering with a laser thermal process for sub-40 nm CMOS devices
Solid-State Electronics 48 (2004) 1837–1842 www.elsevier.com/locate/sse
Novel polysilicon gate engineering with a laser thermal process for sub-40 nm CMOS devices T. Yamamoto a
a,*
, K. Okabe a, T. Kubo a, K. Goto a, H. Morioka a, Y. Wang b, T. Lin b, S. Talwar b, M. Kase a, T. Sugii a
Device Development Department, Advanced LSI Development Division, Fujitsu Ltd., Akiruno Technology Center, 50 Fuchigami, Akiruno, Tokyo, 197-0833, Japan b Ultratech Inc., San Jose, CA 95134, USA Received 10 December 2003; accepted 15 March 2004 Available online 24 June 2004
Abstract We demonstrate a novel poly-Si gate engineering by laser thermal process (LTP) to suppress gate depletion for high performance sub-40 nm CMOS devices. To show the full advantage of LTP, an optimized BEOL process has been employed to suppress dopant deactivation and achieve a reduction of electrical inversion gate oxide thickness by 0.1/ 0.06 nm (PMOS/NMOS), which improves the Ion current by 11/7% (PMOS/NMOS). Furthermore, a novel source-drain rapid thermal annealing (SD-RTA) has been developed to suppress dopant dose loss to achieve a 5% improvement of the Ion current for NMOS. Ó 2004 Elsevier Ltd. All rights reserved. PACS: 85.30.De Keywords: Laser thermal process; Gate depletion; Low thermal budget SD-RTA; Amorphous Si; Sub-40 nm CMOS
1. Introduction For aggressively scaling of CMOS devices, low thermal budget source-drain rapid thermal annealing (SD-RTA) processing becomes more important to maintain shallow junctions for well-controlled short channel effects. However, low thermal budget SD-RTA tends to induce severe poly-Si gate depletion due to low dopant diffusivity and activation and, as a result, device performance is degraded [1–3]. We have developed a novel poly-Si gate engineering method with a laser thermal process (LTP) [4] to minimize poly-Si gate depletion even under low temperature SD-RTA, and applied this process, for the first time, to sub-40 nm CMOS devices. In addition, we have optimized the
*
Corresponding author. Tel.: +81-42-532-1253; fax: +81-42532-2513. E-mail address: [email protected] (T. Yamamoto).
back-end-of-line (BEOL) process to suppress dopant deactivation and developed a new SD-RTA technique with a small O2 flux to suppress the loss of dopant dose and maximize the benefit of LTP.
2. Fundamental characteristics of LTP for Si-Gate activation Fig. 1 shows the concept of gate activation by LTP. Our LTP system used in this work has already been explained in the literature [5] and we have also demonstrated the source-drain extension (SDE) profiles and deep source-drain profiles formed by LTP to reduce the parasitic resistance and improve device performance [5–8]. In previous work, we focused on selective melting for recrystallization and dopant profile control, which was realized with pre-amorphization ion implantation. This is based on the fact that the melting point of amorphous-Si is lower than the melting point of single
0038-1101/$ - see front matter Ó 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2004.05.023
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3
B, P Concentration in Si-Gate[atoms/cm ]
Fig. 1. Schematic diagrams of gate activation by laser thermal process (LTP). Amorphous Si is deposited as the gate electrode material and is transformed to poly-Si with highly activated dopant profiles after laser annealing by melt to recrystallization.
22
10
(a) Boron for PMOS
(b) Phosphorous for NMOS
only SD-RTA 2
SiO2
only SD-RTA
0.8[J/cm ]+SD-RTA
2
SiO2
0.8[J/cm ]+SD-RTA
21
10
SIMS measurement 20
Si-Gate
10
SiO2 Si-Sub.
Sample Structure 0
10
20
30
40
50
60
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80 0
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Fig. 2. SIMS (secondary ion mass spectrometer) profiles of only source-drain rapid thermal annealing (SD-RTA) and LTP + SD-RTA for boron (a) and phosphorous (b). The inset illustration shows the sample structure.
crystal-Si. In this work, we used amorphous-Si as the gate material for selective melting to recrystallization. Doped amorphous-Si is transformed to poly-Si and highly activated dopant profiles down to Si-Gate/SiO2 interface can be achieved by selective melting to recrystallization. Fig. 2 show the SIMS (secondary ion mass spectrometer) profiles of only SD-RTA and LTP + SD-RTA for boron (a) and phosphorous (b), respectively. Compared to only SD-RTA, higher dopant concentrations at the Si-Gate/SiO2 interface can be achieved by using LTP for both boron and phosphorous implants to provide suppression of gate depletion. In addition, in the case of boron, concentrations at the upper side of the Si-Gate can be lowered by LTP. This is because the dopant diffusion in the melting amorphous Si is very high, and the dopant tends to show comparatively uniform box-like profiles in the recrystallized
region. As a result, lower concentrations than those obtained with an SD-RTA process can be achieved at the upper side of the Si-Gate. This process is suitable for silicidation.
3. Device characteristics 3.1. Device fabrication The fabrication process flow of LTP MOSFETs is shown in Fig. 3. After device isolation with shallow trench isolation (STI), a conventional well is formed followed with a threshold voltage control implantation. A nitrided oxide is used as the gate insulator. Amorphous Si is deposited as the gate electrode material and is transformed to poly-Si with highly activated dopant
Isolation Gate Oxidation (Nitrided Oxide) Amorphous-Si Gate Ion Implantation (B+ for PMOS, P+ for NMOS) LTP (melt to recrystallize) Gate Formation Source Drain Extension Ion Implantation Sidewall Spacer Formation Source Drain Ion Implantation Source Drain RTA (Lower Temperature spike RTA) Silicidation BEOL Process (Optimized)
Fig. 3. Fabrication process flow of LTP MOSFETs.
400
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PMOS
350
15 300 14
250 200
13
150 12 100 11
50 0
10 2
0.8[J/cm ]
profiles after laser annealing by melt to recrystallization. A sub-40 nm gate is patterned using ArF lithography and highly selective RIE. A spike RTA is performed with high ramp-up/down rate [9] as the SD-RTA and its peak temperature is comparatively lowered for the effective suppression of short-channel effects. 3.2. Impact of LTP and BEOL process optimization Fig. 4 shows the CV characteristics of PMOSFETs (a) and NMOSFETs (b) with LTP and no LTP ( ¼ only SD-RTA). Gate depletion can be suppressed drastically by using LTP for both PMOS and NMOS. The electrical inversion oxide thickness (effective oxide thickness: Teff ) is improved to 1.45/0.22 nm (PMOS/NMOS) by applying a laser energy density of 0.8 J/cm2 . The laser power dependence of non-silicided Si-Gate sheet resistance (Rs ) and Rs of NiSi on Si-Gate for PMOS are shown in Fig. 5. The Rs of non-silicided Si-Gate can be reduced dras-
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Rs of NiSi on Si-Gate[Ω/sq.]
Rs of non-silicided Si-Gate[Ω /sq.]
T. Yamamoto et al. / Solid-State Electronics 48 (2004) 1837–1842
2
0.6[J/cm ]
no-LTP
Fig. 5. Laser power dependence of sheet resistance (Rs ) of NiSi on Si-Gate and Rs of non-silicided Si-Gate for PMOS.
tically by LTP owing to the higher dopant diffusion and higher carrier activation. In addition, the Rs of NiSi on Si-Gate can also be reduced by LTP. This is because, as shown in Fig. 2, the concentration of boron at the upper side of the Si-Gate is lower than the concentration of only SD-RTA. Thus, the silicide retardation can be suppressed and, as a result, lower Rs values of NiSi on Si-Gate can be achieved by LTP. Fig. 6 shows the comparison of Rs of non-silicided SiGate and Teff between the conventional back-end-of-line (BEOL) process and the optimized BEOL process for PMOS (a) and NMOS (b). By optimizing the BEOL process, dopant deactivation can be suppressed. In our experiments, Teff can be reduced by 0.1 nm for PMOS devices and 0.06 nm for NMOS devices. Ion vs. Ioff characteristics for PMOS and NMOS devices are shown in Fig. 7 (a) and (b), respectively. We see the Ion current
no-LTP
no-LTP 2
2
0.6[J/cm ]
0.6[J/cm ] 2
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-1
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0.5
Vg[V]
1
1.5
(b)NMOS -1.5
-1
-0.5
0
0.5
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1.5
Vg[V]
Fig. 4. CV characteristics of PMOSFETs (a) and NMOSFETs (b) with LTP and no LTP ( ¼ only SD-RTA). The channel width is 20 lm and the gate length is 1 lm.
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delta-Teff [nm] (- Conventional)
Rs of non-silicided Si-Gate[Ω/sq.]
120
-0.1
Optimized Conventional BEOL BEOL
Optimized Conventional BEOL BEOL
Fig. 6. Comparison of Rs of non-silicided Si-Gate and electrical inversion oxide thickness (effective oxide thickness: Teff ) between the conventional back-end-of-line (BEOL) process and the optimized BEOL process for PMOS (a) and NMOS (b).
is improved drastically with the use of LTP, while very poor performance is observed for the case of no LTP because of severe gate depletion. In addition, by employing an optimized BEOL process, an Ion current improvement of 11/7% for PMOS/NMOS devices at Ioff ¼ 3e8 A/lm is achieved compared to the conventional BEOL process. 3.3. Suppression of dopant dose loss by SD-RTA optimization Fig. 8 shows the retained dopant amount in Si-Gate measured by SIMS profile data for only LTP (0.8 J/cm2 )
and LTP + conventional SD-RTA. After a conventional SD-RTA, severe dopant dose loss occurs, especially for the phosphorous case. This is due to the out-diffusion of phosphorous during the SD-RTA processing. We have developed a technique for suppressing the dopant dose loss, which maximizes the benefit of the LTP, by introducing a low O2 flux (less than 0.1%) during SD-RTA processing (O2 -annealing: O2 -AN), while conventional SD-RTA uses a N2 atmosphere (N2 -annealing: N2 -AN). In Fig. 9(a), the Teff of the LTP NMOS device with O2 AN is compared with the conventional N2 -AN. Both SD-RTA devices were processed under the same annealing sequence with respect to annealing tempera-
-6
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(a) PMOS Lower Temp.SD-RTA Vd=-1.0V
(b) NMOS Vd=1.0V
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no LTP+Conventional BEOL
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Ion[mA/µm]
2
0.4
0.5
0.6
0.7
0.8
0.9
Ion[mA/µm]
Fig. 7. Ion vs. Ioff characteristics of PMOS (a) and NMOS (b) for no LTP, LTP with a conventional BEOL process and LTP with an optimized BEOL process.
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2
LTP(0.8J/cm )
NMOS
0.9 -7
Out-diffusion
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Phosphorous Boron
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Vd=1.0V 2
LTP(0.8J/cm )
-9
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SD-RTA:N2-AN with Medium SD-dose 15
2
-10
10
0.4
Fig. 8. Retained dopant amount in Si-Gate measured by SIMS profile data for only LTP (0.8 J/cm2 ) and LTP + conventional SD-RTA.
0.02nm -0.02
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0.9
However, the same characteristics can be achieved by lowering the SD-dose as shown in Fig. 9(b). At the same time, the contact resistance between the silicide and the Si can be reduced by 20% (Fig. 9(c)). This suggests the higher phosphorous concentration at the silicide–Si interface can be achieved by using an O2 -AN process. Fig. 10 shows the Ion vs. Ioff characteristics in the O2 -AN and N2 -AN processes. For the O2 -AN process, the SDdose is lowered to obtain the same Ioff current at the same Lgate. Ion current enhancement by 5% is obtained
(b) Lgate[ m]
LTP(0.8J/cm ) NMOS
0.6
Fig. 10. Improvement in Ion vs. Ioff characteristics with an SDdose and SD-RTA optimization for LTP NMOS.
0.06 0.02
0.5
Ion[mA/µm]
ture and time. By using O2 -AN, the gate depletion is suppressed by 0.02 nm for the same source-drain implant dose (SD-dose) due to the suppression of dopant dose loss in the Si-Gate. We can achieve a lower Teff value regardless of the SD-dose owing to the higher gate activation with the LTP. Fig. 9(b) compares the Lgate at Ioff ¼ 3e8 A/lm of O2 -AN with the N2 -AN. For the same SD-dose, the short channel performance deteriorates for O2 -AN because of the lateral deep SD phosphorous encroachment. This is because the SD dopant dose loss can be suppressed as well as the Si-Gate.
(a) delta-Teff[nm]
2
SD-RTA:O2-AN with Low SD-dose (- 2X10 cm )
LTP & SD-RTA(N )
LTP
delta-Teff[nm](- SD-RTA:N2-AN)
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T. Yamamoto et al. / Solid-State Electronics 48 (2004) 1837–1842
+
(C) Rc (NiSi-N SD) 1
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2
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SD-RTA:O -AN 2
-2 10
15
0
2 10
15
normalized SD-dose(P)
Fig. 9. Comparison of Teff (a), Lgate [lm] at Ioff ¼ 3e8 A/lm (b), and contact resistance (Rc ) between the NiSi and the Nþ sourcedrain (NiSi-Nþ SD) (c) between N2 -annealing (N2 -AN) and O2 -annealing (O2 -AN) for LTP NMOS.
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4. Conclusions
0.06 0.055
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2
delta-Teff[nm] (- SD-RTA:N -AN)
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0.045
0
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0.035 -0.04
Lgate[ µm]@Ioff=3e-8[A/µm]
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We described a novel poly-Si gate engineering with a laser thermal process; we obtained high electrical activation to suppress gate depletion for high performance sub-40 nm CMOS devices. Back-end-of-line (BEOL) process optimization, essential for the suppression of dopant deactivation, is described with 11/7% (PMOS/ NMOS) enhancement of Ion current and 0.1/0.06 nm (PMOS/NMOS) improvement of Teff . In addition, a novel SD-RTA process with a small O2 flux suppresses dopant dose loss for phosphorous and improves the Ion current by 5% for NMOS device with no penalty for PMOS device performance.
SD-RTA:N -AN SD-RTA:O -AN 2
2
Fig. 11. Comparison of Lgate at Ioff ¼ 3e 8 A/lm and Teff between N2 -AN and O2 -AN for LTP PMOS.
0.4 0.3
2
LTP(0.8J/cm ) SD-RTA:O2-AN
Vth [V]
0.2
Acknowledgements The authors would like to thank Y. Tada and S. Kodama of Fujitsu Laboratories for SIMS and TEM measurements and Process Development Department and Manufacturing Technology Department of Fujitsu Ltd., for device fabrication.
Vd=1.0V
0.1 0
References
-0.1
Vd=-1.0V
-0.2 -0.3 -0.4
0.03
0.06
0.09
0.12
Lgate [µm]
Fig. 12. Vth-rolloff characteristics of LTP NMOS and PMOS with an SD-RTA:O2 -AN and an optimized BEOL process.
at Ioff ¼ 3e8 A/lm by using the O2 -AN process. In the case of the PMOS device, we see no difference between N2 -AN and O2 -AN processes (Fig. 11). This is because we have carefully chose the O2 flux condition to avoid severe oxidation-enhanced diffusion (OED) for boron. Fig. 12 shows the threshold voltage (Vth) rolloff characteristics for optimized LTP NMOS and PMOS device, which shows good suppression of short channel effects down to sub-40 nm gate length.
[1] Morifuji E, Kanda M, Yanagishita N, Matsuda S, Inaba S, Okano K, et al. IEDM Tech Dig 2002:655–8. [2] Fukai T, Nakamura Y, Terai M, Koyama S, Morikuni Y, Suzuki T, et al. Symposium on VLSI Technology 2003. p. 83–4. [3] Hokazono A, Ohuchi K, Takayanagi M, Watanabe Y, Magoshi S, Kato Y, et al. IEDM Tech Dig 2002:639–42. [4] Seibel C, Talwar S. US Patent 20030045074. [5] Goto K, Yamamoto T, Kubo T, Kase M, Wang Y, Lin T, et al. IEDM Tech Dig 1999:931–3. [6] Yamamoto T, Goto K, Tada Y, Kikuchi Y, Kubo T, Wang Y, et al. Symposium on VLSI Technology. 2002. p. 138–9. [7] Yamamoto T, Goto K, Kubo T, Wang Y, Lin T, Talwar S, et al. Extended Abstract of International Workshop on Junction Technology. 2002. p. 27–30. [8] Yamamoto T, Goto K, Kubo T, Wang Y, Talwar S, Kase M, Sugii T. International Semiconductor Technology Conference. 2002. No. 67. [9] Momiyama Y, Okabe K, Nakao H, Kase M, Kojima M, Sugii T. IEDM Tech Dig 2002:647–50.
Novel polysilicon gate engineering with a laser thermal process for sub-40 nm CMOS devices T. Yamamoto a
a,*
, K. Okabe a, T. Kubo a, K. Goto a, H. Morioka a, Y. Wang b, T. Lin b, S. Talwar b, M. Kase a, T. Sugii a
Device Development Department, Advanced LSI Development Division, Fujitsu Ltd., Akiruno Technology Center, 50 Fuchigami, Akiruno, Tokyo, 197-0833, Japan b Ultratech Inc., San Jose, CA 95134, USA Received 10 December 2003; accepted 15 March 2004 Available online 24 June 2004
Abstract We demonstrate a novel poly-Si gate engineering by laser thermal process (LTP) to suppress gate depletion for high performance sub-40 nm CMOS devices. To show the full advantage of LTP, an optimized BEOL process has been employed to suppress dopant deactivation and achieve a reduction of electrical inversion gate oxide thickness by 0.1/ 0.06 nm (PMOS/NMOS), which improves the Ion current by 11/7% (PMOS/NMOS). Furthermore, a novel source-drain rapid thermal annealing (SD-RTA) has been developed to suppress dopant dose loss to achieve a 5% improvement of the Ion current for NMOS. Ó 2004 Elsevier Ltd. All rights reserved. PACS: 85.30.De Keywords: Laser thermal process; Gate depletion; Low thermal budget SD-RTA; Amorphous Si; Sub-40 nm CMOS
1. Introduction For aggressively scaling of CMOS devices, low thermal budget source-drain rapid thermal annealing (SD-RTA) processing becomes more important to maintain shallow junctions for well-controlled short channel effects. However, low thermal budget SD-RTA tends to induce severe poly-Si gate depletion due to low dopant diffusivity and activation and, as a result, device performance is degraded [1–3]. We have developed a novel poly-Si gate engineering method with a laser thermal process (LTP) [4] to minimize poly-Si gate depletion even under low temperature SD-RTA, and applied this process, for the first time, to sub-40 nm CMOS devices. In addition, we have optimized the
*
Corresponding author. Tel.: +81-42-532-1253; fax: +81-42532-2513. E-mail address: [email protected] (T. Yamamoto).
back-end-of-line (BEOL) process to suppress dopant deactivation and developed a new SD-RTA technique with a small O2 flux to suppress the loss of dopant dose and maximize the benefit of LTP.
2. Fundamental characteristics of LTP for Si-Gate activation Fig. 1 shows the concept of gate activation by LTP. Our LTP system used in this work has already been explained in the literature [5] and we have also demonstrated the source-drain extension (SDE) profiles and deep source-drain profiles formed by LTP to reduce the parasitic resistance and improve device performance [5–8]. In previous work, we focused on selective melting for recrystallization and dopant profile control, which was realized with pre-amorphization ion implantation. This is based on the fact that the melting point of amorphous-Si is lower than the melting point of single
0038-1101/$ - see front matter Ó 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2004.05.023
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3
B, P Concentration in Si-Gate[atoms/cm ]
Fig. 1. Schematic diagrams of gate activation by laser thermal process (LTP). Amorphous Si is deposited as the gate electrode material and is transformed to poly-Si with highly activated dopant profiles after laser annealing by melt to recrystallization.
22
10
(a) Boron for PMOS
(b) Phosphorous for NMOS
only SD-RTA 2
SiO2
only SD-RTA
0.8[J/cm ]+SD-RTA
2
SiO2
0.8[J/cm ]+SD-RTA
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10
SIMS measurement 20
Si-Gate
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SiO2 Si-Sub.
Sample Structure 0
10
20
30
40
50
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Depth(nm)
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80 0
10
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30
40
50
60
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Fig. 2. SIMS (secondary ion mass spectrometer) profiles of only source-drain rapid thermal annealing (SD-RTA) and LTP + SD-RTA for boron (a) and phosphorous (b). The inset illustration shows the sample structure.
crystal-Si. In this work, we used amorphous-Si as the gate material for selective melting to recrystallization. Doped amorphous-Si is transformed to poly-Si and highly activated dopant profiles down to Si-Gate/SiO2 interface can be achieved by selective melting to recrystallization. Fig. 2 show the SIMS (secondary ion mass spectrometer) profiles of only SD-RTA and LTP + SD-RTA for boron (a) and phosphorous (b), respectively. Compared to only SD-RTA, higher dopant concentrations at the Si-Gate/SiO2 interface can be achieved by using LTP for both boron and phosphorous implants to provide suppression of gate depletion. In addition, in the case of boron, concentrations at the upper side of the Si-Gate can be lowered by LTP. This is because the dopant diffusion in the melting amorphous Si is very high, and the dopant tends to show comparatively uniform box-like profiles in the recrystallized
region. As a result, lower concentrations than those obtained with an SD-RTA process can be achieved at the upper side of the Si-Gate. This process is suitable for silicidation.
3. Device characteristics 3.1. Device fabrication The fabrication process flow of LTP MOSFETs is shown in Fig. 3. After device isolation with shallow trench isolation (STI), a conventional well is formed followed with a threshold voltage control implantation. A nitrided oxide is used as the gate insulator. Amorphous Si is deposited as the gate electrode material and is transformed to poly-Si with highly activated dopant
Isolation Gate Oxidation (Nitrided Oxide) Amorphous-Si Gate Ion Implantation (B+ for PMOS, P+ for NMOS) LTP (melt to recrystallize) Gate Formation Source Drain Extension Ion Implantation Sidewall Spacer Formation Source Drain Ion Implantation Source Drain RTA (Lower Temperature spike RTA) Silicidation BEOL Process (Optimized)
Fig. 3. Fabrication process flow of LTP MOSFETs.
400
16
PMOS
350
15 300 14
250 200
13
150 12 100 11
50 0
10 2
0.8[J/cm ]
profiles after laser annealing by melt to recrystallization. A sub-40 nm gate is patterned using ArF lithography and highly selective RIE. A spike RTA is performed with high ramp-up/down rate [9] as the SD-RTA and its peak temperature is comparatively lowered for the effective suppression of short-channel effects. 3.2. Impact of LTP and BEOL process optimization Fig. 4 shows the CV characteristics of PMOSFETs (a) and NMOSFETs (b) with LTP and no LTP ( ¼ only SD-RTA). Gate depletion can be suppressed drastically by using LTP for both PMOS and NMOS. The electrical inversion oxide thickness (effective oxide thickness: Teff ) is improved to 1.45/0.22 nm (PMOS/NMOS) by applying a laser energy density of 0.8 J/cm2 . The laser power dependence of non-silicided Si-Gate sheet resistance (Rs ) and Rs of NiSi on Si-Gate for PMOS are shown in Fig. 5. The Rs of non-silicided Si-Gate can be reduced dras-
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Rs of NiSi on Si-Gate[Ω/sq.]
Rs of non-silicided Si-Gate[Ω /sq.]
T. Yamamoto et al. / Solid-State Electronics 48 (2004) 1837–1842
2
0.6[J/cm ]
no-LTP
Fig. 5. Laser power dependence of sheet resistance (Rs ) of NiSi on Si-Gate and Rs of non-silicided Si-Gate for PMOS.
tically by LTP owing to the higher dopant diffusion and higher carrier activation. In addition, the Rs of NiSi on Si-Gate can also be reduced by LTP. This is because, as shown in Fig. 2, the concentration of boron at the upper side of the Si-Gate is lower than the concentration of only SD-RTA. Thus, the silicide retardation can be suppressed and, as a result, lower Rs values of NiSi on Si-Gate can be achieved by LTP. Fig. 6 shows the comparison of Rs of non-silicided SiGate and Teff between the conventional back-end-of-line (BEOL) process and the optimized BEOL process for PMOS (a) and NMOS (b). By optimizing the BEOL process, dopant deactivation can be suppressed. In our experiments, Teff can be reduced by 0.1 nm for PMOS devices and 0.06 nm for NMOS devices. Ion vs. Ioff characteristics for PMOS and NMOS devices are shown in Fig. 7 (a) and (b), respectively. We see the Ion current
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-0.5
0
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Vg[V]
Fig. 4. CV characteristics of PMOSFETs (a) and NMOSFETs (b) with LTP and no LTP ( ¼ only SD-RTA). The channel width is 20 lm and the gate length is 1 lm.
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Optimized Conventional BEOL BEOL
Optimized Conventional BEOL BEOL
Fig. 6. Comparison of Rs of non-silicided Si-Gate and electrical inversion oxide thickness (effective oxide thickness: Teff ) between the conventional back-end-of-line (BEOL) process and the optimized BEOL process for PMOS (a) and NMOS (b).
is improved drastically with the use of LTP, while very poor performance is observed for the case of no LTP because of severe gate depletion. In addition, by employing an optimized BEOL process, an Ion current improvement of 11/7% for PMOS/NMOS devices at Ioff ¼ 3e8 A/lm is achieved compared to the conventional BEOL process. 3.3. Suppression of dopant dose loss by SD-RTA optimization Fig. 8 shows the retained dopant amount in Si-Gate measured by SIMS profile data for only LTP (0.8 J/cm2 )
and LTP + conventional SD-RTA. After a conventional SD-RTA, severe dopant dose loss occurs, especially for the phosphorous case. This is due to the out-diffusion of phosphorous during the SD-RTA processing. We have developed a technique for suppressing the dopant dose loss, which maximizes the benefit of the LTP, by introducing a low O2 flux (less than 0.1%) during SD-RTA processing (O2 -annealing: O2 -AN), while conventional SD-RTA uses a N2 atmosphere (N2 -annealing: N2 -AN). In Fig. 9(a), the Teff of the LTP NMOS device with O2 AN is compared with the conventional N2 -AN. Both SD-RTA devices were processed under the same annealing sequence with respect to annealing tempera-
-6
10
(a) PMOS Lower Temp.SD-RTA Vd=-1.0V
(b) NMOS Vd=1.0V
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Ioff[A/µm]
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LTP(0.8J/cm )+Optimized BEOL 2
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LTP(0.8J/cm )+Conventional BEOL
LTP(0.8J/cm )+Conventional BEOL
no LTP+Conventional BEOL
no LTP+Conventional BEOL
0.05 0.1 0.15 0.2 0.25 0.3 0.35
Ion[mA/µm]
2
0.4
0.5
0.6
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Ion[mA/µm]
Fig. 7. Ion vs. Ioff characteristics of PMOS (a) and NMOS (b) for no LTP, LTP with a conventional BEOL process and LTP with an optimized BEOL process.
10
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NMOS
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Out-diffusion
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Phosphorous Boron
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LTP(0.8J/cm )
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SD-RTA:N2-AN with Medium SD-dose 15
2
-10
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Fig. 8. Retained dopant amount in Si-Gate measured by SIMS profile data for only LTP (0.8 J/cm2 ) and LTP + conventional SD-RTA.
0.02nm -0.02
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+ Contact Resistance of NiSi-N SD(P) (a.u.)
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2
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However, the same characteristics can be achieved by lowering the SD-dose as shown in Fig. 9(b). At the same time, the contact resistance between the silicide and the Si can be reduced by 20% (Fig. 9(c)). This suggests the higher phosphorous concentration at the silicide–Si interface can be achieved by using an O2 -AN process. Fig. 10 shows the Ion vs. Ioff characteristics in the O2 -AN and N2 -AN processes. For the O2 -AN process, the SDdose is lowered to obtain the same Ioff current at the same Lgate. Ion current enhancement by 5% is obtained
(b) Lgate[ m]
LTP(0.8J/cm ) NMOS
0.6
Fig. 10. Improvement in Ion vs. Ioff characteristics with an SDdose and SD-RTA optimization for LTP NMOS.
0.06 0.02
0.5
Ion[mA/µm]
ture and time. By using O2 -AN, the gate depletion is suppressed by 0.02 nm for the same source-drain implant dose (SD-dose) due to the suppression of dopant dose loss in the Si-Gate. We can achieve a lower Teff value regardless of the SD-dose owing to the higher gate activation with the LTP. Fig. 9(b) compares the Lgate at Ioff ¼ 3e8 A/lm of O2 -AN with the N2 -AN. For the same SD-dose, the short channel performance deteriorates for O2 -AN because of the lateral deep SD phosphorous encroachment. This is because the SD dopant dose loss can be suppressed as well as the Si-Gate.
(a) delta-Teff[nm]
2
SD-RTA:O2-AN with Low SD-dose (- 2X10 cm )
LTP & SD-RTA(N )
LTP
delta-Teff[nm](- SD-RTA:N2-AN)
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1
Ioff[A/µm]
Retained dopant concentration ratio in Si-Gate
T. Yamamoto et al. / Solid-State Electronics 48 (2004) 1837–1842
+
(C) Rc (NiSi-N SD) 1
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SD-RTA:O -AN 2
-2 10
15
0
2 10
15
normalized SD-dose(P)
Fig. 9. Comparison of Teff (a), Lgate [lm] at Ioff ¼ 3e8 A/lm (b), and contact resistance (Rc ) between the NiSi and the Nþ sourcedrain (NiSi-Nþ SD) (c) between N2 -annealing (N2 -AN) and O2 -annealing (O2 -AN) for LTP NMOS.
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4. Conclusions
0.06 0.055
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delta-Teff[nm] (- SD-RTA:N -AN)
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0.045
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Lgate[ µm]@Ioff=3e-8[A/µm]
0.04
0.03
We described a novel poly-Si gate engineering with a laser thermal process; we obtained high electrical activation to suppress gate depletion for high performance sub-40 nm CMOS devices. Back-end-of-line (BEOL) process optimization, essential for the suppression of dopant deactivation, is described with 11/7% (PMOS/ NMOS) enhancement of Ion current and 0.1/0.06 nm (PMOS/NMOS) improvement of Teff . In addition, a novel SD-RTA process with a small O2 flux suppresses dopant dose loss for phosphorous and improves the Ion current by 5% for NMOS device with no penalty for PMOS device performance.
SD-RTA:N -AN SD-RTA:O -AN 2
2
Fig. 11. Comparison of Lgate at Ioff ¼ 3e 8 A/lm and Teff between N2 -AN and O2 -AN for LTP PMOS.
0.4 0.3
2
LTP(0.8J/cm ) SD-RTA:O2-AN
Vth [V]
0.2
Acknowledgements The authors would like to thank Y. Tada and S. Kodama of Fujitsu Laboratories for SIMS and TEM measurements and Process Development Department and Manufacturing Technology Department of Fujitsu Ltd., for device fabrication.
Vd=1.0V
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References
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Lgate [µm]
Fig. 12. Vth-rolloff characteristics of LTP NMOS and PMOS with an SD-RTA:O2 -AN and an optimized BEOL process.
at Ioff ¼ 3e8 A/lm by using the O2 -AN process. In the case of the PMOS device, we see no difference between N2 -AN and O2 -AN processes (Fig. 11). This is because we have carefully chose the O2 flux condition to avoid severe oxidation-enhanced diffusion (OED) for boron. Fig. 12 shows the threshold voltage (Vth) rolloff characteristics for optimized LTP NMOS and PMOS device, which shows good suppression of short channel effects down to sub-40 nm gate length.
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