Numerical simulation and experimental verification of vacuum directional solidification process for multicrystalline silicon

Accepted Manuscript Numerical simulation and experimental verification of vacuum directional solidification process for multicrystalline silicon Guoqiang Lv, Daotong Chen, Xi Yang, Wenhui Ma, Tao Luo, Kuixianai Wei, Yang Zhou PII:

S0042-207X(15)00109-8

DOI:

10.1016/j.vacuum.2015.03.009

Reference:

VAC 6591

To appear in:

Vacuum

Received Date: 12 January 2015 Revised Date:

6 March 2015

Accepted Date: 11 March 2015

Please cite this article as: Lv G, Chen D, Yang X, Ma W, Luo T, Wei K, Zhou Y, Numerical simulation and experimental verification of vacuum directional solidification process for multicrystalline silicon, Vaccum (2015), doi: 10.1016/j.vacuum.2015.03.009. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

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Numerical simulation and experimental verification of vacuum directional solidification process for multicrystalline silicon Guoqiang Lv a,c, Daotong Chen a,c, Xi Yang a,b,c, Wenhui Ma a,b,c*, Tao Luo a,b,c,

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Kuixianai Wei a,b,c, Yang Zhou a,b,c

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(a. Faculty of Metallurgical and Energy Engineering, Kunming University of Science and Technology, Kunming 650093, China; b. State Key Laboratory of Complex Nonferrous Metal Resources Cleaning Utilization in Yunnan Province/The National Engineering Laboratory for Vacuum Metallurgy, Kunming University of Science and Technology, Kunming 650093, China; c. Engineering Research Center for Silicon Metallurgy and Silicon Materials of Yunnan Provincial Universities, Kunming 650093, China;) *

Corresponding author. Tel.: +86 871 65161583; fax: +86 871 65107208.

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E-mail address: [email protected] (G. Lv), [email protected] (W. Ma).

Abstract

In this paper, a transient numerical model was applied to simulate the vacuum directional solidification (VDS) process of multicrystalline silicon (mc-Si) under

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different pulling-down rates, and the evolution of temperature distribution, thermal stresses and shape of solid/liquid (s/l) interface were simulated and analyzed. The experiments, such as the content and distribution of metal impurity, the crystal growth orientation and quality of mc-Si ingot were investigated to evaluate and validate the

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relationship between the thermal stresses and shape of s/l interface with simulation results. The results show that thermal stress, shape of interface s/l and temperature

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distribution in the silicon is determined by the thermal conditions in the furnace during the VDS process, and the crystal growth quality of mc-Si ingot relates closely to these factors. An appropriate pulling-down rate can satisfy thermal conditions to provide ideal temperature gradient in the silicon with lower thermal stresses and suitable s/l interface. We found that the mc-Si ingot produced by VDS process with pulling-down rate of 10 µm·s-1 had a larger grain size, a vertical columnar structure and an ideal efficiency of the impurity removal. Key words: Numerical simulation; Vacuum directional solidification; Multicrystalline silicon

ACCEPTED MANUSCRIPT 1. Introduction The metallurgical route is one of the most powerful and promising method in preparation of solar grade silicon (SoG-Si) directly from metallurgical grade silicon (MG-Si) because of its energy conservation and emission reduction [1]. The VDS technology is an effective method widely applied to remove metal impurities (such as

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Fe, Al, Ca, Ti, etc.) in silicon ingot casting via metallurgical method [2-3].

The distribution characteristics of metal impurities and the microstructures such as crystal type, grain size and defects of mc-Si ingot are determined by the

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temperature distribution and control of heat flow during the VDS process, so the heat transfer characteristics in which are worthy of in-depth study [4-7]. However, it’s difficult to measure and observe directly some important data in silicon material

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through experimental means during the VDS process, such as the temperature distribution, the shape and transformation of s/l interface, the flow pattern of silicon melt and the thermal stresses within silicon ingot. Numerical simulation makes a effective method for the study of the VDS for mc-Si. Over the years, many studies on analysis and optimization of solidification process of crystalline silicon for solar cells

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have been carried out [8-13]. Recently, numerical simulation is adopted for solving thermal stresses and the shape and transformation of s/l interface of the mc-Silicon during DS process. L.J. Liu et al. [14-16] performed numerical simulations and reported several improvement measures of DS furnace from the view of convection

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and mass transfer based on thermal field. They also obtained that thermal stresses can be reduced by a longer solidification time, and a crucible with large thermal

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expansion coefficient is recommended. C.E. Chang [17] confirmed that the shape of s/l interface can be adjusted by changing the temperature of the heaters. H. Miyazawa et al. [18] numerically investigated the influence factors on interface shape in DS Process and Y. Delannoy et al. [19] simulated the mc-Si furnace using 3D dynamic mesh and had put forward some control methods of the interface, in order to improve the quality of crystal. Although there have been some reports of study on thermal stresses or s/l interface shape relating to temperature field, the results of these reports are not of comprehensive considering of the influencing factors on crystal quality. In this paper,

ACCEPTED MANUSCRIPT a transient numerical model was applied to simulate the VDS process for mc-Si under different pulling-down rates, and the evolution of temperature distribution, thermal stresses and shape of s/l interface were simulated and analyzed. Experiments were carried out, and the distribution and existence form of metal impurities as well as the growth orientation and quality of crystal were investigated to evaluate and validate the

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relationship between the thermal stresses and the s/l interface shape with simulation results.

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2. Model description

Fig. 1. Model configuration for the cross-sectional area of the vertical furnace system

Fig. 1 shows the configuration and computation grids of a VDS furnace for 2D

global analysis with cylindrical crucibles. The system consists of quartz crucible, graphite susceptor, exchange block, graphite heaters, insulations, water cooled plate and furnace walls. The silicon feed materials are loaded into crucible with the diameter of 13 cm and height of 25 cm. During the VDS process, a suitable temperature gradient in the silicon material is maintained by adjusting the heating power and slowly moving components (crucible, susceptor, exchange block and water cooled plate) downwards with a constant pulling-down rate. Thermocouple 1 (TC1) is

ACCEPTED MANUSCRIPT installed in the middle of upper and lower heater, while thermocouple 2 (TC2) is installed between the lower heater and the bottom of the side insulation. The automatic temperature controlling system will adjust heater power output to control the temperatures of TC1 and TC2 to match the pre-set values. The main assumptions in this model are as follows: (1) the convective movement of the free space airflow is

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ignored because the inside of furnace is in a vacuum condition, (2) the flow in silicon melt is mainly natural convection caused by the density changes which has less effect on the m/c interface, (3) all radiative surfaces are diffuse-gray, (4) the heat flux is

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led-out by the cooling water in the water cooled plate under the exchange block during the VDS process. The upper and the underside surface of the water cooled plate are set continuity boundary condition and constant temperature boundary

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condition, respectively.

Governing equations of the heat transfer in all components can be described as: ∂T (1) ρC p = ∇ ( k ∇T ) + Q ∂t where ρ, Cp, and T are density, specific heat capacity, and temperature, respectively. The parameter k is thermal conductivity, and Q is the heat source term. The radiative

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heat exchanges between all gray and diffuse surfaces in the furnace were calculated by following equations:

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r − n ( − k ∇ T ) = ε (G − σ T 4 ) (1 − ε ) G = J − ε σ T

4

(2) (3)

where ε is the emissivity, G is irradiation, σ is called the blackbody radiation constant;

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J is radiosity. It is very important to accurately simulate the s/l interface for the transient simulation of VDS process. The s/l interface plot is theoretically the isotherm of 1685 K, which is the melting point Tm of silicon. With consideration of the calculation of the solidification latent heat, a dynamic interface tracking method was used. The release of latent heat was considered through the change in ∆H (enthalpy). In addition, the specific heat capacity Cp also changed considerably during the transition. To account for the latent heat related to the phase transition, we replaced Cp in the heat equation with (Cp+δ∆H), where ∆H is the latent heat of the transition and δ is a Gaussian curve given by

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exp[ − (T − Tm ) 2 / ( ∆ T ) 2 ] ∆T π

(4)

where Tm is the melting point (1685 K) and ∆T denotes half of the transition temperature span which was set to 0.01 K in this case. The change in specific heat can

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be approximated as ∆Cp=∆H/T, and represented by using software’s built-in smoothed Heaviside step function. A fraction of liquid phase B is induced for dynamic meshing and interface tracking, given by

(5)

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T > Tm + ∆T 1,  B = (T − Tm + ∆T ) / (2∆T ), (Tm − ∆T ) ≤ T ≤ (Tm + ∆T )  T < Tm − ∆T 0,

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The distribution of B reflects directly the position and shape of the solid/liquid interface (Actually, either to plot with the isotherm of Tm or from the distribution of B, we get the same interface shapes since the temperature span ∆T is rather small). The stress–strain relation for thermo-elastic solid body can be given by the following formulation:

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 σ r   C11 C12 C13 0   ε r − α r (T − Tref )   σ z   C12 C22 C23 0   ε z − α z (T − Tref )   σθ  =  C13 C23 C33 0   εθ − αθ (T − Tref )  τ   0 0  0 C44  γ rz  rz    

(6)

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In the above equation, αr、αz and αθ are the thermal expansion coefficient, and αr = αz = αθ = 2.6×10-6 K-1, Cij is the elastic coefficient of a silicon crystal. Silicon

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crystal has a cubic structure and there are only three elastic coefficients C11, C12 and C44. So all other coefficients can be expressed as C11 = C22 = C33, C12 = C13 = C23. Thermo-elastic stress analysis in the axisymmetric cylindrical coordinate system can be performed by using a displacement-based model [20], and magnitude of the gravity in the crystal is negligible compared to that of thermal stress, so the axisymmetric elastic stresses are governed by the following equilibrium equations:

σ 1 ∂ ∂τ (rσ r ) + rz − θ = 0 r ∂r ∂z r

(7)

ACCEPTED MANUSCRIPT ∂σ z 1 ∂ ( rτ rz ) + =0 r ∂r ∂z

(8)

where σr, σz and σθ are normal stresses in the radial, axial and azimuthal directions, respectively, and τrz is the shear stress. The strain–stress relationships are required for the enclosure of the model, and can be denoted by

∂u , ∂r

εz =

∂v , ∂r

u r

εθ = ,

∂u ∂v + ∂z ∂r

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εr =

ε rz =

(9)

where u and ν are displacement components in the radial and axial directions,

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respectively. The thermal stresses equations can be calculated associated with boundary conditions. The m/c interface can move freely and were treated as no

r r

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traction boundary, σ n = 0 . The axisymmetric boundary condition v=0, ∂u / ∂n = 0 was applied to the axial center. The ingot/crucible wall interfaces were rigid boundary, and the displacements u and v on the interface were set to zero, which means the crucible constraint is considered strictly. After the calculation of stress components, the von Mises stress for an axisymmetric geometry can be obtained by (10)

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σ von

(σ r − σ z )2 + (σθ − σ r )2 + (σθ − σ z )2 + 6τ rz2 = 2

The calculation of CRSS for silicon is as given in Ref [21-22], which is σcrss = [exp(10.55+10147/T)] ×10-7. When σvon ≤ σcrss，the excessive stress σex = 0；while the

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σvon > σcrss，the σex = σvon - σcrss. Through calculation, the σcrss compared with σvon is quite small, so we use von Mises stress directly to represent the stress level during the

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solidification process. The material properties are listed in Table 1 for the simulation. Table 1. Material properties used in the simulation

Physical property Silicon solid Density Thermal conductivity Specific heat Latent heat Young's modulus Poisson's ratio Emissivity Silicon melt Density

Value

Unit

2330 75 1000 1800 170 0.28 0.5

kg/m3 W/mK J/kgK KJ/kg GPa

2520

kg/m3

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1710 100 1800 0.8

kg/m3 W/mK J/kgK

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1800 100 1800 0.9

kg/m3 W/mK J/kgK

kg/m3 W/mK J/kgK)

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200 0.045 500 0.2

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60 890

7900 15 477 0.2

kg/m3 W/mK J/kgK

1000 60 4185

kg/m3 W/mK J/kgK

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Thermal conductivity Specific heat Crucible Density Thermal conductivity Specific heat Emissivity Insulators Density Thermal conductivity Specific heat Emissivity Heater Density Thermal conductivity Specific heat Emissivity Chamber Density Thermal conductivity Specific heat Emissivity Cooling water Density Thermal conductivity Specific heat

3. Results and discussion

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Dynamic simulation is carried out by using the commercial software COMSOL Multiphysics 4.2a to study the transient process of VDS at

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different pulling-down rates of 5 µ m· s -1 , 10 µ m· s -1 and 15 µ m· s -1 , and the evolution of temperature distribution, thermal stresses and shape of s/l interface were simulated and analyzed. Experimental verifications on the content, distribution and existence form of metal impurities, as well as the growth orientation and quality of mc-Si crystal were carried out.

3.1 Thermal stresses and temperature distribution The temperature and Von Mises stresses distribution of silicon for 0.25 and 1.0 solidification fractions at different pulling-down rates are shown in Figs. 2-4, respectively. As shown in Figs. 2-4, we can found that stresses occurs during the

ACCEPTED MANUSCRIPT whole VDS process, and the stress magnitudes are higher in the peripheral and bottom region than that in the internal region in VDS process; along with the solidification of melt, the maximum stresses gradually concentrated to the peripheral region, i.e. the adjacencies of crucible inner wall. Time solution also reveals that thermal stresses increased as the melt solidified because the temperature difference in ingot increased

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as the melt solidified. By comparison of Figs. 2-4 it can be found that the stresses and temperatures within solid silicon under different pulling down rates are of very similar profiles but quite different values. At a same solid fraction, the axial temperature gradient in crucible and the stresses in silicon are the largest while solidified under the

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rate of 15 µm·s-1, the smallest for 5 µm·s-1 and intermediate for 10 µm·s-1. Such results indicate that higher solidification rate will enlarge the axial temperature

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gradient in crucible and thereby increase the stresses within solid silicon. Fig. 5 shows the maximum Von Mises stresses of silicon at the different solidification fractions with the different pulling-down rates. We can find that the maximum Von Mises stresses increased as the pulling-down rate and

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the solidification fractions increased, respectively.

Fig. 2. Temperature (left) and Von Mises stress (right) distributions in the silicon during VDS process with pulling-down rate of 5 µm·s-1 at different solid fractions: (a) 0.25, (b) 1.0.

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Fig. 3. Temperature (left) and Von Mises stress (right) distributions in the silicon during VDS

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process with pulling-down rate of 10 µm·s at different solid fractions: (a) 0.25, (b) 1.0.

Fig. 4. Temperature (left) and Von Mises stress (right) distributions in the silicon during VDS -1

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process with pulling-down rate of 15 µm·s at different solid fractions: (a) 0.25, (b) 1.0.

Fig. 5. Maximum Von Mises stresses in silicon at different solidification fractions with different pulling-down rates.

ACCEPTED MANUSCRIPT 3.2 S/l interface shape and crystal growth orientation S/l interface shapes of different solidification fractions for 0.25, 0.5 and 0.75 solidification fractions under different pulling-down rates are shown in Fig. 6. When the solidification interface is convex, large bubbles are likely to form in the crystals

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and generate massive defects; while the solidification interface is concave, fine-grained zones are likely to remain and impurities and pores are likely to be included, likewise causing massive defects; a flat solidification interface is beneficial for the removal of impurities, elimination of defects, reducing of thermal stresses and

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formation of vertical columnar grains [23]. Thus, in terms of removing impurities, eliminating defects (such as dislocations) and reducing thermal stresses, a flat

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solidification interface is the most ideal [24].

Fig. 6. The s/l interface shape for 0.25, 0.5, and 0.75 solidification fractions under different pulling-down rates: (a) 5 µm· s -1 , (b) 10 µm· s -1 , (c) 15 µm· s -1 .

According to the judgment criterion of solidification interface shape, the plot is

more convex in Fig. 6(c), but flatter in Fig. 6(a) and Fig. 6(b) for each solidification fraction respectively; at the same time, in a grown condition as Fig. 6(a), the interface would experience a transformation from concave in the initial stage of solidification to relatively convex in the end. Such transformation is not conductive to the smooth growth of crystal, which is in accord with our experimental result that the ingot grown under the rate of 5 µm·s-1 has smaller grain size. Hence we deem that the

ACCEPTED MANUSCRIPT experimental condition as Fig. 6(b) is optimal for growing crystals of the best quality. Usually (100) wafers are textured on the wafer surface to improve light trapping properties of solar cells. Texturing is accomplished by chemical etching and pyramidal textures based on intersecting (111) equivalent planes are uniformly formed

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on all over the wafer surface [25]. It is not conductive to the texturing of (100) wafers if the mc-Si has many crystallographic orientations because etching rate and textural morphologies are inhomogeneous in each grain. So mc-Si grown in homogeneous orientation is favorable.

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To investigate the crystal orientation under different growth conditions, nine silicon films as thick as 2 mm were chosen at 1/6, 3/6 and 5/6 of the height from the

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bottom along the axial direction of three silicon ingots solidified under different rates of 5, 10 and 15 µm·s-1 for X-ray diffraction (XRD) analysis. The detected XRD patterns are shown in Fig. 7, among which Fig. 7(a) shows the XRD patterns of the bottom of silicon ingots that grew in the initial stage of solidification. Under the rate of 5 µm·s-1, the ingot were dominated by grains with (220) and (311)-orientations

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accompanied with a few (111) grains. Under the rate of 10 µm·s-1, as the supercooling of the crucible bottom increased, the growth rate of (111) was fastened but still slower than that of the (220) plane where the coarse grains grew, which means (220) grains dominated. Under the rate of 15 µm·s-1, the growth rate of (111) grains leaped as a

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consequence of further increased supercooling, thus the (111) grains, accompanied with (220), (311) and (331) grains, were favored in the bottom of the ingot. The

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results imply that there are many grain dendrites grown in the initial stage under all three pulling-down rates. Fig. 7(b) shows the XRD patterns of the middle part of silicon ingots that grew in

the middle stage of solidification. Under the rate of 5 µm·s-1, the (220) grains and (311) grains gradually stopped growing with the growth of crystal, the (111) grains which grew the slowest were favored, and fresh (422) grains emerged. Under the rate of 10 µm·s-1, (111) grains dominated in the middle part, while the growth of (220) grains and (311) grains died out, and the diffraction peak intensity of (331) grains is so weak. Similarly, under the rate of 15 µm·s-1, the middle part of the ingot were

ACCEPTED MANUSCRIPT dominated by (111) grains while the growth of (220), (311) and (331) grains died out gradually. Fig. 7(c) shows the XRD patterns of the upper part of silicon ingots that grew in the late stage of solidification. Under the rate of 5 µm·s-1, (111) grains still

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dominated in the upper part of the ingot, the diffraction peak intensity of (220) grains weakened more and was likely to fade out while fresh (422) grains occurred, and. Under the rate of 10 µm·s-1, (111) grains prevailed while the growth of (311) grains and the newly favored (422) grains died out. Under the rate of 15 µm·s-1, (111) grains

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kept dominant, but some (311) grains and (422) grains newly emerged. By comparison between the plots in Fig. (7) we can find that the mc-Si grown in more

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homogeneous orientation under the rate of 10 µm·s-1 than the other conditions.

Fig. 7. XRD spectrum of pilot-scale multicrystalline silicon at different location with different solidification rates: (a) 1/6, (b) 3/6 and (c) 5/6 of the height from bottom

3.3 Crystal quality of the silicon ingots However, from the viewpoint of crystal quality, the growth of (111) grains needs to be avoided because {111} planes have more slip systems to be activated for the generation of dislocations [26]. Since (111) grains dominate in the growth under all

ACCEPTED MANUSCRIPT three pulling-down rates, it requires larger grain size to reduce the amount of grains and grain boundaries. Fig. 8 shows the crystal morphology in longitudinal cross sections of the silicon ingots after being cut, polished and cleaned, and the grain growth directions were marked by arrows. It is found that vertical growth crystal morphology of the silicon ingots is best by the pulling-down rate of 10 µm·s-1 (Fig.

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8(b)).

In Fig. 8(a), though the grain sizes of the columnar crystals are relatively large, the grains are oriented diversely from the bottom up rather than vertically; the crystals

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nucleated at the bottom, ended on the crucible wall. This is because in the beginning of pulling down the crucible, the heat flux direction was oriented from the crucible to

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the inside of silicon melt; and as a consequence of slow solidification rate, the heat compensation from the heater was more than the heat dissipation through the crucible, which caused the temperature of the crucible bottom was higher in the edge but lower in the center, resulting the nucleation occurred firstly near the center of crucible bottom. As the crucible fell downward, columnar crystals expanded steady into the liquid, and finally grew diversely from the central crucible to the wall, appearing the

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morphology shown in Fig. 8(a). The columnar crystals shown in Fig. 8(b) are mainly oriented vertical to the crucible bottom because the faster solidification rate resulted in an approximate balance between the heat compensation from the heater and the

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dissipation through the crucible, thus the supercooling degrees of different parts of the bottom were almost the same, crystals nucleated and grew simultaneously from all

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areas of the bottom, and finally formed such morphology of vertical columnar crystals.

Under the solidification rate of 15 µm·s-1, the heat compensation from the heater

was less than the heat dissipation through the crucible, consequently the supercooling degree of the silicon melt adjacent the crucible wall was larger than that adjacent to the solidification front. Thus crystals nucleated firstly near the crucible wall. Moreover, the released laten heat of the front melt caused partial remelting of some crystals, which increased the dissociative grains and reduced columnar crystals, making the grains disordered and irregular as shown in Fig. 8(c). The crystal growth

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three different solidification rates.

Fig. 8. Crystal morphology of the silicon ingots in a longitudinal sectional with different -1

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pulling-down rates: (a) 5 µ m· s , (b) 10 µ m· s , (c) 15 µ m· s .

It can be concluded from Table 2 that regardless of the solidification rates, the

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average grain sizes increase gradually form 1/6 of the height of ingots at bottom up to 5/6 of the height. The ingot solidified under 10 µm·s-1 has the largest average grain size comparing to the other two conditions. When the solidification rate is 5 µm·s-1, silicon crystals started nucleation at the central bottom and grew towards the wall of crucible. Under 10 µm·s-1, the nucleation occurred on the whole plane of the crucible bottom and the solidification front was flat, and the crystallization was less affected by the nucleation on the crucible wall. Thus the largest grains were obtained in this situation. Under 15 µm·s-1, due to the cooling rate was too fast, the supercooling of the bottom and wall of crucible was too large; consequently the nucleation ratio and

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Grain size (mm)

Rate 2/6 of ingot

3/6 of ingot

4/6 of ingot

5

1.88

2.06

2.36

10

2.03

2.44

2.83

15

1.31

1.48

1.71

2.71

3.10

2.00

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3.4 Purification efficiency

5/6 of ingot

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(µ m •s-1)

Scanning electron microscope (SEM) and energy dispersive spectroscopy (EDS)

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were used to analyze the concentration profile and presence pattern of metallic impurities in the mc-Si ingot cast under solidification rate of 10 µm·s-1. The results show that impurities distribute unevenly in form of metal particles included in the silicon ingot. These metal particles have sizes in the range of 5 ~ 45 µm, as shown in Fig. 9. The compositions of the metal particles were analyzed by EDS and metal

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elements as Fe, Al, Ca and Ti were detected. In the solidification process, the impurities segregated at the s/l interface due to the relatively overlarge interfacial tension force and temperature gradient, then nucleated and grew into particles at the

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solidification front before being engulfed by silicon crystal as inclusions. Such inclusions are not only the optical scattering centers, but also the inducements of

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dislocations which are fatal for the photoelectric conversion efficiency of solar cell.

Fig. 9. SEM micrographs and EDS chart of impurities after directional solidification

ACCEPTED MANUSCRIPT VDS experiments were conducted using MG-Si powder in a pilot-scale furnace and silicon ingots under different solidification rates. Silicon wafers were cut down from each ingot at 1/6 of the height from bottom and analyzed by inductively coupled plasma mass spectrometry (ICP-MS). Detected results are as listed in Table 3. Table 3. Impurity content of 1/6 of silicon ingots with different solidification rates Solidification

Experimental

Impurities in raw

content

rate (µ m·s-1)

values (ppmw)

material (ppmw)

5

23

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Impurity

Removal efficiency 98.11%

1220

10

1.3

5

6.7

99.89%

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Fe

99.40%

1120

Al 9.3

5

0.1

Ti

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10

99.17% 99.92%

120

10

0.01

99.99%

In the sample from the ingot solidified with the rate of 5 µm·s-1, the content of metal impurities Fe, Ti and Al decreased to 23 ppmw, 6.7 ppmw and 0.1 ppmw, indicating the one-time removal efficiencies of 98.11%, 99.40% and 99.92%,

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respectively. While in the sample solidified under the rate of 10 µm·s-1, the content of metal impurities Fe, Ti and Al decreased to 1.3 ppmw, 9.3 ppmw and 0.01 ppmw with one-time removal efficiencies of 99.89%, 99.17% and 99.99%, respectively; among

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all impurities, Ti was removed the most effectively and can meet the requirement for solar grade silicon. Thus, the impurity removal efficiency of the solidification rate of

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10 µm·s-1 is better than that of 5 µm·s-1.

4. Conclusion

We performed a transient simulation to investigate the VDS process for mc-Si.

The simulation results show a satisfactory agreement with the experiments. The results indicate that thermal stresses, shape of interface s/l and temperature distribution in the silicon are determined by the thermal conditions in the furnace during the VDS process, and the crystal growth quality of mc-Si ingot related closely to these factors. An appropriate pulling-down rate can satisfy thermal conditions to provide ideal temperature gradient in the silicon with lower thermal stresses and

ACCEPTED MANUSCRIPT suitable s/l interface. We found that the mc-Si ingot produced by VDS process with pulling-down rate of 10 µm·s-1 had a larger average grain size, a vertical columnar structure and ideal efficiency of the impurity removal. Therefore, we can expect to manipulate the crystal quality of silicon ingot for solar cells by controlling the thermal

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stresses and crystallographic orientations during the vacuum solidification process.

Acknowledgments

This work is supported by NSFC project (Nos.51466005 and U1137601), the Key project of Yunnan Provincial Department of Education (2013Z122), the Graduate

training

Foundation

of

Kunming

of

Science

and

Technology

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(KKZ3201352011).

University

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project of Yunnan Provincial Department of Education (2014J020), and the talent

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ACCEPTED MANUSCRIPT Highlights

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►Comprehensively investigations into the vacuum directional solidification process for multicrystalline silicon were conducted. ►Proper thermal condition that meets the demands of high-quality crystal production can be obtained by adjusting the growth rate. ►The simulation and experimental results were in accord with each other.