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Occurrence of giant current fluctuations in 2D tunnel junction arrays
Solid-State Electronics 48 (2004) 445–452 www.elsevier.com/locate/sse
Occurrence of giant current fluctuations in 2D tunnel junction arrays A.S. Cordan
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ERM/PHASE, ENSPS, Bd S ebastien Brant, F67400 Illkirch, France Received 1 February 2003; received in revised form 1 July 2003; accepted 1 September 2003
Abstract Some 2D arrays composed of nanometer-size islands exhibit very large fluctuations in the current responses. The model and numerical tool presented here show that such devices are characterized by a dominant conduction path. In this paper, we explain the origin of this important noise, and suggest a design modification to reduce it. Then the same model is applied to a floating gate array (FG) on top of a tiny channel (FG-MOS). We show that in order to avoid giant current variations in the read process, large tunnel junctions are prerequisite between FG and channel, yet also between dots within the FG, even if the latter process is not correlated to the FG total retention time. 2003 Elsevier Ltd. All rights reserved. Keywords: Single electron devices; Tunneling; Coulomb blockade; Noise; Multi-dot floating gate
1. Introduction Since more than 10 years, the decreasing dimensions of the devices in microelectronics have led to important quantum effects. The aim is to reach the ultimate performance for future electronic ultra-large scale integrated circuits, by controlling electrons one by one. Two main ways are considered, either the single electron transistor (SET) [1–5] or the ultimate metal-oxidesemiconductor transistor (MOS) [6,7]. We will focus here on SET arrays: they are based on the Coulomb blockade [8–10] of a single charge on a tiny dot between electrodes. In order to extend the maximum operating temperature up to 300 K, we will see that dot and junction dimensions have to be near to 1 nm. Either single dot arrays or multi-dot arrays have been used [11– 16], obtained from different fabrication techniques [15, 17–22]. Yet as limits of the lithography technique are in the 10 nm range, no precise dimensional control could be achieved up to now for devices with only one island.
*
Tel.: +33-3-90-24-44-25; fax: +33-3-90-24-45-45. E-mail address: [email protected] (A.S. Cordan).
The most promising way appears to include small one- or two-dimensional (1D/2D) arrays of nanodots between electrodes. Island radii must still lie in the r ’ 1 nm range, but now the distance between the drain and source electrodes is at least equal to 10 nm. The additional expected advantages of dot arrays compared to single island devices are a larger threshold voltage Vth , and a higher maximal operating temperature for a given mean value of island radii, noted r. We will base the model on metallic Au islands on a SiO2 insulating substrate, as previous calculations using a similar model have been successfully compared to experimental devices fabricated with this technology [15]. Moreover, the latter was developed in order to be compatible with the Si technology already on hand, at least on the laboratory level. As aforementioned, dot sizes and junction lengths cannot be perfectly controlled, therefore the resulting arrays are necessarily disordered. Only the dimensions between drain and source electrodes, and also the array width, are controllable through a high precision lithography process. Then we will evaluate numerically the current I as a function of time, for disordered 1D and 2D tunnel multi-junction arrays. We will see that in main random arrays, only quantum shot noise is present.
0038-1101/$ - see front matter 2003 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2003.09.010
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A.S. Cordan / Solid-State Electronics 48 (2004) 445–452
Nevertheless, some 2D devices exhibit very large fluctuations [23]. The aim is on one hand to find the origin of such phenomena in these devices, and on the other hand, to propose a design modification in order to strongly reduce those large fluctuations, highly detrimental to any application. Moreover, the numerical tool can also yield to IðtÞ characteristics of more complex structures like multi-dot floating gate MOS devices (FG-MOS). In a FG-MOS, a floating gate is buried within the insulator, between the channel and the gate in the MOS transistor. In the model, we will consider the channel as a highly conducting array surrounded by blocked charges on the FG array. The Coulomb blockade effect will contribute to the retention ability of extra charges transferred from the channel to the dots in the floating gate. We will show that important noise level shifts may also occur in that case. We will present the model in Section 2, and explain the simulation method in Section 3. IðtÞ results will be discussed in Section 4, followed by the conclusion.
2. Model We consider nanodot arrays between source and drain electrodes, and a gate as drawn in Fig. 1. Arrays are composed of Au dots related by tunnel junctions on an insulator substrate (SiO2 ). Three physical phenomena could yield to electrical transport across the structures, namely the conductivity of materials, the thermoelectronic effect, and the tunnel effect. However, the material linking the conductors is an insulator with a resulting barrier height much larger than thermal activation energy at room temperature: as a consequence, only the tunnel transport takes place here. The SET arrays studied in this paper are based on the Coulomb blockade of a single charge on a tiny dot. The most simple way to explain its principle is to consider a single dot between electrodes. An electron coming onto this island involves a charging energy EC ¼ e2 =2C, where C stands for the equivalent dot capacitance. In order to hold the charge carrier on the dot up to room temper-
Junctions S
Dots D
G Fig. 1. Diagram of a 2D array. S, D, and G stand respectively for source, drain, and gate electrodes.
ature, EC must exceed by far the energy of thermal fluctuations kB T , i.e. EC > 0:1 eV, which requires an electron unlocking threshold voltage Vth larger than 0.1 V: dot and junction dimensions have then to lie near to 1 nm. For SET composed of either a single dot or a dot array, the threshold voltage Vth is defined as follows: if the applied voltage between the drain and source electrodes, noted VDS , is less than Vth , then the tunnel current IDS is not significant and the device stands in the Coulomb blockade regime. The gate electrode modulates this effect. As aforementioned, nanodot arrays can show larger values of the threshold voltage with respect to single dot devices. The starting-point was the distribution of junction lengths and dot radii. Experimental analysis by scanning electron microscope (SEM) revealed an important dispersion of inter-dot distances as compared to the one coming from dot radii [15,21]. Therefore in order to speed up calculation times, we consider the same radius r for all islands and take the geometrical disorder into account through the inter-dot distances fdj g. To be coherent with experimental conditions concerning arrays of Au dots on a SiO2 substrate [24], we take r ’ 3 nm [21]. However the model enables to consider random values of r. A tunnel junction j is characterized by a capacitance Cj and a tunnel resistance RTj , that we have calculated as a function of r, dj , and Au and SiO2 structural parameters [16,21]. In the model, each junction capacitance Cj is given by the influence capacitance between two dots (charge image method [25]) dj Cj ¼ 4p0 r r sinh acosh 1 þ 2r 1 1 X dj sinh 2n acosh 1 þ : 2r n¼1
ð1Þ
Then, the capacitance matrix C of the whole system can be constructed. Diagonal elements of C are the sum of all junction capacitances associated with a dot, and offdiagonal elements are the opposite of junction capacitance linking two neighboring dots. We have neglected the stray capacitances of islands as the SiO2 substrate of the experimental devices is thick enough. The calculation of tunneling transmission values is a challenge when a complex structure cannot be reduced to a one-dimensional case [26,27]. For a given junction, we restrict the problem to the tunneling through rectangular barriers between two dots: it is justified as long as / eVDS , / being the effective barrier height. A first approximation is to use a simple ballistic model [28], as the electron Fermi wave vector kF is much larger than r 1 . The expression of the tunnel resistance RTj is written as
A.S. Cordan / Solid-State Electronics 48 (2004) 445–452
RTj ¼
1 h3 64p2 me2
EF þ U EF
2
j Ur
expð2jdj Þ rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 r 1 1 rþd j
ð2Þ
pffiffiffiffiffiffiffiffiffiffi with j ¼ 2mU=h; the second part corresponds to the geometrical factor, and EF is the Fermi energy. Inter-dot distances fdj g are taken in the ½0:3; 0:9 nm range. Therefore, as tunnel resistances vary exponentially with inter-dot distances, the span of resistance values is very important (more than eight orders of magnitude). Calculations have been carried out in the orthodox theory frame, developed by Averin and Likharev [29]. Briefly, it is based on the following hypotheses: • a metallic island is considered as an ideal metal with an energy quasi-continuum. This hypothesis holds as long as dE kB T : dE is the energy gap between two successive states in islands; • electron localization on an island is assured when RTj RK ¼ h=e2 ’ 25:8 kX;
ð3Þ
where RK is the quantum resistance; • between two tunnel events, the system partially relaxes, charges are redistributed and equilibrium is reached before a new event occurs. Therefore the relaxation time is smaller than the time between two successive tunnel transfers; • cotunneling effects can be ignored if relation (3) is verified. Finally, electron tunneling through a tunnel junction j between two islands k and k 0 is characterized by a
forward tunnel transfer rate (Cþ j ) and a reverse one (Cj ), given by " #
DFj ðfnp gÞ 1
; Cj ðfnp gÞ ¼ ð4Þ RTj e2 1 exp DFj ðfnp gÞ=kB T where DFj corresponds to the free energy variation generated by this random tunnel effect, in the positive direction or in the opposite one. fnp g is the charge configuration on the dots before the tunnel transfer. DFj is calculated as follows DFj ¼ Ef Ei eðVk0 Vk Þ; Ef ¼ 12Qðfn0p gÞC 1 Qðfn0p gÞ; Ei ¼
447
vices with source and drain electrodes only. Therefore, we will calculate IðtÞ characteristics––i.e. the current IDS between S and D––for an electrical potential VDS applied between drain and source. Two types of arrays will be studied: 1D and 2D arrays between S and D, and arrays specially constructed in order to model a floating gate array near a semiconductor channel in a FG-MOS device. As IDS is a function of VDS only, the latter will correspond to a floating gate which is not biased by a gate voltage.
3. Simulation Since the aim was to account for disorder effects on metallic dot arrays, a specific simulator has been developed––based on a Monte Carlo approach––which includes a geometrical description of the array [16]. The Monte Carlo method for single-electron tunneling devices was first proposed by Mullen et al. [30] and Bakhvalov et al. [31]. Electron motions through tunnel junctions are randomly generated. Each event is associated with the junction j whose stability interval Dtj is minimal for a given charge configuration. As tunneling effect is a poissonian process, Dtj is obtained from the tunneling rate of Eq. (4) thanks to: Dtj ¼
lnðpj Þ ; C j
ð6Þ
where pj stands for the motion probability through junction j, and is randomly taken in 0; 1. Electron motions lead to the time evolution of charges QðtÞ and current IðtÞ across the device, for different bias voltages and temperature values. IðV Þ responses are then evaluated by averaging current values IðtÞ over t for a fixed voltage V ¼ VDS . We focus here on IðtÞ characteristics: calculations have been performed by considering Ne ¼ 103 electrons leaving the device for each simulated point, to be coherent with the experimental conditions which provided the first validation of the calculation [23]. Moreover, the applied voltage VDS has to be larger than the threshold voltage Vth at 0 K so that the system conducts. Finally, we do not take any external perturbation into account in the simulations, e.g. offset charges.
ð5Þ
1 Qðfnp gÞC 1 Qðfnp gÞ; 2
where fn0p g is the charge configuration on the dots after the tunnel event, Vk the potential of dot k, Q the charge vector (Qp ¼ enp ), and C the capacitance matrix. In this paper, we do not consider the gate electrode effect on electrical characteristics, as we first want to understand the important noise arising from some de-
4. Results and discussion 4.1. SET arrays In this first part, numerical results are presented for gateless SET devices composed of 1D and 2D arrays of M N metallic dots separated by tunnel junctions of variable lengths. M corresponds to the number of islands
A.S. Cordan / Solid-State Electronics 48 (2004) 445–452 260 1D 5x1 random array
255 250 Current I (pA)
in a row between the two electrodes, and N to the number of islands in the width of the device. For example, in 1D systems, N is equal to 1. We have limited the investigations on random disordered arrays to M; N 6 5 because of large computation times needed to isolate fluctuation occurrence. In fact, for SET, it is a realistic choice since useful devices will not involve larger arrays to avoid screening effects. Before the study of IðtÞ curves, we show in Fig. 2 an IðV Þ characteristic for a 1D random array of five islands at T ¼ 50 K. The Coulomb staircase structure is pronounced, with a threshold voltage Vth equal to 0.52 V. In the IðtÞ curves below, the temperature is fixed to 50 K, and we always take the applied voltage V outside the Coulomb blockade range. Concerning the current noise, only shot noise should appear for random 1D and 2D devices, as the tunnel effect consists in a random poissonian process. Thus we would pffiffiffiffiffi expect a relative noise limited to the value 1= Ne ’ 3%, corresponding to the Ne ¼ 103 electrons leaving the device. In Fig. 3, we first present IðtÞ results for the same random 1D array (M ¼ 5) than in Fig. 2, with an operating voltage taken equal to V ¼ 0:75 V: as anticipated, there is only shot noise. Moreover, all of the other 1D arrays we tested always followed the same trend. Secondly we consider 2D random arrays: they give rise to two distinct kinds of IðtÞ behaviors. Indeed in a first group, shot noise is again the main contribution–– as represented in Fig. 4 for a 5 · 5 device––while a second group exhibit large fluctuations in the current instead of shot noise only. Actually, we have found that all arrays of this last set are characterized by a dominant conduction path (DCP)––or minimal resistance path––as drawn in Fig. 5 for a 5 · 5 device. The line on this picture schematizes the DCP. If an extra charge is created on the DCP, it will be swept away.
245 240 235 230 225 220 215 210 0
2
4 6 -5 Time (10 s)
8
10
Fig. 3. IðtÞ curve for a 1D random array. The operating voltage is equal to 0.75 V, and T ¼ 50 K.
1.55 2D 5x5 random array 1.5 Current I (nA)
448
1.45 1.4 1.35 1.3 1.25 0
0.4
0.8 1.2 Time (10-5 s)
1.6
2
Fig. 4. IðtÞ curve for a 2D random array of the first group. The operating voltage is equal to 0.42 V, and T ¼ 50 K.
900 800
1D 5x1 random array
Intensity I (pA)
700 600
Fig. 5. Schema of a 2D array characterized by a dominant conduction path. The DCP is represented by the line.
500
Operating point
400 300 200 100 0 0
0.2
0.4
0.6 0.8 1 1.2 Applied voltage (V)
1.4
1.6
Fig. 2. IðV Þ characteristic for a 1D random array, at T ¼ 50 K. The operating voltage is taken equal to 0.75 V.
Fig. 6 shows the IðtÞ giant fluctuations for such an array. We have also evaluated the charge configurations, corresponding respectively to an IðtÞ reference level (a) and a higher one (b): in the (b) charge configuration–– compared to (a)––an extra charge is added on an island lying very near to the DCP, but not directly on it. This charge acts like a perturbation on the DCP as its retention time on the dot is longer than the DCP motion scale. Therefore, giant fluctuations can never be ob-
A.S. Cordan / Solid-State Electronics 48 (2004) 445–452
2D 5x5 array with DCP 4 Current I (nA)
b a
3.5 3 2.5 2 1.5 0
0.4
0.8 1.2 Time (10-5 s)
1.6
2
Fig. 6. IðtÞ curve for a 2D array of the second group. The operating voltage is equal to 0.36 V, and T ¼ 50 K. The configuration charge of noise level (a) does not contain any charge apart from the DCP, whereas for (b) level, one electron is added on a dot very near to the DCP.
served in the 1D arrays, as long as neither external perturbations nor gates are taken into account: as aforementioned, any excess charge on the line itself is quickly swept out. Notice that islands lying farther from the DCP can be implied too, but their effects are negligible and probably lost in the shot noise contribution. Results are reliable, as we have checked that the perturbing charge remains the same while at least 103 electrons leave the device. The noise observed here is analogous to the telegraph type [32–35], with random switching between several states. Another example is given in [36]: once low energy Heþ ions are directly deposited onto their multi-junction single electron transistor, IðtÞ discontinuities appear: they have been explained through the same process. Each jump in the IðtÞ curve is attributed to a single ion landing very close to one of the islands. In this paper, we only consider traps on islands. However the present analysis can include structural traps within the SiO2 insulator. A similar behavior has also been observed on the conduction signal of a silicon gated quantum wire, with a switching behavior ascribed to single electron trapping in the wire or the surrounding oxide [37]. The above calculations have shown that the trapping phenomenon does not happen in the wire itself, but in its vicinity. The number of states involved in the telegraph noise depends on the number of accessible levels in islands near to the DCP that are possible charge traps. As the disordered 2D arrays studied here are small, there are only few levels that cannot be uniformly distributed: thus, we do not expect a simple 1=f contribution. Once the origin of such phenomena was found, the aim was to propose a realistic solution to reduce these giant fluctuations in 2D arrays, evidently highly detri-
mental to any future application. We suggest to modify the design of the devices in a way such that no more island in the DCP vicinity would play the role of perturbing charge trapping, as electron transfer on the DCP would be slowed down and brought back to the same common time scale. With this end in view, the total resistances of the different paths should be almost the same. In principle, it requires a precise control on all tunnel junctions, that is technically not realistic up to now. As no other distance can be controlled, the only possibility would be to put larger tunnel resistances along one electrode, for instance by a self-aligned process. The IðtÞ curve obtained for a modified device is shown in Fig. 7. The device is based on the one studied in Fig. 6, except that junction lengths along one electrode are now larger and equal to 1.1 nm (wide endjunctions), with an operating voltage V ¼ 0:32 V: giant fluctuations are quenched, and only shot noise persists. The same result is obtained for arrays with random wide end-junctions. As a matter of fact, a slight modification is already adequate. We can also notice that even if this modification implies larger resistances and consequently smaller currents, their values still remain adequate for applications. 4.2. FG-MOS arrays In this second part, we turn now to more complex structures like multi-dot floating gate MOS, as drawn in Fig. 8. In this device, a classical current flows from the source to the drain through the semiconducting channel, but not through the floating gate. A charge transfer–– between the channel and the FG––is possible when the gate G is strongly biased. The Coulomb blockade effect contributes to the retention ability of extra charges on the FG dots. When the control gate voltage (between
0.068 2D 5x5 wide end-junction array 0.066 Current I (pA)
4.5
449
0.064 0.062 0.06 0.058 0.056 0
0.1
0.2 0.3 Time (s)
0.4
0.5
Fig. 7. IðtÞ curve for a 2D modified array. The operating voltage is equal to 0.32 V, and T ¼ 50 K.
A.S. Cordan / Solid-State Electronics 48 (2004) 445–452
Fig. 8. Diagram of a FG-MOS, with a floating gate of nanodots. S, D, and G stand respectively for the source, drain and gate electrodes, and FG for the floating gate.
gate and source electrodes) is varied, the addition of a charge onto the FG corresponds to a writing process, whereas the removal of a charge corresponds to an erasing process. By sensing the current difference between the two states––with and without FG charge––the stored information can be read. The straightforward calculation by means of Schr€ odinger–Poisson equations would lead to very cumbersome calculations as the number of finite element nodes would be very large for a realistic picture. Yet thanks to our approach, we have followed another way. Indeed, we are able to build specially designed devices in order to get the FG array effect on a biased semiconducting channel. This latter is modeled like easy paths, and the FG array like dots separated by wide tunnel junctions. We represent the channel by a small 2D array with small tunnel junctions (in the ½0:3; 0:5 nm range) that simulate the elementary Landauer channels and the energy barrier which originates from the confinement [6]. As a first approximation, we consider EC like an effect of the confinement of the carriers in the channel. Therefore we take implicitly the Poisson equation into account through Eqs. (5) and (1). If a voltage VDS ¼ 0:3 V is applied (larger than the threshold voltage), straightforward calculations lead to a number of channels Nch P 10 for a n-doped Si channel (height > 10 nm). However, in order to easily identify the charge transfers and to keep a reasonable computation time, we take Nch 6 2. The floating gate is represented by an array with wider tunnel junctions, as well between dots and channel, as between dots themselves (0.9 nm). The charge transfer should be possible when the gate is strongly biased, to add or remove charges on the FG. We put however much wider end gaps between the gate array and both source and drain (1.3 nm) to cut down any current flowing between source and drain through the floating gate itself. In the next IðtÞ curves, the voltage is only applied between source and drain electrodes, corresponding therefore to a reading process. As the current is again calculated from time intervals corresponding to 103 charges coming out, the shot noise should amount to 3%.
We have tested several devices at 50 K, varying in a systematic way transversal distances dtrans between the channel and the FG array, and longitudinal distances dlong between neighboring dots within the FG array. First, in Fig. 9, we have represented the IðtÞ curve associated with dtrans ¼ dlong ¼ 0:9 nm: giant fluctuations happen. In the reference level (a), the FG does not contain any electron; we have verified here that the higher level (b) results from one electron motion within the FG array, whereas the lower levels (c) and (d) correspond to one electron transfer from the FG array to the channel. In Fig. 10, dtrans is increased to 1.1 nm while dlong is kept to 0.9 nm: giant fluctuations show then a predominance of high levels, i.e. individual motions within the FG in that example. This result is not surprising, as larger dtrans values lead to higher tunnel resistances, and thus to decreasing transversal motion probabilities. These large chaotic level shifts in the current remain until both dtrans and dlong reach 1.3 nm at least. Above this value, the noise falls to 3%. Of course dtrans will obviously be designed following the requirements on the retention time s. However, we have shown that dlong is also relevant. It induces a variation in the read current of the same magnitude than for a charge transferred from FG to channel. To avoid it, we have proved that dlong has also to be enlarged. Moreover, if we consider non-rectangular barriers [6], these junctions must be slightly larger: this is coherent with dtrans P 1:6 nm for a reliable retention time [1]. In this paper, we have considered metallic nanodots. But the new hybrid structures, made of a regular MOS
5 Model of 2D FG-MOS b
4.5 Current I (nA)
450
a
4 3.5 3
c
2.5
d
2 0
1
2 3 Time (10-5 s)
4
5
Fig. 9. IðtÞ curve for a FG-MOS with only the floating gate and with dtrans ¼ dlong ¼ 0:9 nm (V ¼ 0:3 V and T ¼ 50 K). The configuration charge of noise level (a) does not contain any charge on the FG, whereas for (b) level, one electron has moved inside the FG, leaving a hole. Then, the configuration charge of (c) level corresponds to one transversal electron motion, and the same for (d) level.
A.S. Cordan / Solid-State Electronics 48 (2004) 445–452
distance (dtrans ), since the charge transfer inside the floating gate is evidently highly detrimental to memory applications. Therefore, the location of the nanocrystals in the oxide is predominant as a very small change in their distances (inside the FG, between the FG and the channel, between the FG and a gate electrode) will dramatically modify the memory properties.
4.8 Model of 2D FG-MOS b’ c’
Current I (nA)
4.4
451
4 a’ 3.6
5. Conclusion
3.2 2.8 2
3
4
5
Time (10-5 s)
Fig. 10. IðtÞ curve for a FG-MOS with only the floating gate and with dtrans ¼ 1:1 nm and dlong ¼ 0:9 nm (V ¼ 0:3 V and T ¼ 50 K). The configuration charge of noise level (a0 ) does not contain any charge on the FG. For (b0 ) level, one electron has moved inside the FG, leaving a hole, and the same for (c0 ) level.
transistor with a multi-dot floating gate, are rather fabricated with semiconducting nanodots, especially Si, as mature fabrication technologies for large scale integration circuits are available. Nanocrystals of Si have already been buried in the gate oxide of MOS transistors to form the FG [1,3]. Recently, floating gates consisting of Si nanocrystal layers were obtained through ultra-low energy Si implantation [38–40]. The nanocrystal mean radius is about 1.5 nm. The hope is that such devices will lead to high-storage density low-power memory applications, as only a few electrons are concerned against 105 for classical FLASH memory and because of the nanometer scale feature sizes. Of course, the Coulomb blockade condition is EC ¼ e2 =2C kB T , with T ¼ 300 K, thus EC and the threshold voltage need to be sufficiently large to keep a good memory control against thermal effects. But as Wong et al. have underlined it in their review [7], for Si storage dot sizes in the [3–6] nm range, the operating voltages do not exceed the [1–1.5] V range! The maximum oxide thickness between the floating gate and the control gate (that we did not take into account in our model) must be limited to reduce the gate voltage needed, and the minimum size should avoid leakage to the control gate: the optimal distance lies between 5–10 nm. Moreover, the oxide thickness between the channel and FG (dtrans ) depends on the retention time which is required: for example, 1.5 nm allows write times about 100 ns, but the retention time is only about days, whereas larger thickness of 4 nm is necessary for non-volatility, but the write time also increases to 10 ls. Finally, our study of a floating gate composed of nanodots as charge storage elements in a MOS transistor has also shown the importance of the inter-dot distances inside the FG (dlong ) besides the channel-FG
In this paper, we have shown that some SET devices composed of 2D metallic nanodot arrays can present giant current fluctuations, very large compared to the usual shot noise. Actually, such arrays are characterized by a dominant conduction path. We have determined the origin of the IðtÞ chaotic level shifts, and proposed a cure to these dramatic effects by opening an insulating gap along one electrode, for instance by a self-aligned process. This solution will now have to be tested experimentally. Thanks to a simple model, calculations have also been applied to a more complex case nowadays intractable, like arrays on top of a semiconducting channel (reading process in a FG-MOS). This is a direct consequence of the starting-points, i.e. the charging energy EC of the whole array and the tunnel transfer probability: the first one accounts for the Poisson equation, and the second one corresponds to the solution of the Schr€ odinger equation, both equations being also coupled in the considered picture. In order to avoid large spurious current fluctuations in the channel, large tunnel barriers are necessary, as well between the FG and the channel, as between the dots of the FG array itself. Even if the latter process is not relevant for the retention time of a charge on the FG, it yields to a jump in the read current.
Acknowledgements The author thanks A. Pepin and C. Vieu for showing her their unpublished experimental results, and Y. Leroy and A. Goltzene for fruitful discussions.
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[22] Peercy PS. The drive to miniaturization. Nature 2000;406: 1023–6. [23] Vieu C, Pepin A. Private communication, 1999. [24] Mejias M. Fabrication et etude de dispositifs a blocage de coulomb realises en combinant le dep^ ot de films granulaires d’or et la lithographie electronique a tres haute resolution. PhD thesis, Universite Louis Pasteur, Strasbourg, 1998. [25] Durand E. In: Electrostatique: problemes generaux des conducteurs, vol. 2. Masson; 1966. p. 207–10. [26] Cohen-Tannoudji C, Diu B, Lalo€e F. In: Mecanique quantique, vol. I. Paris: Hermann; 1996. p. 32–40, 68–86. [27] Ferry DK. Quantum mechanics: an introduction for physicist and electrical engineers. Bristol: Institute of Physics Publishing; 1995. [28] Simmons JG. Generalized formula for the electric tunnel effect between similar electrodes separated by a thin insulating film. J Appl Phys 1963;34(6):1793–803. [29] Averin DV, Likharev KK. Single electronics: a correlated transfer of single electrons and cooper pairs in systems of small tunnel junctions. In: Altshuler BL, Lee PA, Webb RA, editors. Mesoscopic phenomena in solids. Modern problems in condensed matter sciences, vol. 30. Amsterdam: Elsevier Science; 1991. p. 173–272 [Chapter 6]. [30] Mullen K, Ben-Jacob E, Jaklevic RC, Schuss Z. I–V charateristics of coupled ultrasmall-capacitance normal tunnel junctions. Phys Rev B 1988;37(1):98–105. [31] Bakhvalov NS, Kazacha GS, Likharev KK, Serdyukova SI. Single-electron solitons in one-dimensional tunnel structures. Sov Phys JETP 1989;68(3):581–7. [32] Zimmerli G, Eiles TM, Kautz RL, Martinis JM. Noise in the coulomb blockade electrometer. Appl Phys Lett 1992; 61(2):237–9. [33] Starmark B, Henning T, Claesson T, Delsing P, Korotkov AN. Gain dependence of the noise in the single electron transistor. J Appl Phys 1999;86(4):2132–6. [34] Zorin AB, Ahlers F-J, Niemeyer J, Weimann T, Wolf H, Krupenin VA, et al. Background charge noise in metallic single-electron tunneling devices. Phys Rev B 1996;53(20): 13682–7. [35] Geerligs LJ, Anderegg VF, Mooij JE. Tunneling time and offset charge in small tunnel junctions. Physica B 1990;165/ 166:973–4. [36] Graham MR, Ahmed H. The effect of offset charge deposited directly onto single-electron devices. Appl Phys Lett 1998;72(25):3350–2. [37] Smith RA, Ahmed H. Gate controlled Coulomb blockade effects in the conduction of a silicon quantum wire. J Appl Phys 1997;81(6):2699–703. [38] Assayag GB, Bonafos C, Carrada M, Claverie A, Normand P, Tsoukalas D. Transmission electron microscopy measurements of the injection distances in nanocrystalbased memories. Appl Phys Lett 2003;82(2):200–2. [39] Carrada M, Cherkashin N, Bonafos C, Benassayag G, Chassaing D, Normand P, et al. Effect of ion energy and dose on the positioning of 2d-arrays of Si nanocrystals ion beam synthesised in thin SiO2 layers. Mater Sci Eng B 2003;101(1–3):204–7. [40] Dimitrakis P, Kapetanakis E, Normand P, Skarlatos D, Tsoukalas D, Beltsios K, et al. MOS memory structures by very-low-energy-implanted Si in thin SiO2 . Mater Sci Eng B 2003;101(1–3):14–28.
Occurrence of giant current fluctuations in 2D tunnel junction arrays A.S. Cordan
*
ERM/PHASE, ENSPS, Bd S ebastien Brant, F67400 Illkirch, France Received 1 February 2003; received in revised form 1 July 2003; accepted 1 September 2003
Abstract Some 2D arrays composed of nanometer-size islands exhibit very large fluctuations in the current responses. The model and numerical tool presented here show that such devices are characterized by a dominant conduction path. In this paper, we explain the origin of this important noise, and suggest a design modification to reduce it. Then the same model is applied to a floating gate array (FG) on top of a tiny channel (FG-MOS). We show that in order to avoid giant current variations in the read process, large tunnel junctions are prerequisite between FG and channel, yet also between dots within the FG, even if the latter process is not correlated to the FG total retention time. 2003 Elsevier Ltd. All rights reserved. Keywords: Single electron devices; Tunneling; Coulomb blockade; Noise; Multi-dot floating gate
1. Introduction Since more than 10 years, the decreasing dimensions of the devices in microelectronics have led to important quantum effects. The aim is to reach the ultimate performance for future electronic ultra-large scale integrated circuits, by controlling electrons one by one. Two main ways are considered, either the single electron transistor (SET) [1–5] or the ultimate metal-oxidesemiconductor transistor (MOS) [6,7]. We will focus here on SET arrays: they are based on the Coulomb blockade [8–10] of a single charge on a tiny dot between electrodes. In order to extend the maximum operating temperature up to 300 K, we will see that dot and junction dimensions have to be near to 1 nm. Either single dot arrays or multi-dot arrays have been used [11– 16], obtained from different fabrication techniques [15, 17–22]. Yet as limits of the lithography technique are in the 10 nm range, no precise dimensional control could be achieved up to now for devices with only one island.
*
Tel.: +33-3-90-24-44-25; fax: +33-3-90-24-45-45. E-mail address: [email protected] (A.S. Cordan).
The most promising way appears to include small one- or two-dimensional (1D/2D) arrays of nanodots between electrodes. Island radii must still lie in the r ’ 1 nm range, but now the distance between the drain and source electrodes is at least equal to 10 nm. The additional expected advantages of dot arrays compared to single island devices are a larger threshold voltage Vth , and a higher maximal operating temperature for a given mean value of island radii, noted r. We will base the model on metallic Au islands on a SiO2 insulating substrate, as previous calculations using a similar model have been successfully compared to experimental devices fabricated with this technology [15]. Moreover, the latter was developed in order to be compatible with the Si technology already on hand, at least on the laboratory level. As aforementioned, dot sizes and junction lengths cannot be perfectly controlled, therefore the resulting arrays are necessarily disordered. Only the dimensions between drain and source electrodes, and also the array width, are controllable through a high precision lithography process. Then we will evaluate numerically the current I as a function of time, for disordered 1D and 2D tunnel multi-junction arrays. We will see that in main random arrays, only quantum shot noise is present.
0038-1101/$ - see front matter 2003 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2003.09.010
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A.S. Cordan / Solid-State Electronics 48 (2004) 445–452
Nevertheless, some 2D devices exhibit very large fluctuations [23]. The aim is on one hand to find the origin of such phenomena in these devices, and on the other hand, to propose a design modification in order to strongly reduce those large fluctuations, highly detrimental to any application. Moreover, the numerical tool can also yield to IðtÞ characteristics of more complex structures like multi-dot floating gate MOS devices (FG-MOS). In a FG-MOS, a floating gate is buried within the insulator, between the channel and the gate in the MOS transistor. In the model, we will consider the channel as a highly conducting array surrounded by blocked charges on the FG array. The Coulomb blockade effect will contribute to the retention ability of extra charges transferred from the channel to the dots in the floating gate. We will show that important noise level shifts may also occur in that case. We will present the model in Section 2, and explain the simulation method in Section 3. IðtÞ results will be discussed in Section 4, followed by the conclusion.
2. Model We consider nanodot arrays between source and drain electrodes, and a gate as drawn in Fig. 1. Arrays are composed of Au dots related by tunnel junctions on an insulator substrate (SiO2 ). Three physical phenomena could yield to electrical transport across the structures, namely the conductivity of materials, the thermoelectronic effect, and the tunnel effect. However, the material linking the conductors is an insulator with a resulting barrier height much larger than thermal activation energy at room temperature: as a consequence, only the tunnel transport takes place here. The SET arrays studied in this paper are based on the Coulomb blockade of a single charge on a tiny dot. The most simple way to explain its principle is to consider a single dot between electrodes. An electron coming onto this island involves a charging energy EC ¼ e2 =2C, where C stands for the equivalent dot capacitance. In order to hold the charge carrier on the dot up to room temper-
Junctions S
Dots D
G Fig. 1. Diagram of a 2D array. S, D, and G stand respectively for source, drain, and gate electrodes.
ature, EC must exceed by far the energy of thermal fluctuations kB T , i.e. EC > 0:1 eV, which requires an electron unlocking threshold voltage Vth larger than 0.1 V: dot and junction dimensions have then to lie near to 1 nm. For SET composed of either a single dot or a dot array, the threshold voltage Vth is defined as follows: if the applied voltage between the drain and source electrodes, noted VDS , is less than Vth , then the tunnel current IDS is not significant and the device stands in the Coulomb blockade regime. The gate electrode modulates this effect. As aforementioned, nanodot arrays can show larger values of the threshold voltage with respect to single dot devices. The starting-point was the distribution of junction lengths and dot radii. Experimental analysis by scanning electron microscope (SEM) revealed an important dispersion of inter-dot distances as compared to the one coming from dot radii [15,21]. Therefore in order to speed up calculation times, we consider the same radius r for all islands and take the geometrical disorder into account through the inter-dot distances fdj g. To be coherent with experimental conditions concerning arrays of Au dots on a SiO2 substrate [24], we take r ’ 3 nm [21]. However the model enables to consider random values of r. A tunnel junction j is characterized by a capacitance Cj and a tunnel resistance RTj , that we have calculated as a function of r, dj , and Au and SiO2 structural parameters [16,21]. In the model, each junction capacitance Cj is given by the influence capacitance between two dots (charge image method [25]) dj Cj ¼ 4p0 r r sinh acosh 1 þ 2r 1 1 X dj sinh 2n acosh 1 þ : 2r n¼1
ð1Þ
Then, the capacitance matrix C of the whole system can be constructed. Diagonal elements of C are the sum of all junction capacitances associated with a dot, and offdiagonal elements are the opposite of junction capacitance linking two neighboring dots. We have neglected the stray capacitances of islands as the SiO2 substrate of the experimental devices is thick enough. The calculation of tunneling transmission values is a challenge when a complex structure cannot be reduced to a one-dimensional case [26,27]. For a given junction, we restrict the problem to the tunneling through rectangular barriers between two dots: it is justified as long as / eVDS , / being the effective barrier height. A first approximation is to use a simple ballistic model [28], as the electron Fermi wave vector kF is much larger than r 1 . The expression of the tunnel resistance RTj is written as
A.S. Cordan / Solid-State Electronics 48 (2004) 445–452
RTj ¼
1 h3 64p2 me2
EF þ U EF
2
j Ur
expð2jdj Þ rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 r 1 1 rþd j
ð2Þ
pffiffiffiffiffiffiffiffiffiffi with j ¼ 2mU=h; the second part corresponds to the geometrical factor, and EF is the Fermi energy. Inter-dot distances fdj g are taken in the ½0:3; 0:9 nm range. Therefore, as tunnel resistances vary exponentially with inter-dot distances, the span of resistance values is very important (more than eight orders of magnitude). Calculations have been carried out in the orthodox theory frame, developed by Averin and Likharev [29]. Briefly, it is based on the following hypotheses: • a metallic island is considered as an ideal metal with an energy quasi-continuum. This hypothesis holds as long as dE kB T : dE is the energy gap between two successive states in islands; • electron localization on an island is assured when RTj RK ¼ h=e2 ’ 25:8 kX;
ð3Þ
where RK is the quantum resistance; • between two tunnel events, the system partially relaxes, charges are redistributed and equilibrium is reached before a new event occurs. Therefore the relaxation time is smaller than the time between two successive tunnel transfers; • cotunneling effects can be ignored if relation (3) is verified. Finally, electron tunneling through a tunnel junction j between two islands k and k 0 is characterized by a
forward tunnel transfer rate (Cþ j ) and a reverse one (Cj ), given by " #
DFj ðfnp gÞ 1
; Cj ðfnp gÞ ¼ ð4Þ RTj e2 1 exp DFj ðfnp gÞ=kB T where DFj corresponds to the free energy variation generated by this random tunnel effect, in the positive direction or in the opposite one. fnp g is the charge configuration on the dots before the tunnel transfer. DFj is calculated as follows DFj ¼ Ef Ei eðVk0 Vk Þ; Ef ¼ 12Qðfn0p gÞC 1 Qðfn0p gÞ; Ei ¼
447
vices with source and drain electrodes only. Therefore, we will calculate IðtÞ characteristics––i.e. the current IDS between S and D––for an electrical potential VDS applied between drain and source. Two types of arrays will be studied: 1D and 2D arrays between S and D, and arrays specially constructed in order to model a floating gate array near a semiconductor channel in a FG-MOS device. As IDS is a function of VDS only, the latter will correspond to a floating gate which is not biased by a gate voltage.
3. Simulation Since the aim was to account for disorder effects on metallic dot arrays, a specific simulator has been developed––based on a Monte Carlo approach––which includes a geometrical description of the array [16]. The Monte Carlo method for single-electron tunneling devices was first proposed by Mullen et al. [30] and Bakhvalov et al. [31]. Electron motions through tunnel junctions are randomly generated. Each event is associated with the junction j whose stability interval Dtj is minimal for a given charge configuration. As tunneling effect is a poissonian process, Dtj is obtained from the tunneling rate of Eq. (4) thanks to: Dtj ¼
lnðpj Þ ; C j
ð6Þ
where pj stands for the motion probability through junction j, and is randomly taken in 0; 1. Electron motions lead to the time evolution of charges QðtÞ and current IðtÞ across the device, for different bias voltages and temperature values. IðV Þ responses are then evaluated by averaging current values IðtÞ over t for a fixed voltage V ¼ VDS . We focus here on IðtÞ characteristics: calculations have been performed by considering Ne ¼ 103 electrons leaving the device for each simulated point, to be coherent with the experimental conditions which provided the first validation of the calculation [23]. Moreover, the applied voltage VDS has to be larger than the threshold voltage Vth at 0 K so that the system conducts. Finally, we do not take any external perturbation into account in the simulations, e.g. offset charges.
ð5Þ
1 Qðfnp gÞC 1 Qðfnp gÞ; 2
where fn0p g is the charge configuration on the dots after the tunnel event, Vk the potential of dot k, Q the charge vector (Qp ¼ enp ), and C the capacitance matrix. In this paper, we do not consider the gate electrode effect on electrical characteristics, as we first want to understand the important noise arising from some de-
4. Results and discussion 4.1. SET arrays In this first part, numerical results are presented for gateless SET devices composed of 1D and 2D arrays of M N metallic dots separated by tunnel junctions of variable lengths. M corresponds to the number of islands
A.S. Cordan / Solid-State Electronics 48 (2004) 445–452 260 1D 5x1 random array
255 250 Current I (pA)
in a row between the two electrodes, and N to the number of islands in the width of the device. For example, in 1D systems, N is equal to 1. We have limited the investigations on random disordered arrays to M; N 6 5 because of large computation times needed to isolate fluctuation occurrence. In fact, for SET, it is a realistic choice since useful devices will not involve larger arrays to avoid screening effects. Before the study of IðtÞ curves, we show in Fig. 2 an IðV Þ characteristic for a 1D random array of five islands at T ¼ 50 K. The Coulomb staircase structure is pronounced, with a threshold voltage Vth equal to 0.52 V. In the IðtÞ curves below, the temperature is fixed to 50 K, and we always take the applied voltage V outside the Coulomb blockade range. Concerning the current noise, only shot noise should appear for random 1D and 2D devices, as the tunnel effect consists in a random poissonian process. Thus we would pffiffiffiffiffi expect a relative noise limited to the value 1= Ne ’ 3%, corresponding to the Ne ¼ 103 electrons leaving the device. In Fig. 3, we first present IðtÞ results for the same random 1D array (M ¼ 5) than in Fig. 2, with an operating voltage taken equal to V ¼ 0:75 V: as anticipated, there is only shot noise. Moreover, all of the other 1D arrays we tested always followed the same trend. Secondly we consider 2D random arrays: they give rise to two distinct kinds of IðtÞ behaviors. Indeed in a first group, shot noise is again the main contribution–– as represented in Fig. 4 for a 5 · 5 device––while a second group exhibit large fluctuations in the current instead of shot noise only. Actually, we have found that all arrays of this last set are characterized by a dominant conduction path (DCP)––or minimal resistance path––as drawn in Fig. 5 for a 5 · 5 device. The line on this picture schematizes the DCP. If an extra charge is created on the DCP, it will be swept away.
245 240 235 230 225 220 215 210 0
2
4 6 -5 Time (10 s)
8
10
Fig. 3. IðtÞ curve for a 1D random array. The operating voltage is equal to 0.75 V, and T ¼ 50 K.
1.55 2D 5x5 random array 1.5 Current I (nA)
448
1.45 1.4 1.35 1.3 1.25 0
0.4
0.8 1.2 Time (10-5 s)
1.6
2
Fig. 4. IðtÞ curve for a 2D random array of the first group. The operating voltage is equal to 0.42 V, and T ¼ 50 K.
900 800
1D 5x1 random array
Intensity I (pA)
700 600
Fig. 5. Schema of a 2D array characterized by a dominant conduction path. The DCP is represented by the line.
500
Operating point
400 300 200 100 0 0
0.2
0.4
0.6 0.8 1 1.2 Applied voltage (V)
1.4
1.6
Fig. 2. IðV Þ characteristic for a 1D random array, at T ¼ 50 K. The operating voltage is taken equal to 0.75 V.
Fig. 6 shows the IðtÞ giant fluctuations for such an array. We have also evaluated the charge configurations, corresponding respectively to an IðtÞ reference level (a) and a higher one (b): in the (b) charge configuration–– compared to (a)––an extra charge is added on an island lying very near to the DCP, but not directly on it. This charge acts like a perturbation on the DCP as its retention time on the dot is longer than the DCP motion scale. Therefore, giant fluctuations can never be ob-
A.S. Cordan / Solid-State Electronics 48 (2004) 445–452
2D 5x5 array with DCP 4 Current I (nA)
b a
3.5 3 2.5 2 1.5 0
0.4
0.8 1.2 Time (10-5 s)
1.6
2
Fig. 6. IðtÞ curve for a 2D array of the second group. The operating voltage is equal to 0.36 V, and T ¼ 50 K. The configuration charge of noise level (a) does not contain any charge apart from the DCP, whereas for (b) level, one electron is added on a dot very near to the DCP.
served in the 1D arrays, as long as neither external perturbations nor gates are taken into account: as aforementioned, any excess charge on the line itself is quickly swept out. Notice that islands lying farther from the DCP can be implied too, but their effects are negligible and probably lost in the shot noise contribution. Results are reliable, as we have checked that the perturbing charge remains the same while at least 103 electrons leave the device. The noise observed here is analogous to the telegraph type [32–35], with random switching between several states. Another example is given in [36]: once low energy Heþ ions are directly deposited onto their multi-junction single electron transistor, IðtÞ discontinuities appear: they have been explained through the same process. Each jump in the IðtÞ curve is attributed to a single ion landing very close to one of the islands. In this paper, we only consider traps on islands. However the present analysis can include structural traps within the SiO2 insulator. A similar behavior has also been observed on the conduction signal of a silicon gated quantum wire, with a switching behavior ascribed to single electron trapping in the wire or the surrounding oxide [37]. The above calculations have shown that the trapping phenomenon does not happen in the wire itself, but in its vicinity. The number of states involved in the telegraph noise depends on the number of accessible levels in islands near to the DCP that are possible charge traps. As the disordered 2D arrays studied here are small, there are only few levels that cannot be uniformly distributed: thus, we do not expect a simple 1=f contribution. Once the origin of such phenomena was found, the aim was to propose a realistic solution to reduce these giant fluctuations in 2D arrays, evidently highly detri-
mental to any future application. We suggest to modify the design of the devices in a way such that no more island in the DCP vicinity would play the role of perturbing charge trapping, as electron transfer on the DCP would be slowed down and brought back to the same common time scale. With this end in view, the total resistances of the different paths should be almost the same. In principle, it requires a precise control on all tunnel junctions, that is technically not realistic up to now. As no other distance can be controlled, the only possibility would be to put larger tunnel resistances along one electrode, for instance by a self-aligned process. The IðtÞ curve obtained for a modified device is shown in Fig. 7. The device is based on the one studied in Fig. 6, except that junction lengths along one electrode are now larger and equal to 1.1 nm (wide endjunctions), with an operating voltage V ¼ 0:32 V: giant fluctuations are quenched, and only shot noise persists. The same result is obtained for arrays with random wide end-junctions. As a matter of fact, a slight modification is already adequate. We can also notice that even if this modification implies larger resistances and consequently smaller currents, their values still remain adequate for applications. 4.2. FG-MOS arrays In this second part, we turn now to more complex structures like multi-dot floating gate MOS, as drawn in Fig. 8. In this device, a classical current flows from the source to the drain through the semiconducting channel, but not through the floating gate. A charge transfer–– between the channel and the FG––is possible when the gate G is strongly biased. The Coulomb blockade effect contributes to the retention ability of extra charges on the FG dots. When the control gate voltage (between
0.068 2D 5x5 wide end-junction array 0.066 Current I (pA)
4.5
449
0.064 0.062 0.06 0.058 0.056 0
0.1
0.2 0.3 Time (s)
0.4
0.5
Fig. 7. IðtÞ curve for a 2D modified array. The operating voltage is equal to 0.32 V, and T ¼ 50 K.
A.S. Cordan / Solid-State Electronics 48 (2004) 445–452
Fig. 8. Diagram of a FG-MOS, with a floating gate of nanodots. S, D, and G stand respectively for the source, drain and gate electrodes, and FG for the floating gate.
gate and source electrodes) is varied, the addition of a charge onto the FG corresponds to a writing process, whereas the removal of a charge corresponds to an erasing process. By sensing the current difference between the two states––with and without FG charge––the stored information can be read. The straightforward calculation by means of Schr€ odinger–Poisson equations would lead to very cumbersome calculations as the number of finite element nodes would be very large for a realistic picture. Yet thanks to our approach, we have followed another way. Indeed, we are able to build specially designed devices in order to get the FG array effect on a biased semiconducting channel. This latter is modeled like easy paths, and the FG array like dots separated by wide tunnel junctions. We represent the channel by a small 2D array with small tunnel junctions (in the ½0:3; 0:5 nm range) that simulate the elementary Landauer channels and the energy barrier which originates from the confinement [6]. As a first approximation, we consider EC like an effect of the confinement of the carriers in the channel. Therefore we take implicitly the Poisson equation into account through Eqs. (5) and (1). If a voltage VDS ¼ 0:3 V is applied (larger than the threshold voltage), straightforward calculations lead to a number of channels Nch P 10 for a n-doped Si channel (height > 10 nm). However, in order to easily identify the charge transfers and to keep a reasonable computation time, we take Nch 6 2. The floating gate is represented by an array with wider tunnel junctions, as well between dots and channel, as between dots themselves (0.9 nm). The charge transfer should be possible when the gate is strongly biased, to add or remove charges on the FG. We put however much wider end gaps between the gate array and both source and drain (1.3 nm) to cut down any current flowing between source and drain through the floating gate itself. In the next IðtÞ curves, the voltage is only applied between source and drain electrodes, corresponding therefore to a reading process. As the current is again calculated from time intervals corresponding to 103 charges coming out, the shot noise should amount to 3%.
We have tested several devices at 50 K, varying in a systematic way transversal distances dtrans between the channel and the FG array, and longitudinal distances dlong between neighboring dots within the FG array. First, in Fig. 9, we have represented the IðtÞ curve associated with dtrans ¼ dlong ¼ 0:9 nm: giant fluctuations happen. In the reference level (a), the FG does not contain any electron; we have verified here that the higher level (b) results from one electron motion within the FG array, whereas the lower levels (c) and (d) correspond to one electron transfer from the FG array to the channel. In Fig. 10, dtrans is increased to 1.1 nm while dlong is kept to 0.9 nm: giant fluctuations show then a predominance of high levels, i.e. individual motions within the FG in that example. This result is not surprising, as larger dtrans values lead to higher tunnel resistances, and thus to decreasing transversal motion probabilities. These large chaotic level shifts in the current remain until both dtrans and dlong reach 1.3 nm at least. Above this value, the noise falls to 3%. Of course dtrans will obviously be designed following the requirements on the retention time s. However, we have shown that dlong is also relevant. It induces a variation in the read current of the same magnitude than for a charge transferred from FG to channel. To avoid it, we have proved that dlong has also to be enlarged. Moreover, if we consider non-rectangular barriers [6], these junctions must be slightly larger: this is coherent with dtrans P 1:6 nm for a reliable retention time [1]. In this paper, we have considered metallic nanodots. But the new hybrid structures, made of a regular MOS
5 Model of 2D FG-MOS b
4.5 Current I (nA)
450
a
4 3.5 3
c
2.5
d
2 0
1
2 3 Time (10-5 s)
4
5
Fig. 9. IðtÞ curve for a FG-MOS with only the floating gate and with dtrans ¼ dlong ¼ 0:9 nm (V ¼ 0:3 V and T ¼ 50 K). The configuration charge of noise level (a) does not contain any charge on the FG, whereas for (b) level, one electron has moved inside the FG, leaving a hole. Then, the configuration charge of (c) level corresponds to one transversal electron motion, and the same for (d) level.
A.S. Cordan / Solid-State Electronics 48 (2004) 445–452
distance (dtrans ), since the charge transfer inside the floating gate is evidently highly detrimental to memory applications. Therefore, the location of the nanocrystals in the oxide is predominant as a very small change in their distances (inside the FG, between the FG and the channel, between the FG and a gate electrode) will dramatically modify the memory properties.
4.8 Model of 2D FG-MOS b’ c’
Current I (nA)
4.4
451
4 a’ 3.6
5. Conclusion
3.2 2.8 2
3
4
5
Time (10-5 s)
Fig. 10. IðtÞ curve for a FG-MOS with only the floating gate and with dtrans ¼ 1:1 nm and dlong ¼ 0:9 nm (V ¼ 0:3 V and T ¼ 50 K). The configuration charge of noise level (a0 ) does not contain any charge on the FG. For (b0 ) level, one electron has moved inside the FG, leaving a hole, and the same for (c0 ) level.
transistor with a multi-dot floating gate, are rather fabricated with semiconducting nanodots, especially Si, as mature fabrication technologies for large scale integration circuits are available. Nanocrystals of Si have already been buried in the gate oxide of MOS transistors to form the FG [1,3]. Recently, floating gates consisting of Si nanocrystal layers were obtained through ultra-low energy Si implantation [38–40]. The nanocrystal mean radius is about 1.5 nm. The hope is that such devices will lead to high-storage density low-power memory applications, as only a few electrons are concerned against 105 for classical FLASH memory and because of the nanometer scale feature sizes. Of course, the Coulomb blockade condition is EC ¼ e2 =2C kB T , with T ¼ 300 K, thus EC and the threshold voltage need to be sufficiently large to keep a good memory control against thermal effects. But as Wong et al. have underlined it in their review [7], for Si storage dot sizes in the [3–6] nm range, the operating voltages do not exceed the [1–1.5] V range! The maximum oxide thickness between the floating gate and the control gate (that we did not take into account in our model) must be limited to reduce the gate voltage needed, and the minimum size should avoid leakage to the control gate: the optimal distance lies between 5–10 nm. Moreover, the oxide thickness between the channel and FG (dtrans ) depends on the retention time which is required: for example, 1.5 nm allows write times about 100 ns, but the retention time is only about days, whereas larger thickness of 4 nm is necessary for non-volatility, but the write time also increases to 10 ls. Finally, our study of a floating gate composed of nanodots as charge storage elements in a MOS transistor has also shown the importance of the inter-dot distances inside the FG (dlong ) besides the channel-FG
In this paper, we have shown that some SET devices composed of 2D metallic nanodot arrays can present giant current fluctuations, very large compared to the usual shot noise. Actually, such arrays are characterized by a dominant conduction path. We have determined the origin of the IðtÞ chaotic level shifts, and proposed a cure to these dramatic effects by opening an insulating gap along one electrode, for instance by a self-aligned process. This solution will now have to be tested experimentally. Thanks to a simple model, calculations have also been applied to a more complex case nowadays intractable, like arrays on top of a semiconducting channel (reading process in a FG-MOS). This is a direct consequence of the starting-points, i.e. the charging energy EC of the whole array and the tunnel transfer probability: the first one accounts for the Poisson equation, and the second one corresponds to the solution of the Schr€ odinger equation, both equations being also coupled in the considered picture. In order to avoid large spurious current fluctuations in the channel, large tunnel barriers are necessary, as well between the FG and the channel, as between the dots of the FG array itself. Even if the latter process is not relevant for the retention time of a charge on the FG, it yields to a jump in the read current.
Acknowledgements The author thanks A. Pepin and C. Vieu for showing her their unpublished experimental results, and Y. Leroy and A. Goltzene for fruitful discussions.
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