On a timing circuit for Ge(Li) detectors

NUCLEAR INSTRUMENTS AND METHODS I06 (I973) I6I-I69; © NORTH-HOLLAND PUBLISHING CO.

ON A T I M I N G CIRCUIT F O R Ge(Li) D E T E C T O R S L. KARLSSON Physics Laboratory, Royal Veterinary and Agricultural University, 1871 DK, Copenhagen V, Denmark

Received 17 August 1972 A timing circuit suited for deriving time information from Si and memory elements are considered. Results obtained with this and Ge(Li) detectors is presented. Problems adhering to the timing circuit in conjunction with a 20 cm8 coaxial Ge(Li) use of high speed emitter coupled logic circuits as time decision detector are presented. 1. I n t r o d u c t i o n

Timing experiments with lithium-drifted Ge or Si detectors are often performed in order to measure the lifetime of a single nuclear level where this level is part of a complex nuclear decay structure. Because of the high energy-resolution available with lithium-drifted semiconductor detectors it is possible to single out one de-excitation channel in the presence of a multitude of y-ray energies. This implies that, although a desirable property, time walk versus energy is not, as when timing with scintillation counters, the primary figure of merit determining property of a timing circuit to be used with semiconductor detectors. Typically, in a fast-slow coincidence setup including a Ge(Li) detector, a 1% wide energy window is used with the Ge(Li) channel. However, in most timing circuits in use with Ge(Li) detectors some kind of amplitude compensation has been included. The energy-dependent time walk can in principle be minimized by means of any of the known timing methods, such as extrapolated leading edge timingS'2), ELET, constant fraction timinga'4), CFT, or compensated leading edge timingS'6), CLET. Amplitude compensation of simple leading edge discriminators by means of adding an amplitude dependent signal to the TAC output have been reported on in refs. 7, 8 and 9. The primary problem associated with deriving time information from Li-drifted semiconductor detector generated signals is due to the nonuniform charge collection processes observed to take place in these detectors. This variation in the charge liberation and collection processes gives rise to a highly variable risetime and slope of the signal containing the time information~°-~5). It is widely acknowledged that, electronically, the optimum phase point on the signal leading edge where to trigger, is at the point where the r.m.s, noise to slew rate ratio is at its minimum. But with signals of variable rate o f rise this point cannot be unambiguously defined. 161

With a true coax Ge(Li), risetimes varying from 50 ns to 150 ns are not uncommonly encountered. Even larger rise time variations are observed with wraparound and trapezoidal coax detectors. In fig. 1 a n oscilloscope photograph is shown illustrating the amplified and differentiated, % = 50 ns, preamplifierdetector output pulses obtained from a 20 cm 3, 2.2% efficiency O R T E C Ge(Li) true coax detector irradiated with y-rays from a 6°Co source. This detector is mounted with an integral preamplifier and has a resolution of 1.9 keV at 1.33 MeV. Pulses with risetimes within the range from 40 ns to 170 ns are easily identified. It is observable that the leading edge shape o f the slowly rising pulses is markedly different from that of the faster pulses. The possibility of pulse shape discrimination using only the fast pulses for timing purposes has been investigated 7, ~4). Visual inspection of the pulses shown could give rise to the impression that leading edge

Fig. 1. An oscilloscope photo showing the amplified and differentiated detector pulses. The differentiator time constant was equal to 50 ns. A large range of risetimes is clearly visible, and it is seen that the slowest pulses have a concave leading edge.

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timing with a low threshold level would be favorable. However, this is not compatible with the desire to trigger at the optimum phase point of the pulse leading edge where the noise to slope ratio is at its minimum. Some results of leading edge 6ming as applied to different Ge(Li) detectors have been presented16ls). The extrapolated leading edge timing method is based on the use of two leading edge discriminators and associated extrapolating circuitry and represent a marked improvement as compared to the simple leading edge timing method~'2'lg'2°). A modified version of the constant fraction of pulse height method, the amplitude and risetime compensated timing method ARC, has been applied successfully to Ge(Li) detectors. Chase 2~) and Cho 22) have demonstrated the superiority of the ARC timing method as compared to simple leading edge timing. In the present work it has been attempted to implement a timing circuit, based on the ARC principle, using newly developed fast emitter coupled logic, ECL, integrated circuits to perform functions traditionally performed with tunnel diodes and discrete components. The switching speeds obtainable with present day ECL integrated circuits equals or supersedes those obtained with the classic tunnel diode-transistor combination, which is typically in the 1.5-3 ns range when using transistors with an f r in the 1-2 GHz range. By using monolithic circuits, level drift induced by temperature variation, and associated propagation delay shift, is

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In the present timing circuit, fast emitter coupled logic, ECL, circuits have been used to a large extent. Slower ECL circuits, from the Motorola MECL II family with switching speeds in the 5 ns range, have demonstrated their usefulness in timing applications with fast photomuttipliers23). More recently, basically four new integrated circuit ECL families have been made available from the manufacturers. The fastest is the MECL III family from Motorola 2~) with a typical propagation delay per gate of 1 ns and rise and fall times of typically 1.5 ns. Gates and flip-flops from this family have been used in high energy physics experiments as described in refs. 25, 26 and 27. Due to the manufacturing processes involved, the MECL III circuits are at present somewhat expensive and a second new family, the M ECL 10000, has been introduced at a markedly lower price per gate level than that of the MECL III family. With a propagation delay of 2 ns and rise/fall times in the 3 ns range this familY has strong resemblance to a hypothetical MECL 2.5 family. The gates of these two families, as with the older MECL II, are only moderately temperature compensated with respect to the input threshold levels. A temperature coefficient of typically 1.5 mV pel °C is inherent in the design. This threshold level drift is not unimportant when such

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gates are to be used for zero crossing detection. Due to the finite slope of the zero crossing signal, a drift of the threshold level gives rise to an equivalent time shi~t. A third, basically new, ECL family has been introduced from Fairchild under the label ECL 9500. The circuits of this family use the same basic configuration as the MECL II, MECL III and the MECL 10000 families but with the addition of temperature compensated internal reference and current source networks2a). These maintain the threshold level remarkably insensitive to temperature variations, at least one order of magnitude better than the uncompensated standard ECL gate. The ECL 9500 gates operate with switching and propagation delay times in the 2 to 3 ns range, which makes them very similar in this respect to the MECL 10000 gates. From Texas Instruments has come the ECL 2500 family with properties very similar to those of the MECL 10000 series. When striving for an optimum design employing ECL circuits the properties inherent in these five families should be given careful consideration. Beyond doubt, the MECL II family, except for a few fast gates such as the MC 1023 and the MC 1065, wilt be considered to possess too high a speed-power product as compared to the MECL III, 10000 and ECL 9500's more favorable figure. Further, except for its larger range of available circuit function, it is not evident on what basis the MECL 10000 series will compete with the ECL 9500 family in nuclear timing applications. With regard to MECL III, it has no competition at present, when the ultimate in speed is required. The time shift generated due to temperature induced threshold level variations is inversely proportional to the timing signal slew rate in the vicinity of the discriminator threshold level. This implies tha~ the advantages gained by using the temperature compensated ECL 9500 circuits, as zero crossing detectors or simple level discriminators, become more pronounced the lower the slew rate of the time information carrying signal. In accordance with these considerations, ECL 9582 triple line receivers were considered optimal for use as lower level discriminator and zero crossing discriminator. The block diagram shown in fig. 2 illustrates the circuit function of these discriminators.

3. Circuit description In fig. 3 is shown a detailed circuit schematic of the timing circuit. The input signal is applied to a 50 O impedance signal divider, feeding the variable attenuator and the external delay-inverter signal paths. Virtually reflection free termination is accomplished at

the low impedance summing junction at the Qt, Q2 emitters. A coax transformer inverter consisting of 10 windings of thin 50 O teflon coax cable on a toroidal ferroxcube core has been used because of its simplicity and wide bandwidth capabilities29'3°). The circuitry consisting of the transistors Q1 to Q4 and associated O+

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A TIMING CIRCUIT FOR Ge(Li) DETECTORS components serves the double purpose of providing a high quality signal summing junction and of acting as a symmetrical fast recovery limiter protecting the 9582 comparator input transistors from base--emitter breakdown in the presence of large amplitude input pulses. As compared to the more frequently used summing junction/limiter schemes4'21), this circuit has some inherently attractive properties with regard to linearity, summing junction impedance and thermal stability. The ideal summing junction has zero input impedance, no de level drift, infinite bandwidth and linear response for all reasonable input amplitudes to be used. The non-trivial problems adhering to the realization of a fast high quality summing junction arise because bandwidth and slew rate limitations reject the use of an operational amplifier in an inverting setup, which at low frequencies provides a near ideal summing junction at the virtual ground existing at the inverting input

(a)

165

terminal. This implies that some sort of passive summing junction must be resorted to. In fig. 4a is shown a circuit diagram of a frequently used summing junction/limiter scheme. The output de level of this configuration is sensitive to temperature variations at a rate of about - 2 mV/°C. Further, it has an input impedance which is a function of the input signal amplitude, of. fig. 5a, which gives rise to a highly nonlinear response of this circuit element. What makes this nonlinearity especially disadvantageous is that it occurs in the zero crossing region which makes this circuit scheme inconvenient to use in front of z.c. discriminators. The offset voltage generated at the conduction of D1 can be advantageous when this limiter is used with a tunnel diode discriminator. ~ I n fig. 4b is shown a circuit having more properties in common with an ideal summing junction. Within a limited range of input currents the summing junction impedance is about 12 t2, the emitter-base diode impedance of a typical small signal, high frequency transistor. If the diode D1 is properly selected, it will cancel the - 2 m V / ° C drift of the Q1 emitter-base junctional,32). However, the circuit is primarily a ~inipolar response circuit. As shown in the oscilloscope photo in fig. 5b, the response becomes nonlinear when positive pulses of moderate amplitudes are applied. In the present timing circuit, a bipolar version of the circuit shown in fig. 4b is used. This circuit is shown in fig. 4c and its associated response function is illustrated in fig. 5c. A summing junction impedance of about 6 f2 is obtained and the ability to recover from an overload situation is superior to the unipolar version. Furthermore, due to the symmetry of circuit, a near ideal can-

(b) (c) Fig. 5. Oscilloscope photos displaying the performance of the three circuits shown in fig. 4. These recordings were obtained by means of a Tektronix type 576 curve tracer. No bias was supplied in the case of circuit a. It is seen clearly that the input performance of the circuit in fig. 4c, with the response labelled c, is the most desirable of the three.

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cellation of temperature induced offset variations takes place. An ECL 9582 triple line receiver is used as the lower level discriminator. With the three line receivers coupled in cascade, a differential gain of about 350 is obtained. It means that a 5 mV differential input signal can drive the output from one to the other logic level. The diodes D a . . . . . D6 serve to limit the input signal range applied to the lower level discriminator. The output from the Q3, Q, collectors is fed to the zero crossing discriminator consisting of a cascade coupled ECL 9582 triple line receiver. The zero crossing level can be adjusted by means of the potentiometer RV2 which is connected such that its midpoint is virtually connected to the internal temperature compensated bias source of the 9582 circuit. A negative logic NAND operation is performed on the outputs of the zero crossing and the lower level discriminators by means of gate A of IC3. It is an inherent property of the ECL basic gate circuit that the AND operation can only be performed in negative logic, and that the OR operation is only realizable in positive logic. The positive output pulse from gate A triggers the monostable multivibrator consisting of the gates B and C. The pulse width of this monostable multivibrator determines the dead-time of the timing circuit. Three different deadtime intervals can be selected by means of the S2 switch. The 50 ns and 150 ns intervals are intended for use with fast scintillator-photomultiplier detectors while the 600 ns interval is used when the circuit is operated in conjunction with lithium-drifted silicon

(a)

or germanium detectors. The transistor Qs is included in order to shorten the recovery time, within which interval false operation can occur as). In fig. 6 is shown the response of the dead-time multivibrator to closely spaced timing pulses. From the oscilloscope ph~ographs it is seen that the inclusion of the Q5 transistor gives rise to a marked improvement in the recovery response. The two recordings were made under identical conditions, except for the removal of Q5 in the left photograph. As the circuit is wholly dc coupled, the IC a monostable is the only circuit element limiting the count rate capability. When the Q output goes high, this triggers the fast monostable multivibrator, IC4, delivering a 10 ns wide NIM compatible fast logic pulse at the connector CN 7. With this circuitry, a - 700 mV pulse amplitude into a 50 £2 load is obtained. Rise and fall times are less than 1.5 ns. The output pulse width is solely determined by the length of the 50 fl cable inserted between pin 2 and pin 11 on IC,. The amplifier consisting of the transistors Q6, Q7, and Qs converts the __.400mV logic levels into standard NIM compatible slow logic levels, i.e. +4 V amplitude into 50 fl load. MECL III gates have been chosen as IC3 and IC4 because of the high switching speed thus obtained. Insensitivity to temperature variations is not as critical in this part of the circuit because standardized high slew rate pulses are supplied as input to these gates. The alternative use of ECL 9500 gates for these functions would improve the thermal response somewhat, but at the expense of speed.

(b)

Fig. 6. Two photos illustrating the improvement in performance of the deadtime monostable multivibrator obtained when the transistor Qs, of. fig. 3, is included. The left photo shows the response without Qs. The right photo illustrates the response t o closely spaced excitations with Q5 added. The lower trace in the photos shows the fast negative output pulse obtained at CN 7.

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The advantages gained by using temperature compensated ECL circuits for deriving the time information would be lost if these circuits were not supplied with stable Vcc and VE~ levels. In fig. 7 is shown the circuit diagram of the voltage regulators used to supply the + 1.3 V and - 3.9 V levels. These levels are kept stable to within about + 20 ppm per °C of temperature variation. The ECL circuits can be operated at a single supply level, VEE = - 5.2 V and Vcc grounded, but this complicates level interfacing at the inputs of the discriminators and at the output of IC4. Some calculation will show that in the present case, the two-level solution is the least complicated. A 25 f2 resistor, rated at 3 W, has been inserted in series with the BC 140 and the BC 160 collectors in order to reduce power dissipation in these transistors.

Ge(Li) D E T E C T O R S

167

compensated leading edge discriminator6). The stop channel contains a 2.2 % efficiency, 20 cm3 coax Ge(Li) detector mounted with an ORTEC type 120 preamplitier. The timing signal from the preamplifier is amplified and shaped in a timing filter amplifier34) before being fed to the timing circuit. In fig. 8 is shown a time spectrum obtained with a 6°Co source. Compton interactions within the 450900 keV range were allowed to gate the start channel, while the 1.17 MeV photopeak 4- 5 keV was used in the Ge(Li) stop channel. The delay time td and the fraction

4. Experimental results

The timing circuit has been used and evaluated in connection with a fast-slow coincidence timing setup. In the start branch was used an NE 111 plastic scintillator coupled to a XP 1021 photomultiplier feeding a

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Fig. 8. T h e u p p e r p h o t o s h o w s o n a linear scale a time s p e c t r u m obtained with a e°Co source. Below is s h o w n the s a m e s p e c t r u m on a logarithmic scale. T h e center channel contains 1.8 x 103 counts. A conventional f a s t - s l o w coincidence setup was used. T h e start c h a n n e l detector was a N E 111 scintillator coupled to a X P 1021 p h o t o m u l t i p l i e r a n d in the stop channel was u s e d a 20 c m 8 D O E coaxial Ge(Li) detector. Late is to t h e right in t h e pictures. A time scale o f 285 ps/chann¢l was used. F u r t h e r details are discussed in the text.

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L. KARLSSON

f w e r e observed to influence the shape and the fwhm of the time peak heavily. The best operation of the timing circuit was obtained with external delay of about 4 ns and with f = 0.2. As seen from fig. 8, a fwhm of 1.8 ns and a fw(-~o-)m of 4.3 ns is obtained with t d = 4 ns and f = 0 . 2 , which indicates excellent operation as compared to results obtained with coax Ge(Li) detectors reported on in the literature. A feature of the timing spectrum is the absence of tailing effect on the late side of the peak. This indicates that risetime compensation is performed satisfactorily. 5. Constructional details

ves to form a low inductance ground path and facilitates the construction of low impedance striplines. The switching speeds obtained with MECL III circuits are such that stripline connections are essential for pres~erving pulse fidelity2#). As can be seen from fig. 10 t~e BNC connectors are mounted isolated from the front plate in order to avoid uncontrolled ground loops. The 50 12 variable T-pad attenuator is clearly visible in the foreground of the sideview picture. In fig. 11 is shown a photograph of this attenuator with the shield removed. A printed circuit with ground plane divides the two switching sections and assures short lead lengths, screening and low inductance ground connections.

In fig, 9 is shown a sideview of the timing circuit module. Dual sided printed circuit is used, with one side as a ground plane. The use of a ground plane ser-

Some care should be taken with regard to the thermal environment of the MECL III circuits IC3 and IC#. Cooling fins are recommendable but they are not

Fig. 9. Sideview photo illustrating the mechanical structure and the component placement used. On a later version, the 25 ~Q3 W resistor~ in the power supplies, cf. fig. 7, have been mounted on the rear panel of the chassis in order to improve the thermal characteristics.

A T I M I N G C I R C U I T FOR G e ( L i )

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Fig. 10. Frontview photo showing the arrangement of the connectors and controls. As can be seen, the BNC connectors are isolated from the front panel. This reduces possible signal crosstalk due to uncontrolled signal paths. necessary with the low package present construction.

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The author is indebted to members of the laboratory for interest in the present work, in particular to N. Cortsen for technical assistance and to K. Maack Bisghrd for encouragement and support. References 1) j. p. Fouan and J. P. Passerieux, Nucl. Instr. and Meth. 62 (1968) 327. 2) Canberra, Extrapolated Zero Strobe, Model 1426, Manual (Canberra Industries Inc,, 1971).

a) p. Weinzierl, Rev. Sci. Instr. 27 (1956) 226. 4) D. A. Gedcke and W. J. McDonald, Nucl. Instr. and Meth. 58 (1968) 253. 5) L. Karlsson, Nucl. Instr. and Meth. 93 (1971) 563. o) L. Karlsson, Nucl. Instr. and Meth. 100 (1972) 193. 7) j. M. Jaklevic, F. M. Bernthal, J. O. Radeloff and D. A. Landis, Nucl. Instr. and Meth. 69 (1969) 109. s) p. Thieherger and L. Harms-Ringdahl, Nucl. Instr. and Meth. 70 (1969) 346. o) R. Van Zurk and A. Mougin, Nucl. Instr. and Meth. 95 (1971) 475. 10) F. S. Goulding, Nucl. Instr. and Meth. 43 (1966) 1. tl) M. G. Strauss, R. N. Larsen and L. L. Sifter, IEEE Trans. Nucl. Sci. NS-13, no. 3 (1966) 265. 12) E. Sakai, IEEE Trans. Nucl. Sci. NS-15, no. 3 (1968) 310. 18) E. Sakai and T. A. McMath, Nucl. Instr. and Meth. 64 (1968) 132. 14) M. Moszynski and B. Bengtson, Nucl. Instr. and Meth. 80 (1970) 233. 15) M. Moszynski and B. Bengtson, Nucl. Instr. and Meth. 100 (1972) 285. 16) W. Michaelis, Nucl. Instr. and Meth. 61 (1968) 109. 17) j. A. Miehe and P. Siffert, IEEE Trans. Nucl. Sci. NS-17, no. 5 (1970) 8. is) j. B. S. Waugh, IEEE Trans. Nucl. Sci. NS-15, no. 3 (1968) 509. 19) A. Hofman, G. Philipp, K. Thomas and F. Vogler, Nucl. Instr. and Meth. 101 (1972) 467. 2o) Z.H. Cho and R.L. Chase, Nucl. Instr. and Meth. 98 (1972) 335. 21) R. L. Chase, Rev. Sci. Instr. 39 (1968) 1318. z2) Z. H. Cho and R. L. Chase, IEEE Trans. Nucl. Sci. NS-19, no. 1 (1972)451. 2s) M. R. Maier and P. Sperr, Nucl. Instr. and Meth. 87 (1970) 13. 24) j. M. DeLaune, Application Note AN-504 (Motorola Semiconductors Inc., 1972). 25) F. Pozar, Nucl. Instr. and Meth. 91 (1971) 253. 20) W. S. Risk, Nucl. Instr. and Meth. 97 (1971) 547. 27) R. F. Althaus and L. W. Nagel, IEEE Trans. Nucl. Sci. NS-19, no. 1 (1972) 520. 28) Fairchild, Advanced Logic Book (Fairchild Semiconductor, 1972) p. 129. 29) C.K. Winningstad, IRE Trans. Nucl. Sci. NS-6, no. 1 (1959) 26. a0) R. Conrad, Nucl. Instr. and Meth. 67 (1969) 148. al) L. J. Herbst, Nucl. Instr. and Meth. 70 (1969) 185. 32) OR TEC, Model 453 Constant Fraction Timing Discriminator Manual (Oak Ridge Technical Enterprises, 1972). as) E. Renschler, Application Note AN-233 (Motorola Semiconductors Inc., 1972). a4) L. Karlsson, Nucl. Instr. and Meth., in press.