On-Board Computers for Control

ON-BOARD COMPUTERS FOR CONTROL John R. Scull Information Systems Division, Jet Propulsion Laboratory, California Institute of Technology, Pasadena, California

Abstract. Spacecraft computers have evolved over the last decnde from simple, harc-wired sequencers to complex, general purpose machines with large memories and redundant processors. ~anned spacecraft during the 1960's were the first to use general purpose architectures, but were limited by their excessive weight and enormous power requirements. The invention of Large Scale Integrated ci rcui ts (LSI) in the early 1970' s permitted urrnanned sp<"cecraft computers to use architectures which were capable of in-fligPt reprogramming. Recent developments, including microprocessors and large memories on a single chip, have permitted the development of distributed processors and the application of multiple renundancy for long life, high reliability missions. Keywords. Aerospace Computer Control; Attitude Control; Computer ~rchitecture; Computer Hardware; Computer Software; Data Handling; Digital Control; Error Compensation; Integrated Circuits; Kelman Filters; Memory Devices; Space Vehicles.

APOLLO

INTRODUCTION On-board computers for control and sequencing have been used in spacecraft since the beginning of the sp<"ce age in the late 1950's. The first spacecraft used mechanical timers or simple R/C timers for initiating separation from the launch vehicle or the despin sequence. One early spacecraft even used a wristwatch movement to turn off the transmitter after the spacecraft han been in orbit for a period of one year.

The Apollo Guidance Computer (AGe) is an example of the technology available in the early 1960's. Two designs emerged as a result of the rapid change in the state of-the-art at that time. The first design, Plock I, used primarily discrete components. The second improved design, Block 11, utilizing integrated circuits, roughly doubled speed, increased input/output capability, decreased size, and decreased power consumption. The major functions required of the AGC were alignment of the inertial measurement unit, processing of radar data, manegement of astronaut display and controls, and generation of commands for spacecraft engine control. Figure 1 is a functional block diagram of the AGe.

The first three-axis controlled spacecraft used a simple crystal oscillator and a counter chain to time events after launch and a few shift registers to store critical time events which could be changed by ground command. Attitude control electronics were generally non-linear analog "computers" which were used to switch on and off control gas ;ets and to point cameras and instruments.

The AGC was a general purpose parallel architecture with a l~-bit word length including one parity bit. There were 2048 (2K) words of erasable Random Access Memory (RAM) and 36K words of read-only memory (ROM). The RAM memory was? typical coincident current ferrite core type. The ROM memory was of the transformer type, commonly referred to as a "core rope memory."

In the early to mid-l9~0's, moderate-sized general-purpose digital computers (a hundred kilograms and a few hundred watts of power) were developed for aircraft, launch vehicles, and manned spacecraft. These computers were still too heavy, consumed too much power, and generally were not suitable for use in an unmanned spacecraft expected to operate unattended for periods of a year or longer. The computers used in the Gemini and Apollo spacecraft were "man rated" for high reliability for use over relatively short mission lifetimes.

The processor featured the multiple-precision arithmetic capability necessary for guidance computations and an ADD time of 23.4 microseconds. The hardware and software were heavily oriented toward interfacing with the astronaut crew. A Display/Keyboard (DSKY) unit was included 429

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for display ard entry of a verb-noun format language. Examples of verbs were "DTSPUlY", "MCNITOR", and "LOAD", and examples of nouns were "TIME", "GIMBAL ANGLES", and "ERROR INDICATIONS." Each Apollo spacecraft contained two AGC's and three !)';KY's. The basic reI iabil i ty approach included: (1) built-in test for fault detection (/) manually initited powered-down mode of operation, (3) electrical and mechanical designs with large margins, and (4) emphasis on reliability of c~mponents, testing procedures, and fabrlcation processes. (SCull, 1977; Hall, 1972) MNUNER 7 The fi rst unmanned spacecraft to use a general purpose reprogrammable digital computer architecture for sequencing and control was the Mariner 7, launched to Mars in 1969. Although this computer, the Central Computer & Sequencer (CC&S), was fairly crude by today'S standards, it employed many of the techniques of more modern processors and was primarily limited by weight since if was implemented using discrete components and small scale integrated cirCUits. The Mariner 1969 CC&S weighed at:x'ut 10 kg, used 23 watts of power, had 16 lnstructions and contained a core memory of 128 22-bit ~rds. This interrupt driven processor was reprogrammed many times during the mission with a total of 1305 radio commands sent from the Earth. The reprogramming of this computer allowed great mission flexibil i ty, and many sequences were carried. out which had not been planned prior to launch. Reprogramming also permitted alternative approaches to be used to work around problems occurring in other subsystems during fl ight, which greatly enhanced the scientific return of the mission. (Scull 1970) , IMP & (}\O

Several other spacecraft SOOn followed with increased capability on-board computers. In 1971, the IMP-I used the NASA/GSFC SDP-3 (Spacecraft Data Processor) serial computer for control, data compression and experiment data acquisition. This co~puter we ighed 4.5 kg and used 3 watts of power. I t had 54 instructions, 16 interrupts, a 16 bit word length, and a 4K core memory. In the next year, GSFC flew the OBP (On Board Processo r) in its Orbiting Astronomical Observatory (OAO-C). This parallel digital computer was used for attitude control tasks, data handling, and command and control in an off line capacity. It weighed about 20 kg, consumed 20 watts of power had 55 instructions, used an 18 bit word le~th, and had 4K of core memory. (Aukstikalnis 1974) ,

MARINER 8 - 10 The Mariner 8 i'lnd 9 spacecraft, launched to Mars in 1971, and the Mariner 10, which went to Venus and Mercury in 197~, contained a modified version of the Mariner 7 CC&S computer. These improved computers increased the size of the on-board memory to 512 words, added the function of co~recting thrust misalignment of the traJectory correction motors during autopilot control, and provided integration of accelerometer signals for motor shutoff. The Mariner 10 spacecraft also introduced a new digital computer-based telemetry syst~ called the Flight Data System (FDS). ThlS special purpose computer, which was also reprogrammable by ground command, had 18 different data modes which were selectable from the CC&S or by radio command. The Attituee Control System used nearly the same non-linear electronic analog computer as did previous Mariner spacecraft, but the Articulation Control System was a new digital design which contained multiplexed servo control of not only the science scan platform but plso the pointing of a large radio antenna and the solar panels. The latter proved especially valuable after the first close flyby of Mercury when the angles of the solar panels were controlled to provide a simple form of solar pressure control in the roll axis for conserving attitude control gas. This strategy proved so successful that two additional close flybys of Mercury were possible before the gas was exhausted. (SCull, 1972, 1974)

SOVI ET MARS AND VENUS

The Soviet Union has published little about its spacecraft on-board computers. An early paper (Raushenbakh, 1958) described primarily analog non-linear attitude control computers. Papers about the USSR Mars 2-7 (Demiokhin, 1975) and Venera 9-10 spacecraft (Keldysh, 1976- Demiokhin, 1976) reported that the spac~craft contained an on-board digital computer for use in the autonomous guidance system. This system provided determination of the spacecraft position in the Sun-Star-Earth coordinate system. On the Mars spacecraft, there was also a planet sensor, described as a part of the autonomous guidance system for navigation in the vicinity of the planet. Yakubatis (1975) discussed a system for construction of Universal Mu1tifunction Logic Modules where a multiple function structure can be synthesized on an L~I chip us!ng a programmed logic array lnterconnectlon of gates. A 10 X 32 array PLA was described.

On-board Computers for Control

ORBITING APPLICATIONS SATELLITES In the early to mid 1970's, NASA/GSFC redesigned the OBP dpscribed earlier to become the Mvanced On-board Processor. This computer used a Large Scale Integrated circuit called Custom Metalized Multigate Array (CMMA) developed originally by JPL/Harris for the Grand Tour mission. The ilK memory version of this comp.!ter used B to 15 watts of power depending on operations performed, had 55 instructions, an 18 bit wor~ length, a 4 microsecond ADD time, a If; level priority interrupt structure, and direct memory access (DMA). The memory was eXp
431

and e 25 bit word length. The DAPU ~ad an 8K plated wire memory, 2d bits per word, and also used a ~o million bit magnetic tape recorder for storege of deta when the sp?cecreft was out of sight of the tracking stations. The qualification of these computers was unique in that they had to survive a high temperature heat sterilization cycle in order to prevent contamination of the planetary surface with earth-based organisms. The Viking arbiter Command Computer System (ees) shown in Figure 2 was a new redundant serial design containing two ilK plated wire memories of 18 bits per word and electronics redesigned from the previous Mariners using TTL small and medium sc?le integrated circuits. It had an ADD/SUBTRACT time of 90 microseconds and a priority interrupt structure. The architecture sep
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John R. Scull

)~ ]pvel priority interrupt structure. In the origin?l version of this romputer, the cro WP ighed 1. <1 kg i'lne (,rew <; w~tt.s. Er-ch PI< pJeted wire m~mory module ?lso weighed l.~ kg ?rY.' rrew 31 \vetts peck po\lCr •.r, morifif!c low power core m0mory Module reducer the ~ak po..... "r to lc;.7 We logic femi)y for this comp.Jter is the 0Ii'11'- ",nd <;IlL series. (IBM, 1~77) ~

The Voyager sp2ce("ri"ft, or igin<>lly caller' M2riner Jupiter S?turn '7 7 , us~s three sep.JID/SlIB'T'RlI CT cyc 1e t i mr' of 3?.2 microseconcs, which is npcessClry in order to occomp] ish ?ll the functions required in a 10 millisecond computAtion cycle. The activity rete is re]?tively high (about 95%) compared to ~ - <;% for the CCS. f>._ mixture of st?nc1arc And low-power '!'TL is useo to ?ccompl i sh the increased spee(l requirements. The 4K memory is used exclusively for the orientation, st?bilization, and pointing comput?tions, and redundant-element (power supplies, gyros, sensors, etc.) fault retection. Inputs ",re both en~log And digit~l. Outputs are (Hgital ect2 or r1iscret.e pu) se signClls to control the gyros, gilS jet firings, and science instrum~nt pletform stepper motor ectu?tions. The ~CS with renunr1cnt processors i"nd memories we igr.s ?l.] kg "nd drClws 35 WClttS of power. Figure 3 is <> functional block r1i?gr"m of the ACS (Scull, 1977) • '{'he use of a digital computer for all attitude computations permitted C! much more sophisticated system to compensate for gyro crift rate, Kalman filtering to remove sensor noise end to estimilte cngular riltes, and for fault correction. The 1'-ACS computer is linkec to t.he CCS ane t.he F~S so th?t telemetry meClsurements cnd cct.ivity of the 1'-ACf computer c?n be us~n to switch out ilnd replace "bad" sensors, actuators, or computer strings before any dam?ge to the spacecraft can occur. Some of the algorithms for fi'ult correction had to be "tuned" for normel v?lues of rotes i'lnd at.titude limits at the beginning of El ight because sever?l tim~s the preset limits were exceeoed

cellsi ng "CJooc" un i ts to I:>e s\·:i tched out "'nd replaceC. (Flekher, 1977) '{'he Flight Dat~ Subsyst~m (FD~), using u ]r,-hit, PK worn memory with ~n ~1D/SUB'I'R1'-CT cycle time of 15 microseconds, is the Voyager computer used for science instrument control and d~tc processing (see Figure ~). Its design is of the mid ]970's, cnd it uses Complcmentery ~ctC'l Oxide Semiconductor (CMC'S) integrated ci rcui ts for hoth the processing circuitry and memory. The primary functions of the FDS are the timing anr1 mofe control of th~ various science instruments 2nd the multiplexing of date from those instruments as wel) as from engineering subsystems into a serii'll-data output streem whi ch can be recorded or transmitter1 directly from the spccecraft. The FDS handles oet2 from e2ch bufferec input at a sample rate of 8 kilobits per second for low-rete inputs, and l15.? kilobits per second through each of four rirect memory rccess (O~A) chennels for high-rilte inputs. Sixty percent of the PK memory is programmed with 12 to 15 C?til modes which "re selecteo "s required to support t.he r1esirer1 lEvel of science activity. The rem?inr1er of the memory is us~d for science instrument control parilmeters ?ne short-term cete rate buffNing. The ~ \Vf>ighs )8.2 kg Clnd draws o watts of power. (Scull, 1977) F'lJ["UnI' '{'RENDS

'{'he LSI and microprocessor developnents in the latter p?rt of the deCAde have permitted a further rer1uction in the size, weight, and power requirem0nts for sp?cecraft on-board computers. The primery effect has been to allow designers of small, unm?nned spacecraft to incorpor?te digital computing techniques that were previously available only in large Earth-based computers. Tn 'nrger m?nned spacecreft ?ble to CArry he?vier subsystems, the increase in cepability is even more pronounced. Microprocessors, such as the Tntel POP-O, AMD ?900, '{'J ~900, and RC~ 1802, contain on one chip almost the entire CPU portion of a spi'lcecreft computer which used to occupy sever?l printed circuit bo?rds and thousanc1s of components. Memory devices now in mass production controin ]hK bits on 0 single chip with htK chips ?nnounced by severa] mi"nufacturers. LSI chips which hnnd]e I/O, memory aor1ressing, bus interfacing, rono anillog to d igi t?l conversion ere available for the romputer c1esigner. Severa] manuf?cturers hilve announced Very Large Sce]e Integr?ted circuits (VLSI) that contain up to 10,000 active elements such as a 15 bit CPU, I/O control, ROM ;lnc RAM on the same chip. These inventions permit spacecraft computers to use High Order Langueges (HOL), distributed processors, fault tolerant architectures, d?ta bus systems, and spec i al purpose processors such

On-board Computers for Control

as Fast Fourier Transforms (FFT), Tnteger Ring Transforms, pipelin~0 parallel processors, and array processors. The Lsr industry has been improving and expanding the capability on a single chip at the rate of approximc.tely a factor of 00 to 100 every 10 yeers. (Cerberry, 1977; Shepherd, 1977; Hopkins, 1975) Very small semiconduct.or structures ere not without risadvantages as for as spacecraft use is concerned. ~s the area of the active transistor becomes smc.ller and smaller, the amount. of charge represented by the state of o ONE or a ZERO also becomes smaller. The limit of practicalit.y may well be reached when the charge required to change the st.ate of a flip-flop or memory element is that generated by a cosmic ray particle, energetic electron, or proton from trapped radiation belts passing through the integrat.ed circuit. There have been several reported cases of memory bit errors in spacecraft computers which may hove been caused by this effect. (Hollers, 1977) The performance of on-board computers, measured by such factors cS improved speed, lerger memory, and the number of on-boaro processors per spacecraft, has improved more than c factor of 1000 in the last 10 yeers. Using planeti"ry spacecraft as an example, figure 5 shows that the number of on-board processors has increased 7.0 times in a little more than a decade. Figure 5 illustrates that the amount of addressable ROM memory in these spacecraft has grown a thousand fold in the same period. The cycle time, a measure of the computer's speed of operetion, has also improved by more than 2500 times since 19r,9. As a result of this increase in computing power, the amount of date processed, and the complexity of the functions performed, the total amount of data sent back to F.arth for scientific analysis per mission has increased by i" factor of more than 100,000 since the launching of the first U.S. planetary mission in 1~7. (see figure 7). ~t the same time thet the performance of the on-board processors has been improving, the cost, weight, and power to perform a given function has been decreasing significantly. Table 1 shows the characteristics of several typical spacecraft computers developed over the last decade. Figure R illustrates the dramatic miniaturizntion thr.t has occurred in the period from 19~4 to the present. The same basic tr.sk is performed by each of the devices shown.

One of the trends permitted by more computing power on-board spacecraft is that of greater autonomy and eutomation. As missions become more complex and as spacecraft travel to greater distances from the Earth, the spacecraft must be capable of making more decisions on its own. Automatic

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fault recovery has already been described in the Voyager spacecraft. This capability is needed to repoint the spacecraft to the Sun, star, and Earth references and to put the spacecraft into a safe state until ground command intervention can occur. As mission lifetimes increase to many years, it is also necessary to reduce the number of operations personnel required to monitor the deily activities of the mission. In mcny c~ses, it is desireable to adaptively react in real time to a change in the environment or the science results being observed. (Bird, 1979) There are several other more complex functions needed to permit greater eutonomy in spacecraft on-board computers. These incluc.e on-board im2ge processing, feature extrar.tion, data compression, ane tactile fee~beck. High level processing of image data is neened for supplying object edge boundries so th?t less informC'tion need be stored for a miltrix relief !Tl<"p of the local environment. (Dobrotin, 1~7e, 1979; Yastrebov, 1975) There is a need for on-boerd image neta compression and spectrc.l r.li"ssi f icat ion to re<"1uce the amount of Gi"ta which must be sent back to grounr based observers (1."elJm?n, 1978; Jordan, 1979). On-board manipul?tors for roving pI anetary vehicles or automatic assembly tasks in Earth orbit require "touch" or "feel" feedbi"ck to enahle the actuators to adc.ptivly act in an unknown environment. (Bejczy, 1979) HIGH ORDER LANGUAGES Most of the first on-board spi"cecraft computers were progr&mmec in mi"chine or i"ssembly language. Some i"ssisti"nce wC's given to the progri"mmers by having a collection of "macro" instructions written in machine langu?ge for commonly executed sE'quences. Cross C'ssemhlers to generate code for transmission to the spi"cecraft computer were also developed, but most of the early ones did not have a convenient man-mi"chine interface. The Space Shuttle progre.m developed a convenient langu2ge for gener?ting software for the AP-IOl computer called HAL/S (Houston Aerospace Language/Shuttle). This prograrrrning language can be hosted on several types of le.rge ground-based computers and is especially suited for real time programs in space or aircraft computers. This High Order Language addresses itself directly toward menned and unmanned applications where high reliability, good programming constructs, tight compiler checking, and me.intainability are required. The main applications of HAL/S softwi"re are navigation, guidance, control, stabilization systems, operating systems, data management, and communications and display. Many new HPL/S compilers are being developed for different aerospi"ce ti"rget and host computers. (Martin, 1977)

434

John R. Scull RF£F.NT

DESIGN

F.~PL~S

Several recent on-boara computers have been designen using modern LSI and ne .... distributed architectur~l approaches. Distribut~d processing allows a modular approach with local control of processing tasks in dedicated computers each having its own executive operating system. (Reoman, 1977) GALILEO The next V.S. planetary spacecraft, Galileo, has a distributed computer based on the Unified Data System (UDS) concept. (Rennels, 1976, 19 7 P') This computer system, called the ComlT'and D?ta Subsystem (CDS), uses multiple microprocessor mooules interconnected by a data bus communic?tion system. High level modules, each containing 32K of RAM and lK of ROM mf'lTlOry, direct the activities of a group of low level modules, each containing 16K of RA~ and lK of ROM. The high level modules feature DMA, a bus adaptor, bus controller, and real time interrupt. The low level modules contain a large I/O interface capability ano ~ bus adaptor but not a bus controller. A critical controller manages the overall configuration, issues critical enables, and protects delegated blocks of memory. In addition to the large amount of memory contained in the high and low level modules, there is additional bulk memory connected to the bus in blocks of l~K. For storage of program or science data, there are also two tape recorder mass store memories ~'hich can holo up to r,O,OOOK bits each. All commands, memory transfers, and telemetry data gathering from science instruments is accomplished over two dedicated data buses. The CD~ weighs aproximately 30 kg and u~s 28 watts of power. Many of the science subsystems also contain microcomputers and the total count of separate microprocessors in the Galileo spacecraft is over 20. (Ebersole, 1979) The AttitUde and Articulation Control Subsystem (AA.CS) is also a new design for Galileo. It employs a bit slice architecture of 111 bit word length, aproximately 20K of RAM, Q~A from the COS, 3~TS data transfer rate, am a large I/O capability including D/A and A/D converters. The computer has a 129 IT'icroprogrammed instruction set, a 5.p microsecond floating point ADD time, anf uses about 20 watts of power. The requirements on the control system for Galileo are more complex than prior planetary Spacecraft since it is a dual-spin configuration. The AACS controls the despun science platform, antenna pointing, active am passive nutation damping, the RTG boom for CG and product of inertia control, and the spin rate of the main body of the spacecraft.

FTSC

Paytheon is developing a Fault Tolerant Sp;>cE"craft Computer (f'T'f'C) y;hich uses both element level reoundancy and ? distributed architecture to assure that no single point failurE" will result in il complete computer loss. A configurction control unit categorizes any fault and reconfigures the computer moclul es, the CPlI' s, the bus, and initiates recovery. This is accomplished by selecting spares and reconditioning them (such as restoring contents of a memory). The FT se contains 25 separate 4K 32 bit memory modules,and uses a total of I)~K at anyone time with the rest as spares. The design weight is 23 kg with a power consumption of ~5 watts. The instruction set is microprogrammed with Ql instructions and data rates up to 5~BPS can be transferred by OMA memory ?ccess. The FTSC is capable of 250 ROPS with a IT'ixed instruction set. It is constructed of CMOS/SOS devices and has a design life of 10 years. (Fanelli, lS77; Hecht, 1977; A/W, 1977) SPliCE SHUT'I'LE The Data Processing System (OPS) is the computer system for the U.S.A.'s Space Transportation System. This computer carries out all. on-board processing, df·t? transfer, dat? entry and display for the Space Shuttle Orbiter. The DPS consists of Cl group of 5 processors calle0 General Purpose Computers (GPC), seven groups of data buses, ann an Input Output Processor (lOP) consisting of 24 independent bus control element processors. on-bo~rd

Each GPC is an IB~ AP-I0l microprogram controlled CPU and two Line Replaceable Units (LRU) containing portions of memory used on a non de0ic~teO basis. The AP-lOl is an upgraded version of the IBM ~ n computer and has IBM 3hO compatible software. It has 15~ instructions including 15 bit and 32 bit fixed point and 32 bit anc ~4 bit floating point arithmetic. A bidirectional data bus using a 35 bit parallel word structure provioes the connection between the CPU end the lOP. The GPC is constructeo using TTL end Schottky medium scale and large scale integrated circuits. The memory is ferrite core and is in r~ X ~~ bit modules. The normal memory complement is 41K per CPU and 24K in the lOP. Mass memory is provided by a tape recorder with a 134 MPit capacity. In order to interface with engines, displays, keyboards, and telemetry, other modules are connecte0 to the data bus. The CPU draws 350 watts end weighs 2h.4 kg. The processor is capable of 325 KOPS with a typical Shuttle work load. (Gardiner, 1975; KJinar, 1975; C.ooper, 1975)

On-board Computers for Control

SUMr--f>.'W Spececreft computers for control ~nr. sequencing have uncergone many chcngrs since the beginning of the spoce ?ge in the late 19S0's. The primary cause of thp changes has been the cevelopment of the digital integrated circuit vmich has increasecl the number of functions ~~ich cen be performed on a single silicon chir from one or two up to more than la,OOO. These improve r integrated circuits permit significant decreases in weight, size, anf. power of spacecraft computers. The miniaturization for each function generally has not made the on-boa re computer much smaller, but instead, the same amount of ~~ight and power has bren allocated to the computing subsystems. Thus, the computing capability of the modern spacecraft has hecome greater than that Jf many of the 1 C'rgest groun<'l-based computers available at the time of the first artificial F~rth satelJite.

435

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1"'0

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ACKNO"LErGMENrS The author woule like to acknowledge Som Deese for provicing information on the Galileo COS. This peper presents one phase of research carried out by the Jet Propulsion LBhorC'tory, California Institute of Technology, under Contract NAS7-l00, sponsored by the National Aeronautics and Sp?-ce ~inistration. REFERENCES

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~ission

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~ttituCe

'T'ABLE ]. TYPICAL SP,l\,CECRJoFT

Technology

Memory Type

C~PUTER

Speed sec)

(}1

CCMPARISON

\"eight (kg .)

Power (watt.s)

AGe I

Discr.

Core

50

50

AGC

Discr. ,TTL

Core

23.4

2~.3

80

V075 CCS

TTL

5 mil Plated Wire

90

18.2

24

V3R77

TIL

5 mil Platec' wire

32

21

35.5

CMOS

.?5

20

44

II

JlCS

GLL82

Rirolar,

MCS

CMOS

125

On-board Computers for Control

OSC Cll( & TIMING

COUNTER & INTERRUPT PRIORITY CKT.

437

MEMORY 8AN~

REGISIERS

MEMORY

,.---

ADD~ESS

REGISIER

r-

SEa. GEN. MICROPROGRAM PULSES

f--

ERASABLE MEMORY

--.

-

ADDRESS ABLE CENTRAl REGISTERS

L.-

L-.

.-..

FIXED MEMORY

r

ARITHMETIC UNIT

MEM. TIMING

MEMORY LOCAL REGISIER

f--

r

I SPECIAL GATlNG

fI/O CHANNELS

INPUT S OUTPUT S

BUSS

L-.,

INSlRUCTlON DECODING

Fig. J Jlpa] 10 Guidimcp. Computer (AGC)

~ OSC CLK & TIMING

.4KHZ

·MEMORY A

TIMING

++

~

DIGITAL DATA INTERRUPT PROCESSOR A

INPUTS SPACECRAFT & INTERNAl

CENTRAL PROCESSOR A

OUTPUT I

DISCRETE COMMANDS TELEMETRY 10 FDS

-

I-

--

---

-- - -

- - - -_. - -

-- -DIGITAL DATA

~

INTERRUPT PROCESSOR B

CENTRAL PROCESSOR B

+ .4KHZ

OSC Cll( & TIMING

·MEMORY

~

r

OUTPUT 2

DISCRETE COMMANDS TELEMETRY TO FDS

TIMING

t

·ME MORIES APE OPEPATED 1/2 READtWRITE AND 1/2 WRIT< PRO! ECTE 0 (READ ONLYI

Fig. 2 Viking Orhiter Computer CommanO System (oeS)

~

w

(X)

OSC 2.4 KHZ

MEMORY A

CLK &

TIMING

INTERRUPT PROCESSOR

H

A

CENTRAL PROCESSOR A

h~

OTHER SUISVSTfMS

SPECIAL I/O CIRCUITRY

~ OTHfR CONTROL ELEMENTS ~

0

::r ;:3

I

INPUTS-"

I

I

REMOTE DRIVER

f--.-

PYRO & PROPULSION

:;cl

en

()

C

H

INTERRUPT PROCESSOR

•

CENTRAL PROCESSOR

OSC 2.4 KHZ

I

r

1

to-' to-'

-~~ SPECIAL I/O

OTHER SUBSYSTEMS

CIRCUITRY OTHER CONTROl ElEMENTS

MeMORY

CLK &

TIMING

Fig. 1 Voyager

a

~rticuJation

and

~ttitune

Control System (AACS)

On-board Computers for Control

MEMORY A

MEMORY 8

,

•

~

I I I

PROCESSOR

I

DMA

-~ - - - - -COMMAND GENERATOR

TAPE RECORDER I/O

ACS

CCS

CODED COMMAND ENTRY

GOLAY CODER

STATE VECTOR-

MODULATOR I/O

~ DOWN LINK

TO AlL 8LOCKS

OSC &

TIMING CHAIN

ENGINEERING TREE &

~

SCIENCE I/O

ADC

t

ENGINEERING DATA SOURCES

Fig. 4 Voyager Flight OCta System (FDS)

~

_ _~ SCIENCE INSTRUMENTS

John R. Scull

440

NUMBER OF PROGRAMMABLE COMPUTERS IN U.S. PLANETARY SPACECRAFT 20 18 ::::i
16

Vl

14

.... i2

12

<.:l

~

a< w

~

~

u..

=>

10

w

a< w ~

Vl

0

Vl

Z

~

>

<.:l Z

U

0 a< w

.., ~

Cl<

0-0 Vl

6

Cl<

~

a< w

4

~

a<

~

2

R a<

~

..,

~

8

=>

Z

Z ~ ........

> a<

0

U

a< w 0

a<

=>

w

~

>

a< w

~ a<

~

0

YEAR

Fig. 5 Number of progr?mrnable computers in pl?netary spacecrC'ft

MEMORY CAPACITY OF U.S. PLANETARY SPACECRAFT COMPUTERS

~

o Cl< I Vl

o

~

10

3

~

~

w ~

100 L..1960

----''-

---l.

1970

1980

-'--

.....J

1985

1990

YEAR

Fig. h Memory capacity of U.S. planetcry spacecr?ft computers

TOTAL DATA BITS TRANSMITTED FOR U.S. PLANETARY MISSIONS

10 13 Z

10

12

o

~

Q V') V')

~

I

cr'

o

~

1011

t'1

p...

0:::

(")

w

0... V')

10

o

10

::3

"'Cl

C rt

!=

co

u.

0

(l)

t'1

9 10

en

H)

o

0:::

t'1

W

co ~

::> Z

108

(")

o ~

rt

t'1

o

10 7 10

t-"

6

I

60

I

I

I

I

!

62

64

66

68

70

I 72

I

I

I

I

I

74

76

78

80

82

84

85

YEAR

rig. 7 Totf'J

d~r~

hits tr?nsmittC",." hy l'.f'. plC'nf'tr-ry missions ~ ~

442

John R. Scull

o

"-

o

c:

o