On Determining the Speed of Circuits Implemented With LUT-Based FPGA'S

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Copyright © IF AC Programmable Devices and Systems, Ostrava, Czech Republic, 2003

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ON DETERMINING THE SPEED OF CIRCUITS IMPLEMENTED WITH LUT-BASED FPGA'S Andrzej Krasniewski Institute of Telecommunications Warsaw University of Technology

Abstract: We present necessary and sufficient conditions that must be satisfied by an irredundant logical path in a combinational subcircuit of LUT -based FPGAs, i.e. a path that can, under some delay assignment, determine the speed of the circuit. A one-to-one relationship between functionally sensitizable logical paths and irredundant logical paths is found. Thus, a path can be classified as irredundant (or redundant) without any timing infonnation, based exclusively on the user-defined LUT functions and interconnection structure. An example demonstrates the applicability and the importance of the presented results for the evaluation of delay fault testability. Copyright © 2003 I FAC Keywords: digital circuits, timing, delay analysis, testability, fault detection

can significantly exceed the nominal values assumed during the circuit design. Therefore, the development of a test procedure is usually based on an assumption of an arbitrary (unknown) delay assignment, i.e. propagation delays of the circuit components are assumed to have arbitrary positive values. The speed of the circuit is then determined by the propagation delay of some irredundant path, i.e. a path that is true under some delay assignment (Cheng and Chen, 1996).

1. INTRODUCTION Determining the speed of the circuit is important at both design stage and manufacturing stage of the circuit life cycle. At the design stage, the problem is to determine, usually by means of timing simulation based on one of many possible component delay models (Devadas, et al., 1992), if the maximum expected propagation delay of the logic located between memory elements (flip-flops, registers) does not exceed the assumed clock period. One of the reasons for the difficulty of this problem, even for a network of simple gates, lies in that the propagation delay of the network cannot be simply found as a maximum propagation delay for all paths, if the propagation delay of a path is calculated as the sum of propagation delays of all its components. This is because some paths, called false paths, cannot be sensitized to propagate a transition from the input to the output of the circuit, and therefore their propagation delay never determines the circuit performance. For that reason, propagation delays of true paths should only be examined. Unfortunately, the identification of the set of true (or false) paths for a given circuit is not a trivial task.

The verification of temporal correctness, in particular, the identification of a set of irredundant paths, for combinational circuits composed of simple logic gates (NOT, AND, NAND, OR, NOR), has been a subject of many studies (Fuchs, et al., 1994; Lam, et ai., 1995; Sparmann, et al., 1995; Cheng and Cben, 1996; Krstic et al., 1999). Such circuits have a specific feature - their basic logic components (gates) implement Boolean functions that are either positive unate or negative unate in all their variables. This is not the case with LUT-based FPGAs where basic logic components, LUTs, can implement arbitrary Boolean functions. It has been shown that because of this difference, the methods for analysis of excessive delay conditions (delay faults) developed for networks of simple gates are not directly applicable to FPGAs (Krasniewski, 2002a).

After the circuit is manufactured, the timing specifications are verified by means of delay fault testing. Due to imperfections of the fabrication process, propagation delays of the circuit components

In this paper, we derive conditions that allow for the identification of irredundant paths in a combinational

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sub circuit of a LUT-based FPGA. These conditions are timing independent, i.e. the irredundancy (or redundancy) of a path can be decided based exclusively on the user-defmed LUT functions and interconnection structure. We also discuss applications of the presented theoretical results.

rising or a falling transition at the LUT output, depending on the state of the off-paths inputs to the LUT). Therefore, the propagation delay of a path can only be defined for a given path transition pattern, PTP, which specifies for each LC along the path whether a rising transition (i) or a falling transition (..J,) occurs at the output of that LC. If PTP defines for some connection (output of some LC) a rising (falling) transition, we say that initial logic value 0 and final logic value 1 (initial logic value 1 and final logic value 0) are consistent with PT?

2. PATHS AND THEIR PROPAGATION DELAYS IN A LUT-BASED FPGA We consider a combinational subcircuit of a typical LUT -based FPGA programmed to implement some user-defined function. Such a subcircuit can be seen as a network of interconnected logic components (LCs) - mainly LUTs (for the purpose of our analysis, most simple components, such as gates, multiplexers, etc., can be viewed as part of the interconnection structure).

For a network of simple gates, the notion of a logical path is introduced (Sparmann, et al., 1995; Cheng and Chen, 1996). A logical path (also referred to as functional path (Fuchs, et al., 1994» is defined by a path (physical path) and a transition that occurs at its input (or output). Here, we extend this concept. For a network of LCs, a logical path 1t(PTP) is defined by path 1t and path transition pattern PTP. A logical path 1t(PTP) uniquely determines PTP( 1) and PTP(2) - the sets of initial and final logic values associated with all the connections along path 1t. In what follows, if not explicitly stated otherwise, we consider only logical paths that comply with the Le junctions, i.e. such that transitions at the input and output of a given LC have the same (different) polarity if the LC function is positive (negative) unate in its on-path input (Krasniewski, 2002a).

Propagation delays in the considered subcircuit are assigned to logic components and connections. For a single-source multiple-destination user-defined connection, we assume that different delays may be assigned to different source-destination branches. A path (physical path) 1t is an alternating sequence of logic components and connections; individual inputs and outputs of the network are considered as special logic components. For a logic component located on path 1t we distinguish the on-path input (driven by the preceding logic component on 1t) and the off-path inputs. The propagation delay of path 1t is the sum of the propagation delays of all the logic components and connections included in 1t.

As was mentioned earlier, to determine the speed of the circuit, in particular to decide whether or not the propagation delay of the considered network of LCs does not exceed a specified limit (whether or not the network has a delay fault), we should focus on irredundant paths. In the following section, we give a formal defmition of an irredundant logical path and formulate conditions that are satisfied by such a path.

The propagation delay of a path (in particular, an excessive delay caused by a fault condition) can only affect the speed of the network if it is associated with the propagation of a transition that occurs at the input of the path along the whole path. To produce a transition at the input of the path, a pair of vectors applied in two consecutive clock cycles to the input of the network is required. Let
3. IRREDUNDANT LOGICAL PATHS For any pair of input vectors
It is usually assumed that delays that contribute to the propagation delay of a path (delays of LCs and connections) may depend on the polarity of transitions (rising or falling) that occur at the input of the path and at the outputs of LCs along the path (Harris, et al., 2001). It must, however, be noted that, unlike in a network of simple gates, for the considered network of LCs, the polarity of a transition at the input of the path may not determine the polarity of transitions at the outputs of LCs along the path (for example, if a path includes a LUT that implements a XOR function, then a rising transition at the on-path input of the LUT may produce either a

known.

Like for a network of simple gates, we introduce the notion of domination of a logic component by one of its inputs (Cheng and Chen, 1996). For a given delay assignment DA and for a pair of input vectors
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Definition 1: For a given delay assignment, a pair of input vectors
at the time of the last transition at XoP' Le supplied with a PTP-consistent sensitizat vector for Xop, any change that occurs at the input of LC at the last transition at Xop does not affect the 101 value at the output of LC.

Definition 2: A logical path 1t(PTP) is true under delay assignment DA if there exists a pair of input vectors
Lemma 1 is illustrated in Fig. 1. Assume that t logic component LC implements function z = ab + and input a is the on-path input. To comply with t LC function, the transitions at the on-path input aJ at the output of the LC must have the same polari1 Hence, the PTP-consistent sensitization vector f input a is abc = *10. Some possible cases in whit sensitization conditions stated by Lemma 1 a satisfied for the considered LC are shown in Fig. 1.

Definition 3: A logical path 1t(PTP) is redundant if it is false under all delay assignments; otherwise, n(PTP) is irredundant. Definitions 1-3 correspond to similar notions introduced for a network of simple gates (Cheng and Chen, 1996).

(a)

(b) t.

~

t
'.:..y-

As only irredundant logical paths can affect the performance of the circuit, it is essential to derive conditions that would allow one to identify whether or not a particular logical path is redundant (irredundant) without analyzing the timing characteristics of the circuit.

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(d) 1

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For an LC located on a logical path n(PTP) and represented by function F of N input variables, let XE {O,I}N be an input vector and X*E {O,I,*}N be an incompletely specified input vector. Let Xop be the on-path input and z the output of the LC. Let x*(-op) denote an input vector for which Xop = * and all the remaining bit positions (input variables) are specified.

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f-+

Fig. 1. Sensitization conditions for a logic componen that implements function z = ab + c. The "local" sensitization conditions of Lemma 1 illustrated in Fig. 1 are conceptually similar to the timing-dependent path sensitization criterion stated for testing path delay faults in networks of simple gates (Cheng and Chen, 1996). The major difference stems from the fact that the latter are formulated using the notion of controlling and non-controlling values which do not apply to logic components that can implement arbitrary Boolean functions.

Definition 4: An LC input vector x*(-op) is a PTPconsistent sensitization vector for the LC on-path input Xop if F(x*(-op» = Xop in the case when PTP defines the same polarity of transitions at Xop and at z (both rising or both falling), and F(x*(-op» = XoP' in the case when PTP defines different polarities of transitions at Xop and at z (one rising, the other one falling).

The most intuitive concept of timing-independent sensitization of a logical path is that of static sensitization.

It can be seen that for an LC that implements a logic function that is binate in the on-path input, the sensitization vector for the on-path input depends on the path transition pattern. This is not the case for a simple gate for which there is only one sensitization vector for a given on-path input - it is composed of non-controlling values for all off-path inputs.

Definition 5: A pair of input vectors to the network of LCs,
The following Lemma was proven in (Krasniewski, 2002c). Lemma 1: For a given delay assignment DA, a pair of input vectors
Definition 5 corresponds to the notion of static sensitization introduced in the context of testing delay faults in networks of simple gates (Krstic, et al., 1999) (in (Cheng and Chen, 1996), static sensitization by a single vector is defined). It can,

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denoted as xl c x2. iffor each bit position i. i = 1.....

however. be observed that. unlike in networks of simple gates where s-sensitizability by a pair of vectors does not impose any requirements on in( 1). in our case we require that the PTP(I) be produced by in( 1). The concept of static sensitization is illustrated with the following Example.

N. Xli = x2 i or x2 i = *.

Given xCI) and x(2) - input vectors to an LC produced by in(I) and in(2), the transition vector with regard to input Xi, xi(l .2). is defined as follows: for each p~sition j. j = 1..... N : xj(I.2) = xP). ifxil) = xi2) and i j x'iI.2) = *, otherwise.

*

Example 1 - part A: Consider the combinational subcircuit of a LUT-based FPGA shown in Fig. 2. It has five input variables (a. b. c. d. e) and two output variables (w. y). Internal variables (g, h) and output variables are associated with individual LUTs. The functions implemented by the LUTs are given in Fig. 2 in their simplest algebraic representation. Throughout this Example. capital letters are used when referring to LUTs. whereas lower-case letters when referring to the corresponding LUT output variables (e.g. the output variable ofLUT G is g). input

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Definition 6: A pair of input vectors to the network of LCs.
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The second condition in Definition 6 corresponds to the notion of functional sensitization. introduced in the context of testing delay faults in networks of simple gates (Krstic. et al.. 1999). For such a network, the idea of functional sensitization is to represent - besides the obvious case when the offpath inputs of a gate stabilize at non-controlling values before a transition at the on-path input of the gate occurs - the situation when a transition to the controlling value at the on-path input of a simple gate, which occurs earlier than similar transitions at some other inputs of the gate. determines the stabilization time for the gate (this would correspond to the case illustrated in Fig. I (d) if input c were assigned a stable 0 value).

1 ~··t+: ,1 J __ ~ ___ ~ __ ~ 1 _~ __

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Fig. 2. Combinational subcircuit of a LUT-based FPGA. Consider logical path dhiwi. For LUT H. to produce an inverting sensitization vector for the onpath input c. we must have b = I and d == 1. For LUT W. to produce a non-inverting sensitization vector for the on-path input h. we must have g = 1. which is implied by b == 1. Consider input pair: in( 1) == *111* (a = *. b = 1, c = 1. d = 1. e = *). in(2) = *101* (a = *. b = 1. c = O. d = 1. e = *). It can be seen that in(l) produces PTP(I) and in(2) produces PTP(2). Also. in(2) produces PTP-consistent sensitization vectors for the on-path inputs of LUT H and LUT W. Thus. by Definition 5. cJ,hi w i is s-sensitizable. Consider now logical path dhiyi. For LUT H. to produce an inverting sensitization vector for the onpath input c, we must have b = I and d = 1. For LUT Y. to produce a non-inverting sensitization vector for the on-path input h. we must have d = 0 and e = O. The requirements for the two LUTs are contradictory and. thus. dh i yi is not s-sensitizable. It can be shown that the s-sensitization of a logical path 1t(PTP) by a pair of input vectors is a sufficient condition for the sensitization of 1t(PTP) under some delay assignment (as stated in Definition I). It is. however. not a necessary condition. The necessary and sufficient condition corresponds to the notion of functional sensitization which is defined below.

There is an obvious relationship between the concepts of static sensitizability and functional sensitizability - a logical path that is s-sensitizable is also f-sensitizable. The converse is clearly not true. The following Lemma was proven in (Krasniewski. 2002c). Lemma 2: A pair of input vectors to the network of LCs,
An incomjletely specified LC input vector xIE {O.I.*} is covered by another incompletely specified LC input vector x2e {O.I.*}N. which is

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timing characteristics of the circuit. Theorem 1 is based on the concept of functional sensitization which is illustrated with the following Example.

4.

The presented results apply to practical problems associated with the development of various methods and tools related to timing analysis of userprogrammed LUT-based FPGAs, in particular, to testing delay faults in such circuits. The most effective way of implementing a test procedure for a LUT-based FPGA is to rely on the BIST techniques (Stroud, et al., 1996; Krasniewski, 1999; Harris, et ai., 2001). Assuming such a test strategy, our results are essential for the evaluation of the susceptibility of the user-defined circuit to testing and for the evaluation of quality of a specific test procedure. These are measured by: fault testability: the percentage of faults that are detectable, i.e. for which a test exists, fault coverage: the percentage of faults that are detected by the test procedure. These measures can only be calculated for an appropriately selected set of target faults. In the case of path delay faults, the most straightforward selection would be the set of delay faults associated with all logical paths in the circuit. This would, however, lead to the results that in the case of LUTbased FPGAs differ significantly from those obtained when the selection of the set of target faults is based on the path sensitization criteria. This is illustrated in Table I which gives the values of fault testability for the circuit of Fig. 2 for non-robust and robust tests (the requirements for the various types of tests for path delay faults defined for networks of arbitrary logic components can be found in (Underwood, et al., 1994). It should be noted that the values in Table 1 represent also the fault coverage by an exhaustive test sequence containing all pairs of input vectors.

Example 1 - part B: Consider logical path dhiyi which is not s-sensitizable (cf. Example I - part A). Consider input pair . It can be seen that in(l) produces PTP(I) and in(2) produces PTP(2). For LUT H, to produce an inverting sensitization vector for the on-path input c, we must have b = I and d = 1. The transition vector with regard to input c of LUT H produced by <*1110, *1000> has b = 1 and d = *. For LUT Y, to produce a non-inverting sensitization vector for the on-path input h, we must have d = 0 and e = O. The transition vector with regard to input h of LUT Y produced by <*1110, *1000> has d = * and e = O. Thus, by Definition 6, <*1110, *1000> f-sensitizes dhiyi. According to Lemma 2, this means that there exists delay assignment DA, such that <*1110, *1000> sensitizes cJ,.hiyi under DA (which implies that dh i y i is true under DA). Clearly, it does not mean that that <* III 0, *1000> sensitizes cth i y i under any delay assignment. This is illustrated in Fig. 3 which shows the waveforms along path c-h-y for two delay assignments. The waveforms correspond to the inputs and outputs of logic components: C, D, H, Y correspond to the outputs of LUTs and circuit inputs, whereas each waveform marked with the name of a logic component followed by the name of a connection corresponds to the component input driven by that connection (i.e. Hc corresponds to input c ofLUT H). (a) delay assignment DAI C ""''-_ _ _ D - l. He (on·path) --""""1'-_ __ Hd, Vd --:OL.._ __

H ~ Yh (on·path) y YOUTy

.- - ..--,-

.. delay = 10 ..

(b) delay assignment DA2 C 1 '--_ __ _ D , '-_ _ __

Table I. Path delay fault testability for the circuit of Fig. 2

He (on·path) - ----,

Hd, Y~ Yh(on·path) Y YOUTy

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logical paths considered (set of target faults) all logical paths (72 paths) f-sensitizable paths (38 paths) s-sensitizable paths (32 paths)

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----,,-

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APPLICATIONS

delay = 11

..

Fig. 3. Non-sensitization (a) and sensitization (b) of cth i y i under different delay assignments.

non-robust testability

47.2% 84.2% 100.0%

robust testability 36.1 %

68.4% 81.3 %

The data in Table 1 show that a huge misjudgment in the estimation of path delay fault testability can occur if the issue of path sensitization is neglected when selecting the set of target faults (e.g. robust testability of 36.1 % instead of the more appropriate value of 68.4 % would be reported). Experimental data for gate networks, presented in the literature (Sparrnann, et al., 1995; Cheng and Chen, 1996), indicate that for large circuits, the percentage of sensitizable logical paths is generally lower than for small circuits. Thus, we can conjecture that for larger circuits the error made by neglecting the sensitization conditions when calculating the testability measures is likely to be even more significant than it is shown in Table 1.

The first assignment, DAI, is defined as follows: all LUTs and connections have delays equal to 2, except for connection that originates at input c whose delay is equal to 3. For DA1, the on-path input does not dominate LUT H (Fig. 3(a» . Thus, <*1110, *1000> does not sensitize cthiyi. The transition at the output of the path occurs at time = 10 which is not equal to the propagation delay of cthiyi (11 time units). The second assignment, DA2, differs from DAI in that the delay of the connection that starts at input d is equal to 4. For DA2, the on-path input dominates both LUT H and LUT Y (Fig. 3 (b». Thus, <*1110, *1000> sensitizes cthi y i . The transition at the output of the path occurs at time = 11 which is equal to the propagation delay of cthi y i.

As the set of irredundant logical paths, i.e. paths that can affect the speed of the circuit, is equal to the set of f-sensitizable logical paths, an obvious recommendation would be to evaluate the path delay fault testability and test quality for the faults

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associated with f-sensitizable logical paths. This recommendation might, however, be difficult to implement in practice. This is because the identification of the set of f-sensitizable logical paths is computationally quite complex. This complexity is attributed not only to a large number of physical paths (which is typical for many types of circuits), but also to specific features of LUT-based networks, such as a large number of logical paths associated with a particular physical path, and the complexity of conditions that must be examined to decide whether or not a given logical path is f-sensitizable. To avoid difficulties associated with the identification of the set of f-sensitizable logical paths, alternative selections of the set of target path delay faults have been proposed (Krasniewski, 2002b). 5.

for Path Delay Faults Considering Various Test Classes. IEEE Trans. on CAD, 13, pp. 15501562. Harris, I.G., P.R. Menon and R. Tessier (2001). BIST-Based Delay Path Testing in FPGA Architectures. Proc. IEEE Int. Test Cant, pp. 932-938. Krasniewski A (1999). Application-Dependent Testing of FPGA Delay Faults. Proc. 25 th EUROMICRO Cant , pp. 260-267. Krasniewski A (2002a). Testing FPGA Delay Faults: It Is Much More Complicated Than It Appears. In W. CillZynski et a1. (Eds.), Programmable Devices and Systems, pp. 281-286, Pergamon Elsevier Science. Krasniewski A (2002b). Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-Based FPGAs. Lecture Notes in Computer Science, 2438, pp. 616-626, Springer Verlag. Krasniewski A (2002c). On Irredundant Path Delay Faults in LUT-Based FPGAs. Tech. Report, Inst. of Telecommunications, Warsaw Univ. of Tech. Krstic, A., K.-T. Cheng and S.T. Chakradhar (1999). Primitive Delay Faults: Identification, Testing, and Design for Testability. IEEE Trans. on CAD, 18, pp. 669-684. Lam W.K., A Saldanha, R.K. Brayton and AL. Sangiovanni-Vincentelli (1995). Delay Fault Coverage, Test Set Size, and Performance TradeOffs. IEEE Trans. on CAD, 14, pp. 32-44. Sparmann, U., D. Luxenburger, K.-T. Chang and S.M. Reddy (1995). Fast Identification of Robust Dependent Path Delay Faults. Proc. 32nd ACM/IEEE Design Automation Cant, pp. 119125. Stroud C., S. Konala, P. Chen and M. Abramovici (1996). Built-In Self-Test of Logic Blocks in FPGAs (Finally, a Free Lunch: BIST Without Overhead!). Proc. 14th VLSI Test Symp., pp. 387392. Underwood B., W.-O. Law, S. Kang and H. Konuk (1994). Fastpath: A Path-Delay Test Generator for Standard Scan Designs. Proc. IEEE Int. Test Cant, pp. 154-163.

CONCLUSION

We derive necessary and sufficient conditions that must be satisfied by a logical path, so that it could, under some delay assignment, detennine the speed of the circuit. By showing a one-to-one relationship between f-sensitizable logical paths and irredundant logical paths, we can identifY the set of logical paths whose delays (possibly, excessive delays) have impact on the performance of the circuit, based exclusively on the circuit structure - without any information on timing characteristics of the circuit components·. Such conditions have earlier been derived for conventional networks of simple gates, but to the best of our knowledge, this study is the first attempt to do it for LUT-based networks. It should be emphasized that our analysis is not a simple extension of the earlier presented results; it requires a different approach because even such elementary notions like "a controlling value" do not apply to LUTs and similar logic components that can implement arbitrary logic functions. The presented results apply to a number of practical problems associated with the detennining the speed of LUT -based FPGAs, related, in particular, to the evaluation of quality of testing delay faults. We illustrate their relevance with an example of a simple network of LUTs, but the quantitative relations observed in gate networks seem to indicate that for larger FPGA subcircuits their application would be even more important. REFERENCES Cheng K.-T. and H.-C. Chen (1996). Classification and Identification of Non-Robust Untestable Path Delay Faults. IEEE Trans. on CAD, 15, pp. 845853. Devadas, S., K. Keutzer, S. Malik, A Wang (1992). Certified Timing Verification and the Transition Delay of a Logic Circuit. Proc. 29th Design Automation Cant, pp. 549-555. Fuchs, K., M. Pahst and T. Rossel (1994). RESIST: A Recursive Test Pattern Generation Algorithm

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