On the characteristics of an electroless plated (EP)-based pseudomorphic high electron mobility transistor (PHEMT)

Solid-State Electronics 61 (2011) 13–17

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On the characteristics of an electroless plated (EP)-based pseudomorphic high electron mobility transistor (PHEMT) Chien-Chang Huang a, Huey-Ing Chen b, Shiou-Ying Cheng c,⇑, Li-Yang Chen a, Tsung-Han Tsai a, Yi-Chun Liu a, Tai-You Chen a, Chi-Hsiang Hsu a, Wen-Chau Liu a,⇑ a b c

Institute of Microelectronics, Department of Electrical Engineering, National Cheng-Kung University, 1 University Road, Tainan 70101, Taiwan, ROC Department of Chemical Engineering, National Cheng-Kung University, 1 University Road, Tainan 70101, Taiwan, ROC Department of Electronic Engineering, National Ilan University, No. 1, Sec. 1, Shen-Lung Road, I-Lan 26041, Taiwan, ROC

a r t i c l e

i n f o

Article history: Received 14 April 2010 Received in revised form 7 January 2011 Accepted 25 February 2011 Available online 12 April 2011 The review of this paper was arranged by Prof. E. Calleja Keywords: PHEMT Electroless plated (EP) Temperature-dependent characteristics

a b s t r a c t The temperature-dependent characteristics of AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistors (PHEMTs) with electroless plated (EP) deposition approach are systematically studied. Based on the inherent properties of low-temperature and low-energy reaction, this approach can form a well-behaved Schottky interface with a negligible Fermi level pinning effect for superior electric rectifying properties. The studied devices show good DC performance over wide temperature range (300–500 K). In particular, as compared with the device produced by conventional thermal evaporation (TE), the higher turn-on voltage of 0.75 (0.51) V, lower gate leakage current of 3.9 (161) lA/mm at VGD = 15 V, improved threshold voltage of 0.43 (0.61) V, and higher maximum transconductance 225.8 (160.9) mS/mm are obtained, respectively, for the studied EP device at 300 (500) K. In addition, based on the significant advantages of low cost and simple processes, the EP deposition approach provides the promise for electronic device applications. Ó 2011 Elsevier Ltd. All rights reserved.

1. Introduction GaAs-based devices such as high electron mobility transistors (HEMTs) have been extensively used in high-performance microwave and power circuits [1–3]. In order to further improve the device performance, the surface and interface characteristics should be considered more carefully. Based on the disorder-induced gap state (DIGS) model [4], disorders induced currents by the heat damage of the conventional physical vacuum evaporation easily lead to the generation of surface states which subsequently produces a barrier lowering effect. Thus, the quality of Schottky interface appears to heavily depend on the deposition approach. Additionally, under some conditions, the Schottky barrier height is pined at a constant value and nearly independent of the metal work function. This phenomenon is called the Fermi level pinning effect at metal–semiconductor interfaces (M–S) [5]. Many approaches have been reported to overcome this drawback, e.g., a thin interfacial oxide at M–S interfaces [6,7], sulfur or selenium surface treatments [8,9], and the modification of the surface properties by plasma treatments [10,11]. However, these Schottky barriers suffer from instability and poor reproducibility due to ⇑ Corresponding authors. Fax: +886 6 209 4786/3 936 9507. E-mail addresses: [email protected] (S.-Y. Cheng), [email protected] (W.-C. Liu). 0038-1101/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2011.02.006

complex interfacial reactions. By considering the role of electrochemical deposition in passivating the Schottky interface, a new deposition approach, i.e., the electroless plating (EP) is employed in this work to fabricate a high-performance M–S interface. Based on the inherent low-temperature and low-energy characteristics, the EP deposition approach facilitates the formation of a well-behaved Schottky interface with less Fermi-level pinning effect for superior electric rectifying properties [12,13]. Furthermore, the EP deposition approach has the advantages of low cost, simplified process, simple apparatus, and highly promising for use in the IC industry. The EP deposition approach has been applied towards Schottky diodes, which exhibit better electric characteristics than thermal evaporation (TE) does [14,15]. Therefore, the metal gate can be deposited on AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) by using the EP deposition approach. The well-formation Schottky interface is highly promising for enhancing the characteristics of the studied device. 2. Experimental The epitaxial layers of the studied device were grown on a GaAs (1 0 0) semi-insulating (S.I.) substrate by a metal organic chemical vapor deposition (MOCVD) system. From the substrate up, the buffer structure consisted of a 6000 Å GaAs buffer layer, a 150 Å undoped In0.15Ga0.85As strained channel, a 50 Å undoped

C.-C. Huang et al. / Solid-State Electronics 61 (2011) 13–17

Source (AuGe/Au)

Drain (AuGe/Au) Gate (Pd)

Intensity (Arbitrary)

14

500

(111)

P d (fcc)

400 300 200

(222)

(220)

100 30

40

50

60

70

80

90

2θ

Cap (Pd)

barrier

Cap (Pd)

Precursor agent

Reducing agent

deposition

active

Gate (Pd) electronless plating

buffer

barrier

S. I. GaAs Sub. Fig. 1. The schematic cross section of studied device A.

Al0.24Ga0.76As spacer layer, a Si planar-doped sheet with a doping concentration of d(n+) = 3  1012 cm2 as a carrier supplier layer, and a 200 Å n-Al0.24Ga0.76As (n = 3  1017 cm3) Schottky contact layer. The cap layer is 50 Å undoped GaAs. First, mesa isolations were done by wet chemical etching. After mesa isolation, the drain-source Ohmic contacts were formed, using the conventional photolithography, on 50 Å undoped GaAs cap layer by alloying AuGe/Au metal at 340 °C for 40 s. Gate recess etching of 50 Å undoped GaAs cap layer was done by an H3PO4:H2O2:H2O (1:1:50) solution at room temperature. The Pd gate Schottky contact was achieved by EP or TE deposition on the n+-Al0.24Ga0.76As Schottky contact layer. The operation processes of EP approach are explained as follows: (a) surface pretreatment; (b) pattern transferred by photolithography; (c) hard-baked on hot-plate at 90 °C for 30 min; (d) immersing the sample in an EP bath for depositing Pd film as the Schottky contact; (e) lift-off the photoresist (PR) by acetone, and rinsed by D.I. water, and then dried by N2 blow. For comparison, the samples prepared by EP (denoted as device A) and TE (denoted as device B) were fabricated together by using the same process sequence except for the deposition approach of the Schottky contacts. Fig. 1 depicts a schematic cross section of the studied device by EP deposition approach. The gate dimension of 1  100 lm2 was used in this work. As listed in Table 1, a hydrazine-based plating bath was used in this work. The detailed process is listed below: (a) The PdCl2, NH4OH, Na2EDTA, thiourea and deionized water were respectively added into the beaker with a capacity of 100 mL to prepare the precursor solution. (The PdCl2 was used as the palladium precursor and ammonia water as the pH buffer. Small amount of thiourea was added for bath stabilization. The complex agent, Na2EDTA, generates the palladium ions.) (b) Add the appropriate amounts of N2H4 and deionized water into another beaker as reducing agent to react with precursor solution. (c) Blend precursor and reducing agent solution at the volume ratio of 20:1.

Table 1 The composition of precursor and reducing agent solution for palladium deposition. Species

Concentration

Precursor solution Palladium chloride (PdCl2) Seelze, Germany, analytical reagent, P99% Ammonium hydroxide solution (NH4OH) Fluka, Sigma–Aldrich Co. (Seelze, Germany), analytical reagent, 25% Ethylenedinitrilo-tetraacetic acid disodium salt (Na2EDTA, C10H14N2Na2O8) Mallinckrodt Co. (Paris, Kentucky, USA), analytical reagent (ACS grade), 99.3% Thiocarbamide (Thiourea, ((NH2)2CS)) Merck Ltd. (Darmstadt, Germany), analytical reagent, P99% Reducing agent solution Hydrazine (N2H4) (31.875 M)

0.675 g/L 24.375 mL/L

4.375 g/L

3.75  105 g/L

12.5 mL/L

(d) Under room temperature, the mixture solution generates redox reaction until the palladium film on the defined Schottky area is obtained. The chemical reaction equation can be express as:

Oxidation :

N2 H4 þ 4OH ! N2 þ 4H2 O þ 4e

Reduction :

Pd

2þ

þ 2e ! Pd

Total redox reaction : 2Pd  Na2 EDTA

2þ

ð2Þ

þ N2 H4

þ 4OH ! 2Pd þ N2 þ 4H2 O Thiourea

ð1Þ

ð3Þ

The experimental DC current–voltage (I–V) characteristics were measured by an HP4156A semiconductor parameter analyzer at different temperatures. The microwave performance of the studied device was measured by an HP8510C network analyzer (0.5– 50 GHz) in conjunction with Cascade probes at room temperature.

15

C.-C. Huang et al. / Solid-State Electronics 61 (2011) 13–17

0.9

4

0.8

10

Turn–on Voltage V

0.6

Von 2

10 0.5

1

10 0.4

0.3

IG 300

IG (μA/mm) at V GD=-15V

3

10

on

(V)

device A (EP) device B (TE)

0.7

2

1x100μm

350

400

450

0

10 500

Temperature (K) Fig. 2. The turn-on voltage Von and gate current IG at VGD = 15 V as a function of temperature.

2.0 device A (EP) device B (TE)

1.8

0.8

1.6 0.7 1.4 0.6

Ideality Factor n

ΦB

1.2

n 0.5

300

350

400

450

1.0

500

Temperature (K) Fig. 3. The Schottky barrier height UB and ideality factor n as a function of temperature.

2

1x100 μ m VDS= 3 V 400

device A (EP) device B (TE)

Drain Current ID (mA/mm)

600

Drain Saturation Current IDS (mA/mm)

Fig. 2 shows turn-on voltage Von and gate current IG at VGD = 15 V as a function of temperature of the studied devices A (EP approach) and B (TE approach). The Von value is measured under the gate current of IG = 1 mA/mm. The IG values are measured under the gate-drain bias of VGD = 15 V. For devices A and B, the Von values are decreased from 0.75 to 0.51 V and 0.71 to 0.39 V, respectively, as the temperature is increased from 300 to 500 K. The corresponding IG values of devices A and B are 3.9 and 44.5 lA/mm at 300 K. With increasing the temperature to 500 K, the corresponding IG values are increased to 161 and 506 lA/ mm. The gate leakage current of device A is substantially lower than that of device B. It is known that, from experimental results, by mean of a low-temperature and low-energy approach, the EPbased Pd/AlGaAs interface exhibits superior properties than TE one with suffering less thermal damage and disordered-states. Even at higher temperature regimes, the device A still maintains relatively lower values of IG. In addition, the variations of turn-on voltage 4Von and gate leakage current 4IG are 242 (314) mV and 157 (462) lA/mm for device A (B), as the temperature is increased from 300 to 500 K. The related temperature coefficients in turn-on voltage @Von/@T and gate leakage current @IG/@T of device A (B) are 1.25 (1.62) mV/K and 0.72 (2.20) lA/mm K, respectively. It implies that EP deposition approach can substantially suppress the generation of leakage current resulting from the increase of temperature. Therefore, the device A exhibits improved Schottky interface and enhanced I–V rectifying properties. Fig. 3 shows the Schottky barrier height UB and ideality factor n, determined by the gate/drain I–V characteristics, as functions of temperature. For device A (B), the UB is decreased from 0.831 (0.757) to 0.759 (0.718) eV as the temperature is increased from 300 to 500 K, respectively. The corresponding n is increased from 1.10 (1.25) to 1.32 (1.43). Note that the UB is very sensitive to the surface condition of Schottky barrier layer [16]. As compared with device B, the higher UB of device A indicates that the lower interface traps at the Pd/AlGaAs Schottky contact are obtained. This proves that the undesired Fermi level pinning effect is substantially suppressed and the dependence of Schottky barrier height on metal work function is indeed enhanced. The drain saturation current IDS as a function of temperature, under different gate-source voltages VGS, are shown in Fig. 4. The typical common source I–V characteristics of the device A measured at various temperatures are demonstrated in the inset. The applied gate-source voltage VGS is 0.3 V/step and the maximum VGS is +0.9 V. The degraded pinch-off and saturation characteristics

Schottky Barrier Height ΦB (eV)

3. Results and discussion

250 350K V =-0.3V/step 400K 450K

150

500K device A

V = + 0.3V

100

V = 0V

50

V = - 0.6V 0

VGS=+0.9 V

V = + 0.9V

300K1x100μm

200

0

1

2

3

Drain-Source Voltage V DS (V)

200

VGS= 0.6 V

0

VGS= 0 V 300

350

400

450

500

Temperature (K) Fig. 4. The drain saturation current IDS as a function of temperature under different gate-source voltage VGS. The biased voltage is fixed at VDS = 3 V. The inset shows typical common-source I–V characteristics of the device A at various temperatures.

associated with significant gate leakage current caused by the increased of temperature are not observed in the studied device A. The available drain saturation current (41 mA/mm) of device A is lower than that (61 mA/mm) of device B at 300 K, under the bias condition of VGS = +0.0 V. This is mainly caused by the increased Schottky barrier height of EP approach for device A. This may considerably extend the depletion region beneath the gate region and result in the reduced IDSS. Fig. 5 shows the drain saturation current IDS and transconductance gm of devices A and B versus VGS at different temperatures. The bias voltage is fixed at VDS = 3 V. From the measured results shown in this figure, device A has higher maximum transconductance gm,max but narrower VGS operation regime than device B. The measured threshold voltage Vth and its variations DVth as a function of temperature are illustrated in Fig. 6. The biased voltage is fixed at VDS = 3 V. The Vth of device A (B) is decreased from 0.43 (0.57) to 0.61 (0.62) V as the temperature is increased from 300 to 500 K. The device B has a higher magnitude of Vth. This implies that a higher density of defects is produced near the interface for device B which results in a lowering effect of UB [17–19]. Hence the band bending of the Pd/AlGaAs Schottky contact can then be enhanced via the EP deposition approach. The enhanced UB of device A certainly results in the improvement of Vth.

C.-C. Huang et al. / Solid-State Electronics 61 (2011) 13–17

250

1x100 μm

Transconductance g m (mS/mm)

350K 200

VDS=3V

400K

200

450K device B 500K

150

150

100

100

50 50 0 0 -1

0

1

-1

0

Drain Saturation Current IDS (mA/mm)

2

300K

device A

1

Gate-Source Voltage V GS (V) Fig. 5. Transconductance gm and drain saturation current IDS,max versus gate-source voltage VGS for the studied devices at different temperatures.

-0.3

Vth (mV)

-0.4 -100 -0.5

-200

-0.6

-0.7

2

device A (EP)

1x100μm

device B (TE)

VDS=3V

300

350

400

450

500

Threshold Voltage shift

Threshold Voltage V th (V)

0

-300

Temperature (K) Fig. 6. Threshold voltage Vth and variations threshold voltage Vth as a function of temperature. The biased voltage is fixed at VDS = 3 V.

280

240 device A (EP)

IDS

device B (TE)

220

180

gm,max

160

120

2

1x100μm

60

IDS-OP

VDS=3V

300

350

400

450

500

100

Maximum Transconductance g m,max (mS/mm)

Drain Saturation Current IDS (mA/mm) and IDS Operating Regime (>0.9 gm,max) (mA/mm)

Fig. 7 shows the maximum transconductance gm,max, IDS, and drain current operation regime IDS-op (above 90% of gm,max) as s function of temperature. The biased voltage is fixed at VDS = 3 V.

Temperature (K)

The gm,max values of device A (B) are 225.8 (172.5) and 160.9 (137.9) mS/mm at 300 and 500 K, respectively. The corresponding IDS are 220.1 (194.1) and 150.9 (154.9) mA/mm, respectively. The width of IDS operating regime is decreased from 104 (102) to 73 (87) mA/mm for device A (B) as the temperature is increased from 300 to 500 K. As comparing with device B, the device A has advantages of higher gm,max and IDS, but relatively inferior performance on IDS operation regime. Device A exhibits better characteristics at room temperature. Yet, with increasing the temperature, the degradation rate is higher than those of device B. So, the studied device with EP deposition approach shows stronger temperature dependences. The possible reason may originate from the Pd grain size. The surface of EP deposition Pd layer looks rough, which is regularly stacked by Pd grains with the size dimension from 100 to 200 nm [11]. Clearly, as compared with the Pd layer with TE deposition, the one with EP deposition is less dense. The less dense structure of Pd film may exhibit the instability problem at higher temperature and lead to higher degradation rate of these characteristics. Fig. 8 shows the gm, output conductance gds, and voltage gain AV as a function of temperature. The bias voltages are fixed at VDS = 3 V and VGS = 0.3 V. The gm of devices A (B) is decreased from 207.8 (172.8) to 150.5 (132.8) mS/mm as the temperature is elevated from 300 to 500 K. The corresponding gds of device A (B) is increased from 0.44 (0.57) to 2.61 (2.60) mS/mm. Thus, the voltage gain AV (gm/gds) of device A (B) is decreased from 468 (303) to 57.6 (51.1) as the temperature is increased from 300 to 500 K. Obviously, due to the improved gate Schottky characteristics and reduced leakage currents, the relatively higher gm and lower gds of device A are obtained. Hence, a higher AV is obtained for device A. The microwave characteristics of device A at room temperature are shown in Fig. 9. The inset shows the unity current gain cutoff frequency fT and maximum oscillation frequency fmax versus VGS of devices A and B. The bias voltage is fixed at VDS = 3 V. The fT and fmax of the device A (B) extrapolated from the maximum available gain (MAG) are 20.1 (24.2) and 36.8 (50.1) GHz at VDS = 3 V and VGS = +0.9 (+0.6) V. The intrinsic fT and fmax can be expressed as [20]:

fT 

gm g v sat  m  2pðC gs þ C gd þ g m ðRs þ Rd ÞC dg Þ 2pC gs 2pLg

ð4Þ

and

fT fmax  pffiffiffiffiffiffiffiffiffiffi 2 Ri g ds

ð5Þ

220

750

gm 500

165

AV 110

device A (EP)

250

device B (TE) 2

1x100μm VGS=0.3V 2

VDS=3V

0

Voltage Gain Av

250

Transconductance g m (mS/mm), Output Conductance gds (mS/mm)

16

gds

1 0

300

350

400

450

500

-250

Temperature (K) Fig. 7. Maximum transconductance gm,max, maximum drain saturation current IDS,max and drain current operation regimes IDS-OP as a function of temperature. The biased voltage is fixed at VDS = 3 V.

Fig. 8. Transconductance gm, output conductance gds, and voltage gain AV as a function of temperature. The biased voltages are fixed at VDS = 3 V and VGS = 0.3 V.

C.-C. Huang et al. / Solid-State Electronics 61 (2011) 13–17

35 Frequency (GHz)

60

Gain (dB)

28

21

VDS=3V 14

device A (EP) device B (TE)

45 30

T=300K

15 0

VGS=0.9V

fmax

VDS=3V

fT -1.0 -0.5 0.0 0.5 1.0 1.5 Gate-Source Voltage V GS (V)

17

smaller ideality factor (1.10), lower output conductance (0.44 mS/ mm), and higher voltage gain (468) at room temperature. The corresponding unity current gain cutoff frequency fT and maximum oscillation frequency fmax are 20.1 and 36.8 GHz. This indicates that EP deposition approach indeed provides M–S interface and reduces Fermi-level pinning effect. Furthermore, based on the merits of low-temperature and low-energy deposition, the EP approach demonstrates the advantages of simple apparatus, easy operation, mass production, low cost, and being compatible with IC industry. Therefore, the EP deposition approach also shows the promise for electronic device applications.

T=300K 2

1x100μ m 7

0

device A

fT =20.1GHz

H21

fmax=36.8GHz

MSG

1

10

100

Frequency (GHz) Fig. 9. The microwave characteristics of device A at 300 K. The unity current gain cutoff frequency fT and maximum oscillation frequency fmax versus gate-source voltage VGS of the devices A and B are shown in the inset. The bias voltage is fixed at VDS = 3 V.

where Cgs is the capacitance between gate and source, Cgd the capacitance between gate and drain, vsat the electron saturation velocity, Lg the gate length, and Ri the series resistance between gate and source. The fT is directly related to the device geometry according to Eq. (4). The calculated Ri and Cgs of the device A (B) are 169.5 (102.3) X and 1.79 (1.13) pF, respectively. The device A (B) maintains 80% of fT and fmax peak values over VGS operation regimes of 0.62 (1.03) V at 300 K. The device B exhibits better microwave performance than the device A. Again, the possible reason may be the existence of Pd grain size. The larger Pd grain size of device A causes higher contact resistance. So, the microwave characteristics are degraded. 4. Conclusion An interesting AlGaAs/InGaAs/GaAs PHEMTs with an EP based Pd-gate is fabricated and studied. Experimentally, the device with EP deposition approach exhibits the considerably enhanced device characteristics including higher Schottky barrier height (0.831 eV),

Acknowledgments Part of this work was supported by the National Science Council of the Republic of China under Contract No. NSC-97-2221-E-006238-MY3 and NSC-97-2221-E-197-027. The authors are also grateful to National Nano Device Laboratories (NDL) for RF measurements. References [1] Liu WC, Yu KH, Liu RC, Lin KW, Lin KP, Yen CH, et al. IEEE Trans Electron Dev 2001;48:2677. [2] Tsai JH. IEEE Electron Dev Lett 2003;24:1. [3] Lin YS, Hsieh YL. J Electrochem Soc 2006;153:G498. [4] Hasegawa H, Ohno H. J Vac Sci Technol B 1986;4:1130. [5] Yin LW, Hwang Y, Lee JH, Kolbas RM, Trew RJ, Mishra UK. IEEE Electron Dev Lett 1990;11:561. [6] Kolnik J, Ivanco J, Ozvold M, Wyczisk F, Olivier J. J Appl Phys 1993;73:5075. [7] Sugimura T, Tsuzuku T, Katsui T, Kasai Y, Inokuma T, Hashimoto S, et al. SolidState Electron 1999;43:1571. [8] Eftekhari G. Semicond Sci Technol 1993;8:409. [9] Kang MG, Park HH. Jpn J Appl Phys Part 1 2001;40:4454. [10] Herman JS, Terry FL. J Vac Sci Technol A 1993;11:1094. [11] Sugino T, Sakamoto Y, Sumiguchi T, Nomoto K, Shirafuji J. Jpn J Appl Phys 1993;32:L1196. [12] Chen HI, Chou YI, Chu CY. Sens Actuators B 2002;85:10. [13] Chen HI, Chou YI, Hsiung CK. Sens Actuators B 2003;92:6. [14] Chen HI, Hsiung CK, Chou YI. Semicond Sci Technol 2003;18:620. [15] Chen HI, Chou YI. Semicond Sci Technol 2003;18:104. [16] Lai PH, Chen CW, Kao CI, Fu SI, Tsai YY, Hung CW, et al. IEEE Trans Electron Dev 2006;53:1. [17] Lai PH, Liu RC, Fu SI, Tsai YY, Hung CW, Chen TP, et al. J Electrochem Soc 2007;154:H134. [18] Kim YK, Kim S, Seo JM, Ahn S, Kim KJ, Kang TK, et al. J Vac Sci Technol A 1997;15:1124. [19] Moon CR, Choe BD, Kwon SD, Lim H. J Appl Phys 1997;81:2904. [20] Sze SM. Semiconductor devices: physics and technology. 2nd ed. New York: Wiley; 1985.