- Email: [email protected]
On the effect of power cycling stress on IGBT modules
MICROELECTRONICS RELIABILITY Microelectronics Reliability38 (1998) 1347-1352
PERGAMON
On the effect of power cycling stress on IGBT modules P. Cova a, F. Fantini b University of Parma, Dipartimento di Ingegneria dell'Informazione, Viale delle Scienze, 43100 Parma, Italy University of Modena, Dipartimento di Scienze dell'lngegneria and INFM, via G. Campi, 213/b, 41100 Modena, Italy a
Abstract IGBT reliability is becoming of great relevance, due to the range of application of these devices. Nevertheless, no standard test methods have been established, in order to evaluate their power cycling reliability. On this paper we report on the effect of A T and Tjraaz on the power cycling capability of IGBT dice, by means of a matrix of stress cycles with different values of A T and Tjmaz. Failure analysis has been performed, in order to understand the failure mechanisms induced by the stress. O 1998 Elsevier ScienceLtd. All rights reserved.
1. I n t r o d u c t i o n
During the last years the importance of IGBT reliability has continuously increased, due to the widespread use of these devices in many fields, including lighting, power conversion, motor drivers and electronic ovens. To asses their reliability in these applications, power cycling is the most suitable stress test, because the devices are operated in conditions similar to those encountered in the field. In effect, the main cause of failure is the repetitive thermal cycling, which occurs when power cycling is applied [1]. Failure modes of IGBT modules were identified in the past as to be related to A1 wires debonding, due to A1 reconstruction [2], to thermo-mechanical fatigue produced by the repetitive expansion cycles of the wires [3] and to thermo-mechanical problems in the die attach [4, 5].
Recent papers have reported substantial reliability improvements, thanks to new technological solutions [3, 6]. hz spite of the fact that reliability is a key factor for the development of the IGBT technology, only few data are available and no standard test methods have been defined to evaluate the power cycling reliability and the effective impact of the various stress paramenter is not yet established [3, 6, 7]. On this paper we report on the effect of AT and Tjmaz on the stress level during thermal cycling of IGBT modules, by means of the study performed on a matrix of stress cycles employing different values of A T and Tjmaz. Failure analysis is also used, to understand the failure mechanisms induced by the different stresses. In paragraph 2 the measurement set-up is described, paragraph 3 reports on stress cycles results and paragraph 4 deals with the failure analysis. Discussion and conclusions follow.
0026-2714/98/$ - see front matter. C) 1998 Elsevier ScienceLtd. All rights reserved. PlI: S0026-2714(98)00081 -X
1348
P. Cova, F. Fantini/Microelectronics Reliability 38 (1998) 1347-1352
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.
.
.
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,
,
,
,
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VCE[mV]
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Fig. 1. Calibration curve (Tj versus VcE at Ic = 100 mA) for two of the tested IGBTs.
2. M e a s u r e m e n t set-up The tested samples, purchased from various manufacturers, were commercially available medium power devices, packaged in modules containing 6 IGBTs in a three-phase inverter configuration, with fast free-wheeling diodes. Every IGBT was guaranteed for a 10 A, 600 V operation. We report here on the power cycling tests performed on two different lots of samples from the same manufacturer, named in the follow A (from an older production) and B (the newer one). To submit the modules to power cycles, we designed and built-up a system able to supply a predefined square-wave collector current into a single IGBT and to measure at the same time its junction temperature. Fig. 2 shows the block diagram of the measurement equipment. We selected the collector-emitter saturation voltage as a suitable TSP (Temperature Sensitive Parameter), because it exhibits a linear dependence with respect to the junction temperature at a given measuring current [8, 9, 10]. To determine the relationship between VcE and T in the range from 20 °C up to 125 °C (calibration curve, see Fig. 1), we injected the measuring current Im=100 mA in the collector and recorded the corresponding VcE value. The measurements were performed under both continuous and pulsed currents and no differences were observed, so that we can conclude that this level of measuring current does not appreciably influence the junction temperature. The TSP is monitored during the fast electric transient between the on-off conditions, be-
Fig. 2. Block diagram of the circuit used to submit the samples to power cycling and measure the junction temperature. Ic,VcEI
,oA't
. . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .
"" Ic
\ IOOmA
..................
th
Fig. 3. Magnification of the collector current waveform, showing the VcE sampling when Ic = 100 mA.
fore the beginning of the slow thermal transient, when the current level is equal to the measuring current (see Fig. 3). For these measurements, a current power supply, which is able to supply a current up to 20 A with an arbitrary waveform, in accordance with a set-point signal, was built. All measurements are controlled by means of a PC driven board. During the test, the samples are stressed by a rectangular wave collector current and, at every period, the temperature is monitored. The gate voltage is kept high (12 V) during the operation. The module is placed in a thermally controlled chamber, able to establish the ambient tempera-
P. Cova, F. Fantini/Microelectronics Reliability 38 (1998) 1347-1352
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,
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# of cycles Fig. 4. Junction temperature versus the number of cycles for the tested samples. ture, by forced air ventilation, from 0 to 150 °C. The temperature of the device depends on the duty-cycle of the square waveform. W e set the high current level,lh,equal to the m a x i m u m continuous current allowed for the devices (lh --10 A), the low current level above the measurement level (for instance 50 m A ) and, by a trigger system, we measure VcE when Ic = I m =100 mA. If, as in our case, the sampling time (of the order of 10 #s) is much shorter than the time constant of the current supply (hundreds of ps), the error we made in the Tj measurement (i.e. the difference between 100 m A and the real value of the current during the VcE measurement) is negligible. Furthermore, as illustrated by Fig. 3, the time between the heating current switch time (th)and the VCE measurement time (tin)is of the order of hundreds of ps, much shorter than the thermal time constant of the device (hundreds of ms or more).
The test on lot A samples was performed by keeping constant the duty-cycle of the collector current: an increase of the junction temperature
was generally observed in the final part of the test, as shown in Fig. 4. This behaviour was due to the increase of the thermal resistance, probably because of the degradation of the interfaces between the different materials employed. To avoid this positive feedback, which could affect the life-tests results, we introduced a duty-cycle automatic software control, able to keep constant the junction temperature of the device during the whole test. The start-up of this correction and its amount are monitors of the device degradation and we recorded, together with the values of VcE, the duty-cycle variations during the stress.
3. Stress cycles Stress tests on the modules have been performed by subjecting the devices to different power cycles, all with Im --10 A, but with different duty-cycle, which sets the thermal excursion. Table 1 summarizes the parameters of the stresses performed. For samples from lot B we
P. Cova, F. Fantini/Microelectronics Reliability 38 (1998) 1347-1352
1350
Table 1. Main parameters of the stresses performed. Sample
AT (°C)
Tjm~x(°C)
Period (s)
Duty-cycle (%)
# of cycles
Failure
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3
65 65 65 50 50 60 60 70 65 55 60 70 60
90 90 90 82 120 120 120 100 120 100 100 120 120
2.0 2.0 2.5 3.0 3.5 3.5 3.5 21.2 5.7 3.0 3.5 3.8 3.5
50 50 12 80 9.4 35 35 94 33 26 8 22 12
221,000 221,000 553,000 3,300,000 428,500 155,000 140,700 96,300 86,700 239,000 522,400 270,100 437,700
no no
emitter bond lift-off emitter bond damage emitter bond damage emitter bond damage emitter bond damage emitter bond lift-off emitter bond lift-off emitter bond damage to be analyzed to be analyzed to be analyzed
Fig. 5. Photograph of the failed sample A3, showing the break in the emitter bond.
Fig. 6. Photograph of the failed sample A4; the damage in the emitter bond is less evident.
have reported the duty-cycle at the beginning of the stress. Fig. 4 reports on the values of Tj monitored during the stress for all our samples. For most of the samples from lot A both the minimum and maximum temperatures increased in the last part of the test, probably due to the degradation of the die attach thermal resistance, but the thermal excursion was maintained constant. For two samples (A1 and A2) we stopped the stress after the observation of an increase of Tjmax of about 10% and we acquired again the calibration curve, finding a shift of about 5 + 6 °C. It
means that a corresponding variation in the device temperature may occur during the test, in spite of the duty-cycle correction.
4. Failure
analysis
The failed samples were submitted to electrical tests, in order to verify the presence of short or open circuits. All the samples showed an open circuit between emitter and collector. The physical failure analysis was performed by means of optical and SEM failure analysis, after opening
P. Cova, F. Fantini/Microelectronics Reliability 38 (1998) 1347-1352
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AT [°C] Fig. 7. I G B T lifetime versus A T for the tested samples. The numbers close to the symbols are Tjrn==. Dashed lines limit the range of results from many groups, while the bold line represents the interpolation of the whole set of data.
the package and removing the insulating gel. For all the devices we observed a break or a damage of the emitter bond. Fig. 5 and Fig. 6 show two different levelsof device degradation: sample A3 shows a large shiftof the bonding wire; in sample A4, on the contrary, the verticaldisplacement of the wire is less evident, because the photograph was taken at an early phase of degradation. Optical and S E M inspection did not show any macroscopical damage on the die attach, but microscopical internal degradation of the interfaces cannot be excluded at this stage of the analysis.
5. Discussion The measurements on devices from lot B were performed after updating the system with the automatic duty-cycle correction and this improvement has to be taken into account when we compare these results with those obtained on the lot A. To this purpose we have to look at the behaviour of the junction temperature of the samples from lot A during the stress, from which the
onset of thermal resistance increase appears. More data have to be collected, in order to perform a statistical analysis, but from these preliminary results some conclusions can be drawn.
5.1. Dependance of the lifetime versus AT In Fig. 7 we show a collection of lifetime resuits versus A T from our tests and data from literature [3, 6, 7]. The results of life-tests on our samples are represented by the circles (open for lot A, filled for lot B) while the dashed lines show the limits for the data collected from the literature. The bold line is a tentative interpolation of all these data. The sample lifetime seems to be exponentially related to A T and we can extrapolate a device lifetime longer than 10 e cycles for the typical application range ( A T = 20 + 40 °C).
5.e. Influence of Tjma= The values of Tj,n== for our tests are reported close to the circles in Fig. 7. From the analysis of the whole set of data it seems that a high value of Tjmaz (> 120 °C) drastically decreases the
1352
P. Cova, F. Fantini/MicroelectronicsReliability 38 (1998) 1347-1352
lifetime, while at lower Tjm,z a clear dependence is not exhibited.
5.3. Failure modes Even though electrical and optical analysis of the devices demonstrated that the emitter bond damage was the main failure mechanism, the increase of the junction temperature and the shift of the calibration curve of the samples from lot A, clearly indicated that the degradation of the thermal resistance between the die and the heat-sink (which is composed by various layers of different materials), is not negligible. This phenomenon appears mostly related to AT, while no particulax correlation was found with Tjmax.
5.5. Technological improvements Although this observation is at present based on few data, our preliminary measurements on samples from lot B confirmed the influence of the technological improvements on the IGBT modules lifetimes. A correlation with particular technological aspects cannot be made at present because constructive details are not known.
6. C o n c l u s i o n s
Power cycling is the most largely employed test for the reliability evaluation of power IGBTs. The thermal excursion AT has been found to be the more important paramenter in this type of stress, and may be the cause of damage of the soldering layers and bond wires. From the analysis of our data and the results from other groups we can assert that the power cycling lifetime is exponentially related to AT, so that it is possible to evaluate the field lifetime, by means of accelerated test, if the thermal excursion during application is known. For normal application, where thermal excursions range from 20 to 40 °C, IGBT lifetimes longer than 10e cycles can be extrapolated. The maximum temperature operation Tjma~ has a lower impact on the lifetimes, if it does not reach temperatures > 120 °C. This situation limits the possibility of performing accelerated tests at very high Tj,naz without inducing failure modes, which are specific of the test conditions.
We have observed the emitter wire bonding lift-off or damage as the main failure mechanisms, although the degradation of the die attach is probably the root cause of the failure mechanism.
References
[1] Ohga K. Failure analysis of bonding wires in power transistor modules. Proc. ISTFA, 237247, Los Angles, USA, 1991. [2] Malberti P, Ciappa M, Cattomio R. A powercycling-induced failure mechanism of IGBT multichip modules. Proc. ISTFA, 163-168, Santa Clara, USA, 1995. [3] Sankaran V A, Chen C, Avant C S, Xu X. Power cycling reliability of IGBT power modules. IEEE Ind. Appl. Soc. Annual Meeting, New Orleans, USA, 1997. [4] Franceschini G, Fantini F, Salini D, Bricca G, Muschitiello M. Reliability evaluation of power SCR's. Proc. ESREF, 51-54, Scw~ibischGmiind, Germany, 1992. [5] de Lambilly H, Keser H O. Failure analysis of power modules: a look at the packaging and reliability of large IGBTs. IEEE Trans. on CHMT, 16 (1993) 412-417. [6] Sommer K, GSttert J, Lefranc G, Spanke R. Multichip high power IGBT-modules for traction and industrial application. Proc. EPE, 1.112-1.116, Trondheim, Norway, 1997. [7] Hamidi A, Coquery G. Effect of current density and chip temperature distribution on lifetime of high power IGBT modules in traction working conditions. Microelectron. Reliab. 37 (1997) 1755-1758. [8] Baliga B J. Evolution of MOS-bipolar power semiconductor technology. Proc. of IEEE, 76 (1995) 409-418. [9] Baliga B J. Temperature behavior of insulated gate transistor characteristics. Solid State Elect. 28 (1985) 289-297. [10] Cova P, Ciappa M, Franceschini G, Malberti P, Fantini F. Thermal characterization of IGBT power modules. Microelectron. Reliab. 37 (1997) 1731-1734.
PERGAMON
On the effect of power cycling stress on IGBT modules P. Cova a, F. Fantini b University of Parma, Dipartimento di Ingegneria dell'Informazione, Viale delle Scienze, 43100 Parma, Italy University of Modena, Dipartimento di Scienze dell'lngegneria and INFM, via G. Campi, 213/b, 41100 Modena, Italy a
Abstract IGBT reliability is becoming of great relevance, due to the range of application of these devices. Nevertheless, no standard test methods have been established, in order to evaluate their power cycling reliability. On this paper we report on the effect of A T and Tjraaz on the power cycling capability of IGBT dice, by means of a matrix of stress cycles with different values of A T and Tjmaz. Failure analysis has been performed, in order to understand the failure mechanisms induced by the stress. O 1998 Elsevier ScienceLtd. All rights reserved.
1. I n t r o d u c t i o n
During the last years the importance of IGBT reliability has continuously increased, due to the widespread use of these devices in many fields, including lighting, power conversion, motor drivers and electronic ovens. To asses their reliability in these applications, power cycling is the most suitable stress test, because the devices are operated in conditions similar to those encountered in the field. In effect, the main cause of failure is the repetitive thermal cycling, which occurs when power cycling is applied [1]. Failure modes of IGBT modules were identified in the past as to be related to A1 wires debonding, due to A1 reconstruction [2], to thermo-mechanical fatigue produced by the repetitive expansion cycles of the wires [3] and to thermo-mechanical problems in the die attach [4, 5].
Recent papers have reported substantial reliability improvements, thanks to new technological solutions [3, 6]. hz spite of the fact that reliability is a key factor for the development of the IGBT technology, only few data are available and no standard test methods have been defined to evaluate the power cycling reliability and the effective impact of the various stress paramenter is not yet established [3, 6, 7]. On this paper we report on the effect of AT and Tjmaz on the stress level during thermal cycling of IGBT modules, by means of the study performed on a matrix of stress cycles employing different values of A T and Tjmaz. Failure analysis is also used, to understand the failure mechanisms induced by the different stresses. In paragraph 2 the measurement set-up is described, paragraph 3 reports on stress cycles results and paragraph 4 deals with the failure analysis. Discussion and conclusions follow.
0026-2714/98/$ - see front matter. C) 1998 Elsevier ScienceLtd. All rights reserved. PlI: S0026-2714(98)00081 -X
1348
P. Cova, F. Fantini/Microelectronics Reliability 38 (1998) 1347-1352
100 8O 60
.
.
.
.
,
.
.
.
.
,
.
•
,
.
~ q
. CURRENT
SUPPLY
>
Vr
S
o
b-40
! measured
20 O....O~a,~ aIGBT2:T(V)=-0.595*V+523.3 00 .
.
.
.
I 750
,
,
,
,
8 ~I
VCE[mV]
I 850 '
Fig. 1. Calibration curve (Tj versus VcE at Ic = 100 mA) for two of the tested IGBTs.
2. M e a s u r e m e n t set-up The tested samples, purchased from various manufacturers, were commercially available medium power devices, packaged in modules containing 6 IGBTs in a three-phase inverter configuration, with fast free-wheeling diodes. Every IGBT was guaranteed for a 10 A, 600 V operation. We report here on the power cycling tests performed on two different lots of samples from the same manufacturer, named in the follow A (from an older production) and B (the newer one). To submit the modules to power cycles, we designed and built-up a system able to supply a predefined square-wave collector current into a single IGBT and to measure at the same time its junction temperature. Fig. 2 shows the block diagram of the measurement equipment. We selected the collector-emitter saturation voltage as a suitable TSP (Temperature Sensitive Parameter), because it exhibits a linear dependence with respect to the junction temperature at a given measuring current [8, 9, 10]. To determine the relationship between VcE and T in the range from 20 °C up to 125 °C (calibration curve, see Fig. 1), we injected the measuring current Im=100 mA in the collector and recorded the corresponding VcE value. The measurements were performed under both continuous and pulsed currents and no differences were observed, so that we can conclude that this level of measuring current does not appreciably influence the junction temperature. The TSP is monitored during the fast electric transient between the on-off conditions, be-
Fig. 2. Block diagram of the circuit used to submit the samples to power cycling and measure the junction temperature. Ic,VcEI
,oA't
. . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .
"" Ic
\ IOOmA
..................
th
Fig. 3. Magnification of the collector current waveform, showing the VcE sampling when Ic = 100 mA.
fore the beginning of the slow thermal transient, when the current level is equal to the measuring current (see Fig. 3). For these measurements, a current power supply, which is able to supply a current up to 20 A with an arbitrary waveform, in accordance with a set-point signal, was built. All measurements are controlled by means of a PC driven board. During the test, the samples are stressed by a rectangular wave collector current and, at every period, the temperature is monitored. The gate voltage is kept high (12 V) during the operation. The module is placed in a thermally controlled chamber, able to establish the ambient tempera-
P. Cova, F. Fantini/Microelectronics Reliability 38 (1998) 1347-1352
li A8
130
'
'
'
A5
1349
A3
120 110 0
o
I-:- 100 90
A4
>
80 70
,
0e+00
I
J
I
2e+05
4e+05
6e+05
# of cycles Fig. 4. Junction temperature versus the number of cycles for the tested samples. ture, by forced air ventilation, from 0 to 150 °C. The temperature of the device depends on the duty-cycle of the square waveform. W e set the high current level,lh,equal to the m a x i m u m continuous current allowed for the devices (lh --10 A), the low current level above the measurement level (for instance 50 m A ) and, by a trigger system, we measure VcE when Ic = I m =100 mA. If, as in our case, the sampling time (of the order of 10 #s) is much shorter than the time constant of the current supply (hundreds of ps), the error we made in the Tj measurement (i.e. the difference between 100 m A and the real value of the current during the VcE measurement) is negligible. Furthermore, as illustrated by Fig. 3, the time between the heating current switch time (th)and the VCE measurement time (tin)is of the order of hundreds of ps, much shorter than the thermal time constant of the device (hundreds of ms or more).
The test on lot A samples was performed by keeping constant the duty-cycle of the collector current: an increase of the junction temperature
was generally observed in the final part of the test, as shown in Fig. 4. This behaviour was due to the increase of the thermal resistance, probably because of the degradation of the interfaces between the different materials employed. To avoid this positive feedback, which could affect the life-tests results, we introduced a duty-cycle automatic software control, able to keep constant the junction temperature of the device during the whole test. The start-up of this correction and its amount are monitors of the device degradation and we recorded, together with the values of VcE, the duty-cycle variations during the stress.
3. Stress cycles Stress tests on the modules have been performed by subjecting the devices to different power cycles, all with Im --10 A, but with different duty-cycle, which sets the thermal excursion. Table 1 summarizes the parameters of the stresses performed. For samples from lot B we
P. Cova, F. Fantini/Microelectronics Reliability 38 (1998) 1347-1352
1350
Table 1. Main parameters of the stresses performed. Sample
AT (°C)
Tjm~x(°C)
Period (s)
Duty-cycle (%)
# of cycles
Failure
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3
65 65 65 50 50 60 60 70 65 55 60 70 60
90 90 90 82 120 120 120 100 120 100 100 120 120
2.0 2.0 2.5 3.0 3.5 3.5 3.5 21.2 5.7 3.0 3.5 3.8 3.5
50 50 12 80 9.4 35 35 94 33 26 8 22 12
221,000 221,000 553,000 3,300,000 428,500 155,000 140,700 96,300 86,700 239,000 522,400 270,100 437,700
no no
emitter bond lift-off emitter bond damage emitter bond damage emitter bond damage emitter bond damage emitter bond lift-off emitter bond lift-off emitter bond damage to be analyzed to be analyzed to be analyzed
Fig. 5. Photograph of the failed sample A3, showing the break in the emitter bond.
Fig. 6. Photograph of the failed sample A4; the damage in the emitter bond is less evident.
have reported the duty-cycle at the beginning of the stress. Fig. 4 reports on the values of Tj monitored during the stress for all our samples. For most of the samples from lot A both the minimum and maximum temperatures increased in the last part of the test, probably due to the degradation of the die attach thermal resistance, but the thermal excursion was maintained constant. For two samples (A1 and A2) we stopped the stress after the observation of an increase of Tjmax of about 10% and we acquired again the calibration curve, finding a shift of about 5 + 6 °C. It
means that a corresponding variation in the device temperature may occur during the test, in spite of the duty-cycle correction.
4. Failure
analysis
The failed samples were submitted to electrical tests, in order to verify the presence of short or open circuits. All the samples showed an open circuit between emitter and collector. The physical failure analysis was performed by means of optical and SEM failure analysis, after opening
P. Cova, F. Fantini/Microelectronics Reliability 38 (1998) 1347-1352
I
I
I
10 ~ "-.
-
82 ~O
10s
120 "O.,
o
120
O
>' o
I
[
#cycles=1.01X1
-
1351
I
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"-O120
v
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104
10 s
,
30
I
40
,
[
50
,
I
60
,
I
70
,
I
80
,
[
90
,
I
,
100
10
AT [°C] Fig. 7. I G B T lifetime versus A T for the tested samples. The numbers close to the symbols are Tjrn==. Dashed lines limit the range of results from many groups, while the bold line represents the interpolation of the whole set of data.
the package and removing the insulating gel. For all the devices we observed a break or a damage of the emitter bond. Fig. 5 and Fig. 6 show two different levelsof device degradation: sample A3 shows a large shiftof the bonding wire; in sample A4, on the contrary, the verticaldisplacement of the wire is less evident, because the photograph was taken at an early phase of degradation. Optical and S E M inspection did not show any macroscopical damage on the die attach, but microscopical internal degradation of the interfaces cannot be excluded at this stage of the analysis.
5. Discussion The measurements on devices from lot B were performed after updating the system with the automatic duty-cycle correction and this improvement has to be taken into account when we compare these results with those obtained on the lot A. To this purpose we have to look at the behaviour of the junction temperature of the samples from lot A during the stress, from which the
onset of thermal resistance increase appears. More data have to be collected, in order to perform a statistical analysis, but from these preliminary results some conclusions can be drawn.
5.1. Dependance of the lifetime versus AT In Fig. 7 we show a collection of lifetime resuits versus A T from our tests and data from literature [3, 6, 7]. The results of life-tests on our samples are represented by the circles (open for lot A, filled for lot B) while the dashed lines show the limits for the data collected from the literature. The bold line is a tentative interpolation of all these data. The sample lifetime seems to be exponentially related to A T and we can extrapolate a device lifetime longer than 10 e cycles for the typical application range ( A T = 20 + 40 °C).
5.e. Influence of Tjma= The values of Tj,n== for our tests are reported close to the circles in Fig. 7. From the analysis of the whole set of data it seems that a high value of Tjmaz (> 120 °C) drastically decreases the
1352
P. Cova, F. Fantini/MicroelectronicsReliability 38 (1998) 1347-1352
lifetime, while at lower Tjm,z a clear dependence is not exhibited.
5.3. Failure modes Even though electrical and optical analysis of the devices demonstrated that the emitter bond damage was the main failure mechanism, the increase of the junction temperature and the shift of the calibration curve of the samples from lot A, clearly indicated that the degradation of the thermal resistance between the die and the heat-sink (which is composed by various layers of different materials), is not negligible. This phenomenon appears mostly related to AT, while no particulax correlation was found with Tjmax.
5.5. Technological improvements Although this observation is at present based on few data, our preliminary measurements on samples from lot B confirmed the influence of the technological improvements on the IGBT modules lifetimes. A correlation with particular technological aspects cannot be made at present because constructive details are not known.
6. C o n c l u s i o n s
Power cycling is the most largely employed test for the reliability evaluation of power IGBTs. The thermal excursion AT has been found to be the more important paramenter in this type of stress, and may be the cause of damage of the soldering layers and bond wires. From the analysis of our data and the results from other groups we can assert that the power cycling lifetime is exponentially related to AT, so that it is possible to evaluate the field lifetime, by means of accelerated test, if the thermal excursion during application is known. For normal application, where thermal excursions range from 20 to 40 °C, IGBT lifetimes longer than 10e cycles can be extrapolated. The maximum temperature operation Tjma~ has a lower impact on the lifetimes, if it does not reach temperatures > 120 °C. This situation limits the possibility of performing accelerated tests at very high Tj,naz without inducing failure modes, which are specific of the test conditions.
We have observed the emitter wire bonding lift-off or damage as the main failure mechanisms, although the degradation of the die attach is probably the root cause of the failure mechanism.
References
[1] Ohga K. Failure analysis of bonding wires in power transistor modules. Proc. ISTFA, 237247, Los Angles, USA, 1991. [2] Malberti P, Ciappa M, Cattomio R. A powercycling-induced failure mechanism of IGBT multichip modules. Proc. ISTFA, 163-168, Santa Clara, USA, 1995. [3] Sankaran V A, Chen C, Avant C S, Xu X. Power cycling reliability of IGBT power modules. IEEE Ind. Appl. Soc. Annual Meeting, New Orleans, USA, 1997. [4] Franceschini G, Fantini F, Salini D, Bricca G, Muschitiello M. Reliability evaluation of power SCR's. Proc. ESREF, 51-54, Scw~ibischGmiind, Germany, 1992. [5] de Lambilly H, Keser H O. Failure analysis of power modules: a look at the packaging and reliability of large IGBTs. IEEE Trans. on CHMT, 16 (1993) 412-417. [6] Sommer K, GSttert J, Lefranc G, Spanke R. Multichip high power IGBT-modules for traction and industrial application. Proc. EPE, 1.112-1.116, Trondheim, Norway, 1997. [7] Hamidi A, Coquery G. Effect of current density and chip temperature distribution on lifetime of high power IGBT modules in traction working conditions. Microelectron. Reliab. 37 (1997) 1755-1758. [8] Baliga B J. Evolution of MOS-bipolar power semiconductor technology. Proc. of IEEE, 76 (1995) 409-418. [9] Baliga B J. Temperature behavior of insulated gate transistor characteristics. Solid State Elect. 28 (1985) 289-297. [10] Cova P, Ciappa M, Franceschini G, Malberti P, Fantini F. Thermal characterization of IGBT power modules. Microelectron. Reliab. 37 (1997) 1731-1734.