Optical binary logic gate-based modified signed-digit arithmetic

Optics & Laser Technology 34 (2002) 501 – 508

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Optical binary logic gate-based modi%ed signed-digit arithmetic R.S. Fyatha , A.A.W. Alsa,ara , M.S. Alamb; ∗ b Department

a Department of Electrical Engineering, College of Engineering, University of Basrah, Barsah, Iraq of Electrical and Computer Engineering, University of South Alabama, 307 North University Blvd., Mobile, AL 36688-0002, USA

Received 28 November 2001; accepted 17 January 2002

Abstract A new design approach for a three-step modi%ed signed-digit (MSD) adder is presented that can be optically implemented using binary logic gates. The proposed scheme depends on encoding each MSD digits into a pair of binary digits using a two-state and multi-position encoding scheme. The proposed design algorithm depends on constructing the addition truth table of binary-coded MSD numbers and then using Karnaugh map to achieve output minimization. The optical binary logic gates are obtained by simply programming the decoding masks of a shadow-casting-based optical logic gate system. The proposed scheme results in a simple, compact, and e8cient optical binary gate-based parallel addition system. ? 2002 Published by Elsevier Science Ltd. Keywords: Modi%ed signed-digit; Optical logic gate; Binary coded MSD; Shadow-casting system; Decoding mask

1. Introduction Parallel processing and high speed are the two most important features required to enhance the overall performance of today’s digital computers. In electronic computers, the processing speed is limited by the inherent sequential processing as well as by the generation and propagation of carry for arithmetic operations. Optoelectronic computing seems to o,er an attractive solution to overcome the above-mentioned limitations by exploiting some of the excellent features of optics such as inherent parallelism, non-interfering communication, ultrahigh speed, and two-dimensional storage capacity [1–3]. Various number systems, such as the modi%ed signed-digit (MSD) number system have been proposed in the literature to perform carry-free addition and borrow-free subtraction in optoelectronic computing systems [4 – 6]. The MSD number system may have more than one representation for a given decimal number and therefore is denoted as a redundant system. This redundancy property can be successfully utilized in optoelectronic computers to perform arithmetic operations in constant time [7,8]. Di,erent optoelectronic and all-optical implementations have been proposed to perform the arithmetic operations using MSD number system. The implementation may be ∗

Corresponding author. E-mail address: [email protected] (M.S. Alam).

0030-3992/02/$ - see front matter ? 2002 Published by Elsevier Science Ltd. PII: S 0 0 3 0 - 3 9 9 2 ( 0 2 ) 0 0 0 1 5 - 4

based on symbolic substitution algorithm [9,10], shared content-addressable memory [11,12], and optical logic gates [13,14]. The aim of these implementations is to achieve a simple and compact design for a high-speed optoelectronic and=or all-optical arithmetic logic unit. The MSD number system uses three digits {−1; 0; 1}, which cannot be implemented using conventional binary logic gates unless a suitable encoding scheme is adopted. For example, Wong and Cheng [15] proposed a carry-free MSD addition scheme involving optical binary logic operation. Their scheme depends on converting the MSD number into unsigned number by extracting the sign from it. Then a binary logic operation is performed on the unsigned number. Finally, a sign restoration step is introduced at the output stage. Another system has been proposed by Wang et al. [16], which uses a three-position encoding method to optically perform trinary logic operation. In this method [16], the encoding formats for inputs must change for each binary logical processing. Recently, Zhang and Karim [17] proposed a programmable three-step MSD adder using binary logic gates to reduce the complexity encountered in the design of earlier reported systems [15,16]. Their scheme [17] depends on a comparison between the truth table of a three-step binary coded MSD (BCMSD) addition with that of the basic logic gates (AND, OR, EX-OR, and EX-NOR). Then a special function, called mutually exclusive equivalent pair, is applied to follow the speci%ed gate in order to get four transformation digits required to generate the %nal output.

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In this paper, a new three-step MSD adder design is proposed that can be implemented in the all-optical domain using binary logic gates. The proposed scheme depends on the encoding of each MSD digit into a pair of binary digits using a multi-position encoding scheme involving two states. The design equations can be obtained from the BCMSD addition truth table and then output minimization is achieved via Karnaugh map or the Quine–McCluskys tabular reduction method. The proposed scheme can be optically implemented using a shadow-casting system with appropriate programming of associated decoding masks (DMs) subject to the requirements speci%ed by the design equations. This technique results in a simple, compact, and e8cient binary logic gate-based optical arithmetic system. This technique also delineates straightforward guidelines for designing other arithmetic operations based on BCMSD number system and optical logic gates.

2. Three-step MSD adder In general, a decimal number D can be represented in an n-bit MSD number as shown in the following equation: D=

n−1


Xi 2 i :

(1)

i=0

N 0; 1} where 1N In Eq. (1), X is any number of the set {1; denotes −1. Since MSD number is a redundant number system, a decimal number may have more than one representation in the MSD number system. For examN MSD = (1011N1) N MSD = ple, (17)10 = (10001)MSD = (10011) N N N (10111)MSD using 5-bit MSD representation. By exploiting this redundancy, it is possible to perform carry-free MSD addition. This procedure ensures that the arithmetic operation is performed in constant time independent of the operand length. In a three-step MSD addition, the %rst two steps are introduced to ensure that no carry is generated at the third step. Fig. 1 shows a block diagram for the addition of two 5-bit MSD numbers A = (A4 A3 A2 A1 A0 )MSD and B = (B4 B3 B2 B1 B0 )MSD . The three steps are as follows: Step 1 : Table 1a is used to generate the intermediate sum S = (S4 S3 S2 S1 S0 )MSD and carry C = (C4 C3 C2 C1 C0 )MSD bits in parallel. Step 2: The intermediate sum (S) and carry (C) generated in Step 1 are used to yield a second pair of intermediate sum S  =(S4 S3 S2 S1 S0 )MSD and carry C  =(C4 C3 C2 C1 C0 )MSD bits using Table 1b. Step 3: The intermediate sum and carry (S  and C  ) generated in Step 2 are then used to generate the %nal output Z = (Z5 Z4 Z3 Z2 Z1 Z0 )MSD using the rules for carry generation as shown in Table 1a.

Fig. 1. A schematic block diagram for a conventional three-step 5-bit MSD adder. The diagram can also be used to illustrate a three-step BCMSD adder when the input digits Ai and Bi are replaced by (ai1 ai2 , and bi1 bi2 ), respectively, and using the addition rules of Table 2.

The following addition example shows an illustration of the aforementioned algorithm: Addend A Augend B S C S C Sum

Z

= (27)10 = A4 A3 A2 A1 A0 = 11011 N = (−9)10 = B4 B3 B2 B1 B0 = 10111 N = S 4 S3 S2 S1 S0 = I01N100 = C4 C3 C2 C1 C0 = 01111I 1st step output = S4 S3 S2 S1 S0 = I10010 = C4 C3 C2 C1 C0 = 0000II 2nd step output = (18)10 = Z5 Z4 Z3 Z2 Z1 Z0 = 010010 3rd step output

where I denotes a padded zero. This example clearly illustrates that MSD arithmetic operations such as addition can be performed in parallel independent of the operand length. 3. MSD addition using binary logic gates Because MSD number system involves three digits N 0; 1}, it cannot be readily implemented using digital {1; binary logic gates. A binary encoding scheme must be applied to MSD numbers in order to use binary logic gates for implementing a prescribed function. The proposed encoding scheme transforms each MSD digit (X ) into a binary pair of BCMSD digits (x1 x2 ). In the addition operation, the addend A = (A4 A3 A2 A1 A0 )MSD is transformed into (a41 a42 a31 a32 a21 a22 a11 a12 a01 a02 )MSD and the augend A = (B4 B3 B2 B1 B0 )MSD is transformed into

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Table 1 Three-step MSD addition truth table: (a) 1st step symbolic rules, and (b) 2nd step symbolic substitution rules

Table 2 Three-step BCMSD addition truth table: (a) 1st step symbolic rules, and (b) 2nd step symbolic rules

Input

Input

Addend Ai

Output Augend Bi

Carry Ci

Output

Sum Si

Addend 7-8 a1

A2

Augend b1 b2

Carry c1

c2

Sum s1

s2

(a) 1

0

1

0

1

0

0

0

1

0

0

1

0

0

0

0

(a) 1

1

1

0

1 0

0 1

1

1N

1 0

0 0

0 1

0 0

0 1 1N

0 1N 1

0

0

0 1 0

0 0 1

0 0 1

0 1 0

1N 0

0 1N

1N

1

0 0

1 0

0 0

0 1

0

1

1

0

1N

1N

1N

0

0

1

0

1

0

1

0

0

(b) 1

1

1

0

s1

s2

c1

c2

1 0

0 1

0

1

c1

c2

s1

s2

(b) 1

0

1

0

1

0

0

0

0 1 1N

0 1N 1

1 0

0 0

0 1

0 0

0

0

1

0

1N 0

0 1 0

0 0 1

0 0 1

0 1 0

0

0

0

0

1N

0 0

1 0

0 0

0 1

0

1

1

0

0

1

0

1

0

1

0

0

0

0

0 1N

0

1N

1N

1N

0

(b41 b42 b31 b32 b21 b22 b11 b12 b01 b02 )MSD . The binary encoding is realized using a multi-position encoding scheme involving two states (i.e., 1 and 0) as shown in the following equation: 1MSD = 10BCMSD ; 0MSD = 00BCMSD ; 1NMSD = 01BCMSD :

(2)

To implement the MSD adder using binary logic gates, it is necessary to encode the input and output MSD numbers shown in Table 1 according to the rules shown in Eq. (2). Table 2 depicts the truth tables for BCMSD addition. Applying Karnaugh map minimization technique to the outputs of Table 2a, the BCMSD sum S = (s1 s2 ) and carry C = (c1 c2 ) outputs for the %rst step can be expressed as

Input

Output

where the + sign represents logical OR, ⊕ sign represents EX-OR, and the ‘bar’ represents logical NOT operations, respectively. Applying the minimization technique to the outputs of Table 2b, we obtain the following logic equation for the second sum (S  = s1 s2 ) and the second carry (C  = c1 c2 ) of the second step as c1 = s1 c1 + s2 + c2 ; c2 = s1 + c1 + s2 c2 ; s1 = s1 ⊕ c1 + s2 + c2 ; s2 = s1 + c1 + s2 ⊕ c2 :

(4)

c1 = a1 + b1 + a2 + b2 ;

Using the carry rules shown in Table 2a and after applying the minimization technique, the %nal output Z = (z1 z2 ) can be expressed as

s1 = a1 + b1 + a2 ⊕ b2 ;

z1 = s1 + c1 + s2 + c2 ;

c1 = a 1 + b 1 + a 2 + b 2 ;

s1 = a1 ⊕ b1 + a2 + b2 ;

(3)

z2 = s1 + c1 + s2 + c2 :

(5)

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Fig. 2. Binary digital logic-based implementation for three-step MSD adder: (a) 1st step, (b) 2nd step, and (c) 3rd step.

Eqs. (3) – (5) can be easily implemented using simple combinational circuit employing digital logic gates as shown in Fig. 2. It is worth to emphasize that c1 and c2 can be further minimized using the don’t-care conditions of a1 b1 and a2 b2 , respectively. 4. Optical implementation of the proposed scheme We plan to implement the proposed technique using the concept of shadow-casting. Shadow-casting [18] is a lensless system, which can be used for parallel implementation of optical logic gates. The system uses an array of light emitting diodes (LEDs) as the light source in the source plane. The system is capable of performing 16 di,erent basic logic operations for two binary patterns (variables) after decoding them spatially. Fig. 3 shows a schematic block diagram of the shadow-casting system. In Fig. 3, the light

Fig. 3. Lensless shadow-casting system for implementing parallel optical logic gates [18].

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Table 3 The operation of the decoding masks for a three-step MSD adder

Decoding masks

DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8

Shadow-casting logical operation 1st step

2nd step

3rd step

NOR OR OR NOR OR EX-NOR EX-NOR OR

NAND OR OR NAND EX0NOR OR OR EX-NOR

NOR OR OR NOR — — — —

Fig. 4. Spatial encoding of BCMSD input numbers.

Fig. 5 shows an architecture [17] that can be e,ectively utilized to perform each of the three steps required for MSD arithmetic operation. Although this architecture is similar to the one presented in Ref. [17], in our case, it employs di,erent optical logic functions for the programmable decoding masks. It consists of a

Fig. 5. A proposed con%guration for performing each step in the three-step MSD adder, where CP1: composite prism (beam splitter), CP2: composite prism (beam combiner), arid DM: decoding mask.

beam emanating from the LEDs, which are arranged in the form of a square array in the source plane, illuminate the superimposed input object set in the input plane and project multiple shadowgrams of the overlapped pattern into the output plane. The shadowgrams are interlaced over each other depending on the switching mode of the LEDs. To obtain the output corresponding to a logic function, the interlaced shadowgrams are decoded through a decoding mask that contains a square-window-based array in the output plane. Fig. 4 shows all possible 16 combinations of logic functions along with the switching mode of the LEDs. The three-step MSD adder can be optically implemented according to Eqs. (3) – (5) using shadow-casting-based optical binary logic gates. Using shadow-casting technique [18–20], the inputs (for example, a1 , a2 , b1 and b2 ) can be spatially encoded as shown in Fig. 5. Then by superimposing i.e., overlapping two di,erent transparencies (a1 with b1 and a2 with b2 ), it is possible to perform 16 di,erent logic operations as mentioned earlier. These logic operations depend on the decoding masks of the optical shadow-casting system. According to Eqs. (3) – (5), four types of optical logic gates are required (OR, NOR, NAND, and EX-NOR). The decoding masks for these logic gates and the output of the optical system for di,erent input combinations are shown in Fig. 4.

• composite prism (CP1), which is used as a beam splitter, • two-channel optical system that realize the optical logic gates depending on the decoding masks (DM1; DM2; : : : ; DM8), • second composite prism (CP2) is used as a beam combiner, • detector array and NOT gate array that are used to get the output of the step. The operations performed in each step are outlined below: • The inputs containing overlapped transparencies are illuminated by a monochromatic light source. Here a1 is overlapped with b1 (denoted by a1 ∧ b1 ) and a2 is overlapped with b2 (a2 ∧ b2 ), where ∧ represents the overlapping operation. • The composite prism CP1 splits each of the input light beam (modulated by the overlapped transparencies) into four patterns. • Because the optical system consists of two channels introduced between CP1 and CP2, eight logical output beams are generated in parallel according to the programming of the decoding masks, DM1 to DM8. The programming of the decoding masks for each of the three steps of the MSD adder is shown in Table 3. • Each pair of the logical outputs that are generated at the same plane [i.e., (DM1, DM2), (DM3, DM4), (DM5, DM6), and (DM7, DM8)] is combined together by the composite prism based beam combiner CP2. • The %nal output is obtained after applying a NOT gate operation to each signal recorded by the detector array. Figs. 5(a) – (h) illustrate the results when four MSD numbers are added with four other MSD numbers. These numbers and the equivalent BCMSD representations are shown in

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Fig. 6. Illustrative results for an addition example performed using the proposed three-step MSD addition algorithm: (a) decimal Input number and their equivalent BCMSD, (b) 1st step overlapped input transparency, (c) 2nd step overlapped input transparency, (d) 3rd step overlapped input transparency, (e) 1st step NOT gate array output, (f) 2nd step NOT gate array output, and (g) 3rd step NOT gate array output.

Fig. 5(a). The %rst-step input corresponds to the overlapped layers of a1 ∧ b1 and a2 ∧ b2 where each layer consists of 8 × 10 pixels as shown in Fig. 5(b). The overlapping layers for the second and third steps are shown in Figs. 5(c) and (d), respectively. The output generated from the NOT gate array for the %rst step operation is shown in Fig. 5(e). The outputs of the %rst step are then decoded to generate the inputs for the second step. The sum input of the second step is zero-padded from the most signi%cant bit side whereas the carry input is zero-padded from the least signi%cant bit side. These sum (S) and carry (C) inputs are binary coded and overlapped to generate the s1 ∧ c1 and s2 ∧ c2 layers of the second step input, as shown in Fig. 5(c). In this case, each layer consists of 8 × 12 pixels, and the output generated by the NOT gate array for the second step is shown in Fig. 5(f). After zero-padding and binary encoding of the inputs (as in

the %rst step) a 8×14 pixel layer is generated from the NOT gate array as shown in Fig. 5(g). After decoding, the %nal output becomes available as shown in the numerical results of Fig. 5(h). 5. Conclusions A novel approach for designing a three-step MSD adder that can be optoelectronically implemented is proposed. The proposed technique utilizes a multi-position binary encoding scheme and programmable decoding masks for MSD arithmetic and logical operations. Although the MSD number system involves both positive and negative literals (i.e., −1, 0, and 1), the proposed technique utilizes only positive literals (0 and 1) for implementation of the MSD

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Fig. 6. Continued.

arithmetic. Thus, this technique is suitable for implementation both in the optical or electronic domain. The MSD algorithm presented herein has been supported by appropriate design expressions for programming the decoding masks of the optical logic gates. The three-step MSD algorithm technique presented herein can be extended with suitable modi%cation to realize a two-step MSD adder using programmable binary logic gates. (Fig. 6).

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