Optimization of a fractional-N frequency synthesizer for UMTS application with a VHDL-AMS description

Int. J. Electron. Commun. (AEÜ) 61 (2007) 226 – 234 www.elsevier.de/aeue

Optimization of a fractional-N frequency synthesizer for UMTS application with a VHDL-AMS description Ahmed Fakhfakh, Sonia Eloued, Yannick Herve, Nouri Masmoudi∗ Laboratory of Electronics and Technology’s Information, National Engineering School of Sfax, Tunisia Received 1 February 2006

Abstract In this study, we expose new approaches to design and optimize systems at a high level description using Very High Speed Integrated Circuit Hardware Description Language for Analog and Mixed Systems (VHDL-AMS) standard. We detail a theoretical approach to develop self-tuned VHDL-AMS models and we expose some simulations obtained after the optimization of a fractional-N frequency synthesizer’s performances used for wireless systems. The applied optimization method uses the “experience plans” with seven generics having in view to minimize the loop response time and the synthesizer output frequency. 䉷 2006 Elsevier GmbH. All rights reserved. Keywords: Hierarchical design; VHDL-AMS description; Fractional-N frequency synthesizer; Optimization

1. Introduction One of the most challenging RF components to integrate on-chip is a high quality frequency synthesizer. Developing these multi-standard systems further increases the complexity, flexibility and performance requirements of the synthesizer [1]. Behavioural simulation, using a hardware description language, is a promising approach for time-domain analysis of the synthesizer. In fact, the top down methodology is directed by constraints so verification takes place instantaneously and proceeds by downwards propagation of specifications or constraints. It is useful in top-down design to perform a fast and efficient exploration of the design space. After extraction of block generics from transistor-level simulation, behavioural analysis with accurate values corrects errors from architectural choices and speeds up the bottom-up verification process [2]. A VHDL-AMS description of the fractional-N frequency synthesizer allows the verification of its performances and permits to ensure the correctness of the design, especially ∗ Corresponding author. Tel.: +216 74 274 088; fax: +216 74 676 703.

E-mail address: [email protected] (N. Masmoudi). 1434-8411/$ - see front matter 䉷 2006 Elsevier GmbH. All rights reserved. doi:10.1016/j.aeue.2006.05.002

to check circuit operation over range of process and environment variations before doing a transistor level simulation [2]. In our application, the VHDL-AMS description reveals some substantial problems arisen after the implementation of synthesizer’s buildings blocks, such as rising and falling delays, non-symmetrical effects of the charge pump and nonlinearity of the VCO. To optimize their effects, we applied the “experience plan” method. When we develop a VHDL-AMS description, we can only define, in the entity, generics but not specifications. Generics permit to suit the model for new specifications; but this adjustment is done by hand. Consequently, the designer should understand well how the VHDL-AMS description was developed and how chosen topology runs to predict rules that traduce specifications to generics. In this paper, we expose a theoretical approach of needs and possibilities to define generics from specifications. The mapping of specification space into the generic space induces some constraints and methods. If a future standardization of VHDL-AMS includes specification and verification tasks, it will facilitate the designer work and constitute an important step to the development of tools for analogue-synthesis [3]. In addition, it will offer

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the possibility to make virtual prototypes and VHDL-AMS IPs [4]. To illustrate this approach, we propose in this study a self-tuned VHDL-AMS description for a fractional-N frequency synthesizer. The proposed description permits the adjustment of performances by a simple modification of the desired specifications. This application illustrates the difficulties that should be solved to make self-tuned models with the actual VHDL-AMS standard and gives new ideas for a future standardization.

2. Theoretical approach We define for a studied system a set of specifications S = (S1 , S2 , S3 , . . . , SNS ) where NS is the number of specifications. For each Si , we precise a desired value and a constraint domain in which Si will be valid. For example, for a bandwidth (Bp ) specification, we can precise that Bp should equal 100 Hz but must be, in all cases, contained in the interval [90 Hz, 110 Hz]. A constraint domain may be expressed, for instance, as an interval, a maximum or a minimum value. It is also possible to express a constraint domain versus a relationship between two or many specifications. For example, the minimum of the quantity gain ∗ bandwidth may constitute a constraint domain. When introducing the constraint domains, the space S representing the set of specifications is reduced to Ss (Fig. 1). In many cases, it is not possible to satisfy all specifications. So, we define a specification priority and we classify the specifications according to the defined priority (S1 > S2 > S3 > · · · > SNS ). If a solution satisfies the first specifications, it may be considered as suitable one.

M'∞ Ss

Bad solution

M∞

S

227

When a system topology is selected, it can be tuned with a set of generics G = (G1 , G2 , G1 , . . . , GNG ) where NG is the number of generics. The obtained set of generics is completed by some constraints, which can be for example a maximum applied voltage or a minimum current, etc. These constraints are related to the applied process and define an available space called Gc . A specific tuning defines a point in the space Gc but the projection of Gc in the specification space S must have an not empty intersection with SS . If not, the system cannot be realized with the desired specifications. After a simulation of the system with a specific tuning of generics, we obtain a set of measures called Mm = (M1 , M2 , M3 , . . . , MNS ). These measures define a point in the specification space S: if this point Mm is included in the reduced space SS , the obtained solution is accepted. If not, we should modify the tuning of the generics. With current workflow, designers calculate a generic set G and do a measure Mm . If Mm is included in SS (measures satisfy all specifications), the obtained generic set G is a good one. In order to sweep from a near good generic vector to a good one, many optimization algorithms may be used. An automatic and better method consists of finding the transformation that transforms the sub-space SS into a subspace Ga in G. The intersection of this sub space and Gc gives all available tunings. Furthermore, to obtain a robust generic set, the quantity Mi /Gi must be minimized. In this case, a small variation of a generic does not really affect the values of the measure. The passage from the space G to S is simply realized with measures. But the inverse passage is more difficult. If a functional-high-level system description traduces just specifications, we associate one generic for each specification. If we go down in the hierarchical design, the number of

Space of specifications

Ss

Automatic transformation

Good solution

Space of generics

Gc

Gc G

G

By hand tuned system

S

Self tuned system

Fig. 1. Classical approach (By hand designed system) and Automatic synthesis.

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specifications become less than generics (NS < NG ). In this case, the problem becomes more delicate and the designer should have some expressions that define the relationships between generics and specifications. Many classes of systems are possible: Class 1: An analytical passage, completely explicit: in this case, all specifications can be mathematically expressed versus generics (S = f(G)). It is then possible to express generics versus specifications (G = h(S)). Class 2: An analytical passage, partially explicit and implicit: in this case, all specifications can be mathematically expressed versus generics (S = f(G)), but only some generics may be expressed versus specifications: Gi = hi (S) and hk,k=i (Gk , S) = 0. Class 3: An analytical passage, completely implicit: specifications can be mathematically expressed versus generics (S = f(G)), but no generics may be expressed versus specifications: h(G, S) = 0. Class 4: Only some generics may be expressed versus specifications: no mathematical solution may be presented to solve the problem; other solutions should be envisaged. Class 5: In an extreme case, no generics may be expressed versus specifications. It is very useful for a designer to have an automated transformation of specifications into generics. This problem is not really an easy one and so many efforts should be done. In following, we study the case of an automated transformation where NS < NG . The studied example, a Class 2 system, permits an analytical passage, partially explicit and implicit, from specifications to generics.

3. Application: fractional-N frequency synthesizer modelling The fractional-N synthesizer building blocks diagram is shown in Fig. 2. A fractional divider with a division ratio

N/N + 1 divides the output frequency of voltage-controlled oscillator (VCO). The divided frequency is compared to the reference frequency (fref ) by the Phase Frequency Detector (PFD) [5]. The low-pass loop filter filters the output signal and then controls the VCO. If the output frequency decreases, the frequency and phase difference between fdiv and fref will be larger and the phase frequency detector output will increase. Consequently, the output frequency of the VCO will tune until the correct output frequency is reached. This negative feedback mechanism ensures that the output frequency of the synthesizer is locked [5]. The fractional division is achieved by changing periodically the output value “carry” of the accumulator (or a  Modulator). This system is so complex and needs an important simulation runtime at a transistor level design. A behavioural simulation, using a hardware description language allows an easier simulation and characterization. A VHDL-AMS description for the synthesizer was consequently developed using a VHDL-AMS library that contains models for each required block [6]. We added to the developed description a block that transforms specifications to generics to obtain a self-tuned VHDL-AMS description [7]. This added block contains implicit and explicit relationships between specifications and generics. The problem is presented as following: • We introduce four specifications (NS = 4) which traduce synthesizer’s performances: Fmin , Fmax , lcanal and BPLL; where Fmin and Fmax are the minimum and the maximum frequencies of the synthesized band, lcanal the canal width and BPLL the bandwidth of the PLL used in the synthesizer. • We generate height generics (NG = 8): ICP , R, C1 , C2 , f0 , KVCO , T and N ; where ICP is the charge pump current, R, C1 , C2 are loop filter generics, f0 and KVCO are, respectively, the central frequency and the sensitivity

Fref Phase / Frequency Detector

Frequency Divider N/N+1

Input k

charge pump

loop filter

VCO

Accumulator or ΣΔ Modulator

X M1 F out

Fig. 2. Fractional-N synthesizer building blocks diagram.

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UMTS specifications

Specification to generic transformation

Process constrains

Resistance R Capacities CI, C1

Current Ip Fref / M

loop filter

charge pump

Phase/Frequency Detector

Frequency Divider N/N+1

229

VCO

Division ratio N Inputk

Accumulator or ΣΔ Modulator

Central frequency of Accumulator size T Sensibility Kco X M1 Fout

Fractional frequency synthesizer

Fig. 3. A self-tuned model generation.

of the VCO, T is the accumulator size and N is the frequency divider ratio. To transform specifications to generics, we defined mathematical relationships between specifications and generics. To perform filter’s generics, we use Ken Holladay method [8]: — Frequency divider ratio N : Nfrac = Fmin /(M1.(Fref /M)),

(1)

N = TRUNC(Nfrac ).

(2)

J = (Fmax _vco / lcanal ).M1 ,

(11)

int1 = (2.BPLL ),

(12)

int2 = 2..(Xi + (1/(4.Xi ))),

(13)

Fn = (int1 / int2 )(Fn ),

(14)

C2 .J.(2..Fn )2 = Icp .Kvco ,

(15)

2 (Icp .Kvco .C2 ).int = J,

(16)

10.C1 = C2 ,

(17)

R = 2.Xi .int .

(18)

— Accumulator size: Fstep = lcanal /M1 ,

(3)

T = (Fref /Fstep ).

(4)

— VCO generics: Kmin = ((Fmin /(M1.Fref )) − N ).T ,

(5)

Kmax = ((Fmax /(M1.Fref )) − N ).T ,

(6)

Kvco = Kvco_ max ,

(7)

f0 = f0_ max .

(8)

— Charge pump current: Icp = Icp_ max .

(9)

— 2nd-order loop filter generics: DEL = Fmax _vco − Fmin _vco ,

(10)

Fref , M1 and M are generics, directly fixed by the designer. Kmin and Kmax are, respectively, the minimum and the maximum values of the input K providing, respectively, the minimum and the maximum synthesized frequencies. They are automatically performed in the transformation block. DEL is the VCO bandwidth, Fn is the natural frequency and J is the Ratio divider according to VCO frequency. Some constraints are introduced: the minimum and the maximum output frequencies for the VCO (Fmin _vco and Fmax _vco ), the maximum VCO sensitivity (KVCO_ max ), the maximum VCO-central frequency (f0_ max ) and the maximum current for the charge pump (ICP_ max ). Expressions above define generics versus specifications; some are explicit but others are implicit. However, the obtained system can be easily solved with a VHDL-AMS compiler. The developed Specification-to-generic block provides height signals defined in the output ports representing the

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Table 1. Specifications of the frequency synthesizer Synthesized frequency band Channel number Channel width Loop bandwidth (BPLL) Output VCO’s frequency band VCO sensitivity (Kvco) Charge pump current (Icp) M & M1 dividers

[1920 MHz, 1980 MHz] 12 5 MHz 150 kHz [300 MHz, 350 MHz] 50 MHz/V 100 A 6

Table 2. Performed generics Generics

ICP

R

C1

C2

Values Generics Values

100 A f0 325 GHz

33.6 k  KVCO 50 × 106 Hz/V

14.9 nF T 20

0.15 nF N 19

At this step of study, the developed VHDL-AMS description only traduces the ideal functioning of the frequency synthesizer. In order to go deep with this high level description, we introduced additional generics that traduce some process effects and consequently perturb the functioning of the synthesizer. Our target is to study their impact on the system. But in this case, we cannot define implicit or explicit relationships between the added generics and specifications so we have a class 4 system as detailed above. The solution we expose in this study consists in introducing the additional generics in our VHDL-AMS descriptions; then running simulations and introducing the obtained results in an optimization algorithm to fit specifications. In our case, it is not possible to use a traditional optimization method so we applied a special and specific method called the method of “Experience plan” [10]. Fig. 5 illustrates the adopted highlevel design flow.

4. Experience plan application height generics defined above. These signals control the different block of the frequency synthesizer as shown in Fig. 3. In our application, the designed system is used for UMTS standard; synthesizer’s specifications are defined in Table 1. Due to the used VCO’s frequency band, synthesis step and synthesizer channel width were divided by 6 to reduce the synthesized band to [320 MHz, 330 MHz]. Then, a synchronous oscillator multiplied the VCO output by 6 to meet the desired band again [7]. A high level simulation was done using Simplorer 6.0 simulator [9]. The input k was fixed at the value 16, which corresponds to a synthesized frequency equal to 330 MHz. The generics automatically performed from specifications are summarized in Table 2. Fig. 4 shows the synthesizer’s output spectrum in lock condition: we can see that the fundamental is localized at exactly 330 MHz. The simulation and characterization with Simplorer 6.0 needs only few minutes. Whereas, it takes many hours with a transistor level description.

Experience plans have been basically developed by agronomists. It is a research strategy permitting to obtain a maximum of information from a minimum of trials within the framework of phenomenon using several generics. It has been adapted by Deval to optimize electronic systems [10]. Fractional experience plans uses orthogonal matrixes called “Hadamard matrixes” reducing the number of trials. Then a complete plan using 2k trials allows studying 2k−1 instead of k generics. The fractional experience matrix is made as a logic array called “origin plan”. It distributes restricted variables in order to fulfil all possible combinations. The effect of each generic is studied according to two different values to which we attribute levels +1 and −1. Trial results are called “contrasts” because they are a mixture of effects and interactions. To extract effects and interactions, we use a “complementary plan” that presents interactions with opposite signs compared to the original one.

200.0m

100.0m

0 320.0 Meg

325.0 Meg

330.0 Meg

335.0 Meg

Fig. 4. Synthesizer’s output spectrum.

340.0 Meg

FFT (vco.vout)

300.0m

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231

Specifications

Generic generation

Generics

Process characteristics

Additional generics

Simulation

VHDL-AMS description Level 1 (functional)

Characterisation

VHDL-AMS description Level 2 (behavioral)

Simulation

Optimisation algorithm (experience plan)

Characterisation

Fig. 5. High-level design flow.

We define interactions “Ii ” and effects “Ei ”, respectively, as the difference and the summation between contrasts according to origin and complementary plans as follows:   1  Contrast = k Ri−1 , Ri+1 + (19) 2 Ii = 21 (Contrast orig − Contrast comp ),

(20)

Ei = 21 (Contrast orig + Contrast comp ),

(21)

where Ri=+1 , Ri=−1 are trial’s results according to, respectively, i = +1 and i = −1; 2k represents the number of trials. Our target is to obtain an optimized frequency synthesizer via an aimed function  defined as follows: =

  + , TR F

(22)

where TR is the loop filter response and f the synthesizer output frequency error.  and  are constants fixed, respectively, at 1.5e−3 and 10e6 to give the same weight to the two terms of . The experience plan optimization methodology is composed of three steps: initialisation, first experiment and second experiment.

4.1. Initialization step

Table 3. Generic’s values Intensity Trise and Tfall of PFD Trise and Tfall of charge pump Trise and Tfall of VCO Trise and Tfall of N/N + 1 divider Charge pump dissymmetry VCO’s non-linearity coefficient

Tphd (ns) Tpump (ns) Tvco (ns) Tdiv (ns) att1, att2 A

+1

−1

5 5 0.5 5 15% 1

0.5 0.5 0.1 0.5 3% 0.02

the divider N/N + 1 (Tdiv ). These times cause an error on the synthesized frequency [11]. • Non-symmetrical effects into the charge pump: in case of non-symmetrical charge pump, the source pumps Iup and sinks a different current Idn and we define Icp = Iup − Idn . Then non-compensated current pulses appear at the charge pump output [11]. This asymmetry will cause a disturbance on the filter response and consequently on the VCO output frequency. • Non-linearity of the VCO, which can be translated by the addition of a coefficient of non-linearity B. So the VCO output frequency fout is given by Fout = A.Vc + B.Vc2 ,

(23)

The studied generics are summarized mainly on the following points:

where Vc is the input command of the VCO, A the coefficient of proportionality and B the coefficient of nonlinearity.

• The rise and fall times Trise and Tfall introduced in the high level descriptions of the phase frequency comparator (Tphd ), the charge pump (Tpump ), the VCO (TVCO ) and

We have in total six additional generics. Tphd , Tpump , TVCO and Tdiv vary between 1% and 20% of the corresponding input frequency. Charge pump dissymmetry is varying

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Table 4. Origin plan Origin

Tphd

Tpump

TVCO

Tdiv

att1

att2

A

Trial1 Trial2 Trial3 Trial4 Trial5 Trial6 Trial7 Trial8

−1 +1 −1 +1 −1 +1 −1 +1

−1 −1 +1 +1 −1 −1 +1 +1

−1 −1 −1 −1 +1 +1 +1 +1

+1 −1 −1 +1 +1 −1 −1 +1

+1 −1 +1 −1 −1 +1 −1 +1

+1 +1 −1 −1 −1 −1 +1 +1

−1 +1 +1 −1 +1 −1 −1 +1

Table 5. Complementary plan Comp

Tphd

Tpump

TVCO

Tdiv

att1

att2

A

Trial1 Trial2 Trial3 Trial4 Trial5 Trial6 Trial7 Trial8

−1 +1 −1 +1 −1 +1 −1 +1

−1 −1 +1 +1 −1 −1 +1 +1

−1 −1 −1 −1 +1 +1 +1 +1

−1 +1 +1 −1 −1 +1 +1 −1

−1 +1 −1 +1 +1 −1 +1 −1

−1 −1 +1 +1 +1 +1 −1 −1

−1 +1 +1 −1 +1 −1 −1 +1

Table 6. Simulation results

Trial1 Trial2 Trial3 Trial4 Trial5 Trial6 Trial7 Trial8

Origin plan

Origin plan

Comp plan

Comp plan

Origin plan

Comp plan

f (MHz)

TR (s)

f (MHz)

TR (s)





origin

comp

252.99 79.23 232.72 97.92 215.57 183.52 286.95 199.04

266.45 286.06 145.01 226.80 288.85 294.16 214.59 100.64

0.185 0.52 0.14 0.6 0.315 0.1 0.14 0.08

7.54 25 9.3 18.46 8.16 17.96 6.96 20.26

0.20 0.05 0.24 0.07 0.19 0.05 0.17 0.39

between 3% and 15% of Icp and VCO non-linearity should not exceed 10% of AVc. We attribute to each generic two different values representing the minimum and the maximum variations corresponding, respectively, to levels +1 and −1. Table 3 summarizes these values.

4.2. First experiment Generics are randomly distributed in origin and complementary plans as shown in Table 4. Each one requires 8 trials corresponding to 8 simulations. For each one, we calculate the aimed function  according to expression (22). Then, contrasts, effects and interactions are performed by

6.93 17.43 14.64 17.87 6.35 15.93 9.63 20

using expressions (19), (20) and (21). The obtained results are summarized, respectively, in Tables 5 and 6. Generics are classified depending on their effects (absolute values) on the system’s performance. Generics are clustered into groups depending on their influence. Each generic having an effect higher then the half of the maximum one is classified range 1. They are the most influents. Others are less influent. Then we classify generic according to three ranges as following: Generic’s interactions pick up dependencies among generics. Observing interactions, we notice, at range1, that Tpump and Tvco present the highest interactions values. As well, we can see that Tdiv takes both a low effect and a low interaction. Then we decide to reexamine Tpump , Tvco and Tdiv again. Our model is semi-optimized (Table 8).

A. Fakhfakh et al. / Int. J. Electron. Commun. (AEÜ) 61 (2007) 226 – 234

Table 7. Contrasts, effects and interactions

Tphd att1 Tpump A Tvco att2 Tdiv

Table 10. Contrasts, effects and interactions

Contrast orig

Contrast comp

Effects

Interactions

−53.56 23.57 10.66 −11.85 27.78 11.06 −2.11

−0.91 26.25 −56.06 −22.68 −3.26 10.89 7.13

−27.23 24.91 −22.70 −17.27 12.26 10.97 2.51

−26.33 −1.34 33.36 5.41 15.52 0.09 −4.62

Tpump Tvco Tdiv

Origin

Complementary

Effects

Interactions

−5.76 −32.97 8.07

−44.62 3.53 −11.05

−25.19 −14.72 −1.49

19.43 −18.25 9.56

Table 11. Optimum selection of generics

Table 8. Classification of generics Generics Tphd , att1, Tpump , A Tvco , att2 Tdiv

Range1 Range2 Range3

233

4.3. Second experiment In the second experiment we have to analyze three generics (Tpump , Tvco and Tdiv ). We require a 23−1 fractional plan imposing two sets of four simulations. Table 9 shows simulation’s results according to “origin” and “complementary” plans. Effects and interactions are calculated in Table 10. Based on Tables 7 and 10 results, we remark an increase of Tpump and Tvco absolute values effects and a decrease of their interactions. On the other hand, Tdiv has an enhanced interaction value and a poor effect value. Also, we notice that Tpump still has an important interaction value. To improve synthesizer performance, f and TR should be optimum. In fact, a variation of Tphd , Tpump , Tvco , Tdiv and A causes a deviation of the synthesizer output frequency Fout with a large time response TR. As well, a variation of the charge pump dissymmetry (att1, att2) may cause a substantial reduction or shift of the output frequency synthesizer. Better result can be achieved by selecting Tphd , Tpump , Tvco , Tdiv and A on their minimum values and (att1, att2) on their maximum. It provides a compromise to fulfill our aim by a faster loop filter response TR and a minimum synthesizer output frequency error f. Hence, the optimum selection of generic’s values is summarized in Table 11.

Range1

Generics

Level

Value

Range1 Range1 Range1 Range1 Range1 Range2

Tphd Tpump att1 A TVCO att2

−1 −1 +1 −1 −1 +1

0.5 ns 0.5 ns 15% 0.02 0.1 ns 15%

This classification gives information about the mean influent generic on the system. It provides an optimized loop filter response “TR” equal to 7.45 s and a synthesizer output frequency “Fout ” equal to 1980.03 MHz (f = 0.03 MHz). These results suits the UMTS specifications.

5. Conclusion This study exposes a high-level description and simulation with VHDL-AMS of a fractional-N frequency synthesizer system. We show how a high level language can be used to describe such complex system. At this level, we can talk about virtual prototyping making possible the characterisation of a designed system and the prediction of it’s performances before developing a transistor level description. Two types of virtual prototypes are exposed: an ideal one used to verify and to optimize the system’s architecture and a non-ideal prototype used to study the influence of physical generics. We are interested to develop self-tuned VHDL-AMS descriptions that automatically perform generics from system’s specifications and consequently can be easily suited for different specifications. A theoretical approach is proposed in this study and an accurate analysis of lacks and needs of the AMS workflow should be done. An extension of the

Table 9. Simulation results Origin plan

f Trial1 Trial2 Trial3 Trial4



Comp plan TR (s)

f (MHz)

TR (s)





(MHz)

origin

comp

0.185 0.12 0.075 0.165

7.54 8.76 12.85 12.35

0.05 0.15 0.2 0.05

7.5 16.88 8.1 12.73

199.02 171.36 116.93 121.55

200.30 88.96 185.26 118.13

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current VHDL-AMS standard seems necessary in order to taking into account requirements in a most formal approach than currently used tools. The proposed extension allows the propagation of requirements downward through the design hierarchy and to merge measures in order to verify everywhere in the design the concordance of needs and performances [3]. More development of the exposed theoretical approach is important to do. More search efforts are needed to present one or many solutions to solve the five classes of systems presented in this study. It contributes to the development of tools for analogue-synthesis and it will offer the possibility to produce virtual prototypes and VHDL-AMS IPs.

References [1] Ottawa KR. A 4 GHz fractional-N synthesizer for multi-mode wireless applications. www.us.design-reuse.com/articles/ article 6050.html, Canada, 2004. [2] Vachoux A. Modélisation de Systèmes Intégrés Analogiques et Mixtes, Introduction à VHDL-AMS. Laboratoire de Systèmes Microélectroniques EPFL, 2002. [3] Hervé Y, Fakhfakh A. Requirements and verifications through an extension of VHDL-AMS. FDL04, Lille, France, September 2004. p. 111–115. [4] Hervé Y. Langages de haut niveau et flot de conception des systèmes complexes: vers le prototypage virtuel. Dissertation, Louis Pasteur University, Strasbourg, France, 2003. [5] Chun WM. A 1.8-V 2.4-GHz monolithic CMOS inductorless frequency synthesizer for bluetooth application. Diploma thesis, master thesis of philosophy in electrical and electronic engineering, Hong Kong, August 2002. [6] Fakhfakh A. Contribution á la modélisation comportementale des circuits radiofréquence. Dissertation, Bordeaux I University, France, 2002. [7] Eloued S, Fakhfakh A, Loulou M, Masmoudi NYH. High level self-adjusted models and VHDL-AMS application for a frequency synthesizer modeling. FDL’04, Lilles, France, 2004. p. 14–17. [8] Holladay K. Design a PLL for specific loop bandwidth. http//:www.ednmag.com, October 2000. [9] Simplorer reference manual. 2003. [10] Deval Y. Conception de circuits intégrés analogiquesélaboration d’une méthode originale d’optimisation basée sur la technique des plans d’expériences. Dissertation, Bordeaux, France: IXL Laboratory, December 1994. [11] Mannama V, Paavle T. Linearity restrictions for a class of phase frequency detectors, Estonian Acad Sci Eng 2001; 331–346.

Ahmed Fakhfakh received his Electrical Engineering degree in 1997 from Ecole Nationale d’Ingénieurs de Sfax (ENIS), Tunisia; his Master degree in electronics in 1998 and his Ph.D. degree in Electronics in 2002 both from IXL Laboratory, Bordeaux, France. He is an associate professor at the University of Sfax in Tunisia. His research interests

are in the development of VHDL-AMS virtual prototyping, new CAD methods and analogue synthesis tools development. He is member of the group ‘Circuits and Systems’ of the Laboratory of Electronics and Information Technology in Sfax, Tunisia.

Sonia Eloued was born on January 04, 1978, in Moknine, Tunisia. She’s preparing her Ph.D thesis in Electronics (Telecommunications), on the subject of contribution on ICs analogue synthesis. In 2004, she received the Master degree in Electrical Engineering from National engineering school of Sfax, Tunisia. She’s working on analogue synthesis technique using VHDL-AMS behavioural descriptions and she’s developing an analogue design flow for fractional-N frequency synthesizers.

Yannick Hervé received his Aggregation degree from Ecole Normale Supérieure in Electrical Sciences in 1985, his Ph.D. degree in Computer Science and Electronics in 1988 and “Habilitation à Diriger la Recherche” in 2003. He is associate professor at the University Louis Pasteur in Strasbourg, France. His research work is in the field of VHDL-AMS virtual prototyping, formal specifications and new CAD methods. He is within the Department of Complex Systems Modelling and Simulation at the InESS-UNR7163 Laboratory in Strasbourg, France. He is the co-founder and scientific advisor of the systems Virtual Prototyping company.

Nouri Masmoudi was born in Sfax, Tunisia, in 1955. He received the Electrical Engineering degree from the Faculté des Sciences et Techniques de Sfax, Tunisia, in 1982, the DEA degree from the Institut National des Sciences Appliquées de Lyon and Université Claude Bernard de Lyon, France in 1982. From 1986 to 1990, he prepared his thesis at the laboratory of Power Electronics (LEP) at the Ecole Nationale d’Ingénieurs de Sfax (ENIS). He then received the ‘Thèse de 3ème Cycle’ at the Ecole Nationale d’Ingénieurs de Tunis (ENIT), Tunisia in 1990. From 1990 to 2000, he was an assistant professor at the Electrical Engineering department at the ENIS. Since 2000, he has been an associate professor and head of the group ‘Circuits and Systems’ of the Laboratory of Electronics and Information Technology in Sfax. Currently, he is responsible of the Electronic Master Program at ENIS Since 2006, his a professor at ENIS. His research activities have been devoted to several topics: Design, Telecommunications, High-level design flow, Embedded systems and Information technology.