Optimization of thermal processing and device design for high-efficiency c-Si solar cells

Solar Energy Materials and Solar Cells

ELSEVIER

Solar Energy Materials and Solar Cells 48 (1997) 137-143

Optimization of thermal processing and device design for high-efficiency c-Si solar cells T. Warabisako a'*, T. Uematsu a, S. Muramatsu a, K. Tsutsui a, H. Ohtsuka a, Y. Nagata b, M. S a k a m o t o c a Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo 185, Japan bHitachi Device Engineering Co. Ltd., Mobara, Chiba 297, Japan CHitachi ULSI Engineering Co. Ltd., Kodaira, Tokyo 187, Japan

Abstract To improve the cell performance of single-crystal silicon solar cells, the process conditions have been optimized by monitoring the bulk lifetime after each thermal step in the cell fabrication process. The emitter geometry, i.e., front and rear contact size and pitch were optimized, and the cells were fabricated through a set of environmentally considered processes, especially for surface treatment, oxidation, diffusion, and electrode fabrication. Conversion efficiency of 22.3% in a 4 cm 2 cell, and 22.6% in a 1 cm 2 cell, was attained, respectively, with structural features of SiO 2 single-AR, "inverted-pyramid" front texture, point-contact with line-emitter for front electrodes, and locally diffused BSF for rear contacts. Keywords: Solar cell; Crystalline silicon; Carrier lifetime; High efficiency; Thermal process

1. Introduction T r e m e n d o u s efforts are being made to improve the efficiency of crystalline-silicon solar cells. The best results so far have been obtained using a bi-facial contact type structure [1-3]. A g r o u p at the University of N e w South Wales ( U N S W ) has achieved 24% efficiency using a P E R L cell structure [3]. The effective lifetime of a silicon substrate, which reflects the bulk lifetime and surface recombination, is one of the key factors in achieving high-efficiency in crystalline-silicon solar cells. Although silicon

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f. Warabisako et al./Solar Energy Materials and Solar Cells 48 (1997) 137 143

substrates with a bulk lifetime exceeding 1 ms are available today, the succeeding thermal process steps degrade the lifetime to a level that reduces cell performance more than the improvement due to surface and contact passivation, even in a welldesigned cell. Extending the bulk lifetime or improving surface passivation complicate the fabrication process for high-efficiency cells, and some process steps become unacceptable from the environmental point of view. In this paper we describe an improved cell design, including the emitter geometry, and an improved fabrication process from the environmental point of view. Optimizing the process conditions resulted in a device efficiency approaching 23%.

2. Device design 2.1. Cell structure

The solar cell structure we employed is schematically shown in Fig. 1; its design is similar to that of the P E R L cells of the U N S W [ 1 ] and to that of the LBSF cells of the Fraunhofer Institute (FhG-ISE) [2], except for a slight modification in the design of the front n + + layer. It has an inverted-pyramid texture with a 20 p.m pitch on the front surface of the cell as well. The double-emitter structure is composed of a lightly diffused n + layer having sheet resistance of 300 f~/[E over the entire surface of the defined cell area, and a linear, heavily diffused n + + region of 20 f~/E] under the finger electrodes. The rear surface is passivated by a silicon dioxide layer. Boron-diffused local BSF is placed beneath the rear contacts. The rear electrode is A1, so it also acts as a reflecting mirror for light trapping. 2.2. Emitter geomet©' and contact design

We optimized the emitter geometry to obtain a lower series resistance. The detailed analysis for optimizing the emitter and contact design was previously reported [4]. The front contacts often have a point- or line-shape combined with an n + + area of point- or line-shape, respectively. This is due to the process requirement to obtain a heavily diffused area by using dopant diffusion via contact holes. The former design provides a reduced carrier recombination at the contact, but current crowding towards the contact increases the cell series resistance. The latter design reduces series resistance of the cell, but sacrifices recombination loss in the expanded contact area. We use a design including a combination of dot contacts and line-shape heavilydiffused emitters fabricated just beneath the finger electrodes, as shown in Fig. 1. The front contact is made through 4 x 10 p.m holes to the underlying n + + emitter with a spacing of 200 p.m. The rear contact size and pitch are also designed to minimize recombination loss and series-resistance loss. The rear contact is 10 p.m square dots with 250 p.m pitch spacing. The total area of the rear contact is 0.16% of the rear cell surface.

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3. Process design 3.1. Process flow The cell-fabrication process flow is shown in Fig. 2, including the parameters for the high-temperature processing condition. The process flow has been determined so as to maintain the initial bulk lifetime as long as possible. Although there are several thermal treatments, none of the individual oxidation processes was found to significantly degrade bulk lifetime. However, in cell fabrication, the combination of these high-temperature processes was found to degrade bulk lifetime. Especially, the thermal treatment after boron diffusion severely degraded bulk lifetime. We therefore placed the boron diffusion process at the end of the high-temperature steps, as shown in Fig. 2. 3.2. Optimization of thermal process conditions To evaluate the effect of the thermal treatment during cell fabrication, we monitored the wafer bulk lifetime during cell fabrication using FZ, p-type 1 D c m wafers. The change in the bulk lifetime is shown in Fig. 3. The bulk lifetime was measured by using the microwave photoconductive decay (g-PCD) method combined with the iodine passivation technique [5]. The solid line denoted by "bare wafer" in Fig. 3 was obtained by stripping the surface layer of more than 3tam from the substrate after exposed to the process. The dotted line denoted by "covered with oxide" shows the results when the silicon substrate is kept covered with an oxide layer during individual process. Therefore, there is little possibility of suffering from surface contamination and the results indicate the lifetime change along with the thermal experience. We found that oxidation at 1000°C had little effect on the bulk lifetime; however, the lifetime decreased as the fabrication steps progressed. Even so, the bulk lifetime at the end of the fabrication process after hydrogen anneal was still as high as about 60% of the initial value.

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3.3. Basic processes 3.3.1. SupT/&cecleaning T h e w e l l - k n o w n R C A s u r f a c e - c l e a n i n g p r o c e d u r e is c o m m o n l y used prior to surface o x i d a t i o n . H o w e v e r , it c o n s u m e s a c o n s i d e r a b l e a m o u n t of the c h e m i c a l s N H 4 O H , HC1, a n d H 2 0 2 . W e t h u s use o z o n i z e d - w a t e r c l e a n i n g [6] in w h i c h the

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substrate is dipped into de-ionized water containing ca. 10 p p m of ozone, then rinsed in an H F solution and washed in de-ionized water with a low oxygen concentration. We found that this provides an effective lifetime after oxidation similar to that provided by the RCA process. 3.3.2. Oxidation Substrate oxidation in an oxygen ambient containing a small amount of TCA (tri-chloro-ethane) or T C E (tri-chloro-ethylene), or at least in a furnace cleaned in TCA-containing ambient prior to oxidation, provides excellent interface characteristics between the Si substrate and resulting oxide [7]. It has thus been a key process in obtaining good surface passivation for high-efficiency cells [2, 3]. However, these chlorinated organic materials are unwelcome from an environmental view point. We found that an effective lifetime of oxidized wafers (CZ, p-type, 10 ~ cm) of over 300 las can be obtained by using ozonized-water to clean the wafers and a clean furnace that is washed thoroughly and pre-baked at high temperature in a purified gas ambient. 3.3.3. Diffusion In fabricating solar cells, POC13, PBr3, or sometimes PH3 is used for making the n + layer, and BBr3 or sometimes BzH 6 is used for making the p+ layer. Such gaseous diffusion sources require a high-grade scrubbing facility for the exhaust gas. We use solid diffusion sources to diffuse the phosphorus or boron; this requires only ordinary N2, 02, and H2 gases, so no C12 or Br/gases are exhausted [8]. The diffusion source is a mixture of P205 and SiC for phosphorus, and pyrolytic BN for boron, respectively. The former is convenient for providing an n + emitter layer with a controlled surface concentration. 3.3.4. Metallization High-aspect-ratio finger electrodes are needed to obtain high conductance. If these electrodes are plated with Ag, the detoxication of the plating reagent waste is an environmental problem. We thus use an ordinary evaporation procedure with an improved lift-off process produces a finger electrode with a 5 x 5 Jam cross section.

4. Cell fabrication and resulted performance The substrates used for cell fabrication were FZ, p-type, 0.5 ~ cm wafers, 3" in diameter and 250 lam thick. During front electrode fabrication, an aperture was left as a mask for accurately defining the cell area. The total front electrode area was 3.5% of the defined cell area in case of 4 cm 2 cell. The cell efficiencies were measured and identified independently at JQA; the best results obtained are shown in Fig. 4. A conversion efficiency of 22.3% (4 cm z) with Voc = 690 mV, Jsc = 40.7 mA/cm 2, and F F = 0.795, was obtained. We also made 1 cm / test cells on the same wafer. The best conversion efficiency obtained was 22.6% (1 cm 2) with Voc = 681 mV, Jsc = 40.7 mA/cm z, and FF = 0.816. The obtained values were slightly smaller using in-house measurement due to spectral mismatch with the

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secondary standard cell, and were 22.2%, 681 mV, 40.04 m A / c m 2, and 0.815, respectively, for the identical cell. The best values obtained for each parameter using in-house measurement were Voc = 705 mV, Jsc = 40.7 m A / c m z, and F F = 0.832, which imply the possibility of further improvement.

5. Conclusion We have fabricated c-Si solar cells with a conversion efficiency exceeding 22.5% by using a set of processes designed to minimize the environmental effects. The T C A oxidation process, which is t h o u g h t to be indispensable to obtain high efficiency in silicon solar cells, can be eliminated by employing a set of fabrication process and its optimization. The c o m b i n a t i o n of best values for each parameter obtained for small test cells indicates the possibility of attaining an efficiency a p p r o a c h i n g 24% for the p r o p o s e d structure and fabrication process.

Acknowledgements We are grateful to Prof. Tadashi Saitoh at the T o k y o University of Agriculture and T e c h n o l o g y for his input on the lifetime degradation behavior in boron-diffused Si substrates after thermal treatment. This w o r k was supported by the New Energy and Industrial T e c h n o l o g y Development Organization as a part of the New Sunshine P r o g r a m under the Ministry of International Trade and Industry, Japan.

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