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Optimization of WSi2 by SiH4 CVD: impact on oxide quality
Microelectronics Reliability 41 (2001) 1003±1006
www.elsevier.com/locate/microrel
Optimization of WSi2 by SiH4 CVD: impact on oxide quality D. Brazzelli *, G. Ghidini, C. Riva ST Microelectronics, Via C. Olivetti, 2, 20141 Agrate Brianza, Italy
Abstract The deposition of WSi2 on transistor gate in SiH4 /WF6 ambient produces strong variations into the active oxide layer, introducing a signi®cant ¯uorine concentration into the dielectric. This phenomenon is here shown to have dierent eects on p-well and n-well structures and to strongly depend on thermal budget. Dierent amorphization implants after deposition may also be implemented to avoid cracks formations but they will be shown to interact with ¯uorine into the dielectric and strongly impact reliability performances. Ó 2001 Elsevier Science Ltd. All rights reserved.
1. Introduction
2. Substrate doping dependence
The silicidation of transistor gates is a key issue in order to reduce series resistance. When the deposition is done in SiH4 /WF6 ambient, the ¯uorine can drift during subsequent thermal treatments altering the gate oxide thickness and conduction. Also reliability extrapolations are aected by this phenomenon [1]. The determination of which process step is able to in¯uence the F penetration and hence its impact is a critical point in organizing the architecture of a technology including WSi2 silicidation. Moreover, the critical morphology of 0.18 lm FLASH technology causes the generation of cracks, strongly impacting the array world line resistance. Amorphization implant performed right after the layer deposition has been shown to be eective in reducing this problem. Measured structures are ¯at area capacitors with a total area of 1 10 2 cm2 and an oxide thickness of 15 nm (plus the extra growth due to ¯uorine penetration) on n-well and p-well substrate, surrounded by an opposite doped ring to allow measurements in inversion mode. A full fabrication process for FLASH memory, with gate silicidation, two metal levels and passivation has been performed.
The ¯uorine penetration causes an extra growth of gate oxide, catalyzing the subsequent oxidation with interstitial oxygen. The ®nal dielectric thickness has been both evaluated by means of physical (TEM cross-section) and electric techniques [2]. By extrapolating from capacitance measure in accumulation mode for samples with/without WSi2 by SiH4 deposition as shown in Fig. 1 we obtain the same results of 0.7±0.8 nm extra growth found by TEM cross-sections. The dierence between the ellipsometric measurement of the layer and the electric one is the same on nwell and p-well capacitors: this means that the ability of ¯uorine of releasing the interstitial oxygen is not in¯uenced by the B presence into the dielectric, in p-well structures. The second eect of ¯uorine concentration is an extra conduction at low ®elds, reported to occur only with negative polarity [1]. Measurements performed on n-well with negative polarity do not show this behavior, as reported in Fig. 2. This ®nding suggests that the extra conduction in p-well is probably due to a ¯uorine±boron interaction, which causes the formation of traps and hence leaky paths inside the dielectric. Due to this anomalous leakage, the linear dependence of the Fowler±Nordheim voltage with the oxide thickness is no more observable as shown in Fig. 3. Also the trapping properties are in¯uenced by the substrate concentration: Fig. 4 shows DVFN t curves
*
Corresponding author. E-mail address: [email protected] (D. Brazzelli).
0026-2714/01/$ - see front matter Ó 2001 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 0 1 ) 0 0 0 5 7 - 9
1004
D. Brazzelli et al. / Microelectronics Reliability 41 (2001) 1003±1006
Fig. 1. C(V) curves with/without WSi2 by SiH4 .
Fig. 4. I(V) curves in p-well and n-well capacitors.
n-well ones. No dierence is instead observed in positive mode.
3. Fluorine incorporation control
Fig. 2. I(V) curves in p-well and n-well capacitors.
Fig. 3. Voltage necessary to sustain a ®xed injection vs. thickness.
during CCS test performed at 1 10 2 A/cm2 . With the same injection from the n-doped gate a higher trapping rate is observed on p-well capacitors in comparison with
Since the ¯uorine incorporation strongly depends on subsequent steps, dierent process options have been considered. In each trial the voltage necessary to sustain a ®xed current density of 1 10 5 A/cm2 and the oxide thickness have been monitored in p-well capacitors to evaluate the low ®eld conduction properties. As reported in Table 1 dierent thermal treatments obtained in dierent steps have been investigated. Increasing the duration of a 900°C furnace treatment (T1) any signi®cant eect has been found neither on thickness nor on low ®eld conduction. This is probably due to the fact that at 900°C the thermal equilibrium is already reached. A second trial (T2) has hence been introduced, reducing the total thermal budget: the furnace treatment is substituted by a HTO deposition followed by an annealing in NO or in O2 . In this case variation of both chosen parameters, i.e. thickness or low ®eld conduction, can be observed. In Fig. 5 is reported the absolute gate ®eld Vg =tox necessary to sustain a ®xed current density of 1 10 5 A/cm2 . The dierence in voltage measured between the trials cannot be explained with the observed thickness variation but there is a signi®cant higher leakage for the higher furnace thermal budget. With lower thermal treatments not only the amount of ¯uorine penetration is reduced (thickness) but also its interaction with B atoms. The impact of an RTP annealing with temperature ranging from 950°C to 990°C (T3) has been investigated. Even a small change in the RTP annealing temperature
D. Brazzelli et al. / Microelectronics Reliability 41 (2001) 1003±1006
1005
Table 1 Implemented trial on critical steps T1: T2: T3: T4:
furnace HTO RTP Poly-2-anneal
440 900°C thermal 440 900°C thermal 950°C No anneal
280 900°C thermal HTO+NO 990°C Polysilicon anneal
120 900°C thermal HTO+O2 anneal
Table 2 Trials on amorphization implant I1 I2 I3 I4
Fig. 5. Gate ®eld able to sustain 1 10
5
Species
Dose (cm2 )
As As As Ar
1E16 5E15 1E15 1E16
A/cm2 .
Fig. 7. C(V) curves.
Fig. 6. Gate voltage and oxide thickness with dierent RTP temperatures.
is able to in¯uence the ¯uorine penetration, increasing oxide thickness and low ®eld leakage as shown in Fig. 6. A last trial (T4) has been devoted to understand if a polysilicon annealing performed before WSi2 deposition can change the ¯uorine penetration into the layer towards the active oxide. No impact of this variable has been found.
4. Amorphization implants Dierent WSi2 amorphization implants have been implemented, varying both dose and implanting species (As, Ar), as reported in Table 2.
In the C(V) characteristics (Fig. 7) no signi®cant dierence is observed in the case of the lowest As dose (I3) or Ar implantation (I4), while with higher As doses (I1 and I2) a higher oxide thickness is observed. Moreover, a positive charge is also present as shown by a negative C(V) shift. In Fig. 8 the J(V) characteristics are reported. A clear enhancement of leakage current at low ®elds is observed increasing the charged (As) implant dose, on the contrary no eect is observed with Ar implant. The extra conduction cannot be simply explained with thickness dierences, hence besides to a higher ¯uorine penetration there is also a dierent generation of leaky traps. The conduction path formation in the dielectric again shows to be strongly dependent on the presence inside the oxide of charged specie. 5. Reliability performances The oxide defectivity has been evaluated by means of a standard ERCS method.
1006
D. Brazzelli et al. / Microelectronics Reliability 41 (2001) 1003±1006
Fig. 10. DVFN evolution during CCS.
Fig. 8. J(V) curves.
The lowest As dose and Ar implant present a similar behavior to the reference, but very disperse curves are observed.
6. Conclusion
Fig. 9. Qbd distributions and defectivity.
No clear impact of the thermal budget of the implemented trials on reliability performances has been found. On the contrary, the amorphization implants eect is very strong as shown in Fig. 9. In particular, a signi®cant degradation can be observed with the higher doses of As implant in terms of low current failures. Both I3 and I4 exhibit almost no defectivity at low current, but distribution tails are present. Also CCS tests have been performed at a gateinjected current density of 1 10 1 A/cm2 . As observed in Fig. 10 an increase in trapping properties (DVFN ) is detected in As trials with the higher doses.
The ¯uorine incorporation into the oxide due to WSi2 deposition in SiH4 /WF6 ambient has been studied. Two main eects have been shown: an increase in oxide thickness and a leaky path formation. The second aspect depends on the interaction between ¯uorine and reactive atoms, such as incorporated substrate dopant. The interaction of both phenomena with subsequent thermal treatment has been described, showing the importance of careful process architecture to control ¯uorine penetration. The possibility of introducing a WSi2 amorphization implant has been explored using dierent species and doses to avid layer cracks. A clear impact on ¯uorine penetration and oxide leak path formation has been found. Also degradation in term of defectivity has been observed. The interaction depends heavily on the implanted dose. 1 1015 cm2 As implant seems to be feasible as the Ar one. These two last trials should be probably optimized in terms of reproducibility. References [1] Ghidini G, Drera D, Maugain F. Proc IRW 1995;92. [2] Pellizzer F, Pavia G. J Non-Cryst Solids 2001;280:235±40.
www.elsevier.com/locate/microrel
Optimization of WSi2 by SiH4 CVD: impact on oxide quality D. Brazzelli *, G. Ghidini, C. Riva ST Microelectronics, Via C. Olivetti, 2, 20141 Agrate Brianza, Italy
Abstract The deposition of WSi2 on transistor gate in SiH4 /WF6 ambient produces strong variations into the active oxide layer, introducing a signi®cant ¯uorine concentration into the dielectric. This phenomenon is here shown to have dierent eects on p-well and n-well structures and to strongly depend on thermal budget. Dierent amorphization implants after deposition may also be implemented to avoid cracks formations but they will be shown to interact with ¯uorine into the dielectric and strongly impact reliability performances. Ó 2001 Elsevier Science Ltd. All rights reserved.
1. Introduction
2. Substrate doping dependence
The silicidation of transistor gates is a key issue in order to reduce series resistance. When the deposition is done in SiH4 /WF6 ambient, the ¯uorine can drift during subsequent thermal treatments altering the gate oxide thickness and conduction. Also reliability extrapolations are aected by this phenomenon [1]. The determination of which process step is able to in¯uence the F penetration and hence its impact is a critical point in organizing the architecture of a technology including WSi2 silicidation. Moreover, the critical morphology of 0.18 lm FLASH technology causes the generation of cracks, strongly impacting the array world line resistance. Amorphization implant performed right after the layer deposition has been shown to be eective in reducing this problem. Measured structures are ¯at area capacitors with a total area of 1 10 2 cm2 and an oxide thickness of 15 nm (plus the extra growth due to ¯uorine penetration) on n-well and p-well substrate, surrounded by an opposite doped ring to allow measurements in inversion mode. A full fabrication process for FLASH memory, with gate silicidation, two metal levels and passivation has been performed.
The ¯uorine penetration causes an extra growth of gate oxide, catalyzing the subsequent oxidation with interstitial oxygen. The ®nal dielectric thickness has been both evaluated by means of physical (TEM cross-section) and electric techniques [2]. By extrapolating from capacitance measure in accumulation mode for samples with/without WSi2 by SiH4 deposition as shown in Fig. 1 we obtain the same results of 0.7±0.8 nm extra growth found by TEM cross-sections. The dierence between the ellipsometric measurement of the layer and the electric one is the same on nwell and p-well capacitors: this means that the ability of ¯uorine of releasing the interstitial oxygen is not in¯uenced by the B presence into the dielectric, in p-well structures. The second eect of ¯uorine concentration is an extra conduction at low ®elds, reported to occur only with negative polarity [1]. Measurements performed on n-well with negative polarity do not show this behavior, as reported in Fig. 2. This ®nding suggests that the extra conduction in p-well is probably due to a ¯uorine±boron interaction, which causes the formation of traps and hence leaky paths inside the dielectric. Due to this anomalous leakage, the linear dependence of the Fowler±Nordheim voltage with the oxide thickness is no more observable as shown in Fig. 3. Also the trapping properties are in¯uenced by the substrate concentration: Fig. 4 shows DVFN t curves
*
Corresponding author. E-mail address: [email protected] (D. Brazzelli).
0026-2714/01/$ - see front matter Ó 2001 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 0 1 ) 0 0 0 5 7 - 9
1004
D. Brazzelli et al. / Microelectronics Reliability 41 (2001) 1003±1006
Fig. 1. C(V) curves with/without WSi2 by SiH4 .
Fig. 4. I(V) curves in p-well and n-well capacitors.
n-well ones. No dierence is instead observed in positive mode.
3. Fluorine incorporation control
Fig. 2. I(V) curves in p-well and n-well capacitors.
Fig. 3. Voltage necessary to sustain a ®xed injection vs. thickness.
during CCS test performed at 1 10 2 A/cm2 . With the same injection from the n-doped gate a higher trapping rate is observed on p-well capacitors in comparison with
Since the ¯uorine incorporation strongly depends on subsequent steps, dierent process options have been considered. In each trial the voltage necessary to sustain a ®xed current density of 1 10 5 A/cm2 and the oxide thickness have been monitored in p-well capacitors to evaluate the low ®eld conduction properties. As reported in Table 1 dierent thermal treatments obtained in dierent steps have been investigated. Increasing the duration of a 900°C furnace treatment (T1) any signi®cant eect has been found neither on thickness nor on low ®eld conduction. This is probably due to the fact that at 900°C the thermal equilibrium is already reached. A second trial (T2) has hence been introduced, reducing the total thermal budget: the furnace treatment is substituted by a HTO deposition followed by an annealing in NO or in O2 . In this case variation of both chosen parameters, i.e. thickness or low ®eld conduction, can be observed. In Fig. 5 is reported the absolute gate ®eld Vg =tox necessary to sustain a ®xed current density of 1 10 5 A/cm2 . The dierence in voltage measured between the trials cannot be explained with the observed thickness variation but there is a signi®cant higher leakage for the higher furnace thermal budget. With lower thermal treatments not only the amount of ¯uorine penetration is reduced (thickness) but also its interaction with B atoms. The impact of an RTP annealing with temperature ranging from 950°C to 990°C (T3) has been investigated. Even a small change in the RTP annealing temperature
D. Brazzelli et al. / Microelectronics Reliability 41 (2001) 1003±1006
1005
Table 1 Implemented trial on critical steps T1: T2: T3: T4:
furnace HTO RTP Poly-2-anneal
440 900°C thermal 440 900°C thermal 950°C No anneal
280 900°C thermal HTO+NO 990°C Polysilicon anneal
120 900°C thermal HTO+O2 anneal
Table 2 Trials on amorphization implant I1 I2 I3 I4
Fig. 5. Gate ®eld able to sustain 1 10
5
Species
Dose (cm2 )
As As As Ar
1E16 5E15 1E15 1E16
A/cm2 .
Fig. 7. C(V) curves.
Fig. 6. Gate voltage and oxide thickness with dierent RTP temperatures.
is able to in¯uence the ¯uorine penetration, increasing oxide thickness and low ®eld leakage as shown in Fig. 6. A last trial (T4) has been devoted to understand if a polysilicon annealing performed before WSi2 deposition can change the ¯uorine penetration into the layer towards the active oxide. No impact of this variable has been found.
4. Amorphization implants Dierent WSi2 amorphization implants have been implemented, varying both dose and implanting species (As, Ar), as reported in Table 2.
In the C(V) characteristics (Fig. 7) no signi®cant dierence is observed in the case of the lowest As dose (I3) or Ar implantation (I4), while with higher As doses (I1 and I2) a higher oxide thickness is observed. Moreover, a positive charge is also present as shown by a negative C(V) shift. In Fig. 8 the J(V) characteristics are reported. A clear enhancement of leakage current at low ®elds is observed increasing the charged (As) implant dose, on the contrary no eect is observed with Ar implant. The extra conduction cannot be simply explained with thickness dierences, hence besides to a higher ¯uorine penetration there is also a dierent generation of leaky traps. The conduction path formation in the dielectric again shows to be strongly dependent on the presence inside the oxide of charged specie. 5. Reliability performances The oxide defectivity has been evaluated by means of a standard ERCS method.
1006
D. Brazzelli et al. / Microelectronics Reliability 41 (2001) 1003±1006
Fig. 10. DVFN evolution during CCS.
Fig. 8. J(V) curves.
The lowest As dose and Ar implant present a similar behavior to the reference, but very disperse curves are observed.
6. Conclusion
Fig. 9. Qbd distributions and defectivity.
No clear impact of the thermal budget of the implemented trials on reliability performances has been found. On the contrary, the amorphization implants eect is very strong as shown in Fig. 9. In particular, a signi®cant degradation can be observed with the higher doses of As implant in terms of low current failures. Both I3 and I4 exhibit almost no defectivity at low current, but distribution tails are present. Also CCS tests have been performed at a gateinjected current density of 1 10 1 A/cm2 . As observed in Fig. 10 an increase in trapping properties (DVFN ) is detected in As trials with the higher doses.
The ¯uorine incorporation into the oxide due to WSi2 deposition in SiH4 /WF6 ambient has been studied. Two main eects have been shown: an increase in oxide thickness and a leaky path formation. The second aspect depends on the interaction between ¯uorine and reactive atoms, such as incorporated substrate dopant. The interaction of both phenomena with subsequent thermal treatment has been described, showing the importance of careful process architecture to control ¯uorine penetration. The possibility of introducing a WSi2 amorphization implant has been explored using dierent species and doses to avid layer cracks. A clear impact on ¯uorine penetration and oxide leak path formation has been found. Also degradation in term of defectivity has been observed. The interaction depends heavily on the implanted dose. 1 1015 cm2 As implant seems to be feasible as the Ar one. These two last trials should be probably optimized in terms of reproducibility. References [1] Ghidini G, Drera D, Maugain F. Proc IRW 1995;92. [2] Pellizzer F, Pavia G. J Non-Cryst Solids 2001;280:235±40.