- Email: [email protected]
Oscillations in JFETs exhibiting current multiplication in the channel
597
Notes
lorlti 102
DRAIN DDl?REW?fmi&oanp)
Fig. 3. Io vs I,
’
for p-channel JFET T = 155°K. V, cycle; 0, 5% duty cycle.
= 45 volts.
x . 100%duty I
too
m,
zoo 250 TEWEFUTURE
300 CK)
350
400
Fig. 1. !o vs Temp. for typical JFETs at 1% duty V,, = 0. x . n-channel; 0, p-channel.
cycle and
104 ,
/
taking care to hold V, and V, constant and to avoid problems with transients. The pulse rate was 100 Hz with a duty cycle of l-5%. This is adequate to keep power levels in the range found in region A for the d.c. measurements. If self heating is the cause of the nonlinearity in region B. this power reduction should remove the nonlinearity. The pulse data (peak values) are shown in Figs. 2 and 3 for comparison with the d.c. data. Clearly k is very near unity. The same results were obtained for both n- and p-channel devices over a wide range of 1, Figures 2 and 3 show data for only two typical devices. For all devices tested region B of the d.c. curves show 0.78 < k < 0.88. For the pulse tests 0.97 < k < 1.03 over the entire curve. For the curve fit to only region B of the pulse data, similar values of k near unity were obtained indicating no significant nonlinearity. Also similar values of k were found for region A of the d.c. data. It is then concluded that the nonlinearities found earlier are due to self heating and that the only important mechanism generating 1, at low temperatures is impact ionization in the channel.
Acknowledgements-The A:van
4
.
,
DRAIN ‘%fWENT Fig. 2. lo v
,
Engineering Depf. University of Florida GainesuiNe, FL 32611, U.S.A.
Electrical
,
(&
for n-channel JFET T = IWK, V, x , 100% duty cycle; 0, 1% duty cycle. I,
authors wish to express thanks to Dr. der Ziel and Dr. A. Sutherland for assistance. L. M. RUCKER E. R. CHENEITE
= 40 volts.
first taken at d.c. Io was controlled by varying V, V, V, The shown Figs. and have nonat currents k 1). part the is B the At currents k is very near unity. This part of the curve is labeled A. The same measurements were made using pulse techniques
Depanment of Electronics Technology H-1521 Budapest Hungay
A. AUBROZY
REFEUFNCES 1. E. P. Fowler, Elecrron. Len. 4(1 I), (19W. 2. R. D. Ryan. Proc. IEEE, 1225 11%9). 3. A. Ambrozy, Periodica Polyrech Elect. Engng 14, 355 (1970).
OSCILLATIONS IN JFETs EXHIBITING CURRENT MULTIPLICATION IN THE CHANNEL (Received 18 July 1977; in revised form
It is the purpose of this a junction field effect multiplication exhibits method for calculating verify the calculation.
correspondence to show that the gate of transistor (JFET) experiencing channel a negative conductance, to present a the conductance and measurements to
1 September
1977)
In 1968 Fowlder[ I] reported an enhanced drain current in FETs and in I%9 Ryan[2] identified the mechanism as impact ionization in the channel. This is commonly referred to as multiplication and is most pronounced in short channel FETs at low temperature. The ionization process generates majority and
598
Notes
minority carriers in equal numbers. The majority carrier flows down the channel to contribute to the enhancement of drain current. The minority carrier is quickly removed from the channel by the gate depletion region. The gate current is then equal to the enhancement of the drain current. This assumes the thermal component of gate current to be negligible, which is reasonable since the multiplication phenomenon is generally studied at much reduced temperature. In our discussion the following polarities are chosen: I, and 1, print into the device and 1s prints out of the device. The minority carrier collected by the gate depletion region causes a negative gate conductance. The value of this conductance can be found as follows. The multiplication factor, M is defined as: M = IdI,.
II)
Fig. I. Circuit
used to measure
Table
R,
10
M
-g,,
Calculated
bmho)
R, (Kohm)
is: 1, = Is - lo
(2a)
= Is - MIS
(2b)
= -I&v
(2c)
- I).
1000 I20
For a small variation
of VGs then: (3)
‘d” = &lb,, where id0 and g,,,, are values of i, and g,,, without Hence the ax. currents id and i, are i, = -i,,(M
(4)
since the a.c. currents are multiplied by the same factors d.c. currents, which gives the input conductance as:
as the
g,, = i&‘
+ I) = -g,,u,,(M
= -g,,(M
- I).
(5)
This negative conductance can become sufficiently large to cause instabilities or oscillations in common amplifier circuits. To check the value of input conductance. the circuit of Fig. 1 was constructed. The FET is placed in liquid nitrogen CT= 77°K) to enhance the multiplication process. The resistor R, was removed and Voo adjusted to produce a small oscillation at the gate as observed on an oscilloscope. The amplitude of the oscillation was less than IOmv. The gate was then connected to the electrometer to measure &. fo was measured and M found from: M = fc&
- ro,
g,, is then found using eqn S(b). The tance of the tank, R,, is: R, = l/g,,
= I/g,.
(6) equivalent
parallel
resis-
M---2N4220A---g, 33.5 I .0089 34.5 1.0091 41.5 1.0110
= 4.64 mmho 40.80 41.92 50.66
DEVICE 1.68
N---2N4220A---g, 19.02 1.0114
= 4.18 mmho 47.87
19.45 22.27 22.98
I.0117 1.0133 1.0136
48.96 55.48 56.94
FH R-5 49.77 50.81 57.40 58.95
(U or F)--g, = 14.0 mmho 1.0039 52.95 1.0039 54.16 9-G 1.0044 61.14 123 1.0045 62.80 102
I.68 1.70 1.71
1000 120 100
DEVICE 13.2 13.2 13.2 13.2
894 102
913 131
I IO
to a peak value of 0.33 V for device N and 0.68 V for device M. Pinch off voltage for device N is 066V and for device M is 1.25 V. The mean value of spr is zero in each case. The data of Table I is a good demonstration that the multiplication mechanism produces a negative input conductance. The value of the conductance can be calculated using eqn (5b) and measured using the circuit of Fig. I. The negative conductance 5,. occurs in a wide frequency range, so that the circuit can oscillate over a wide frequency range when the turned circuit is properly adjusted. At very high frequencies transit time effects give use to a positive conductance in parallel to -g,(M - I), and oscillations cease when the total input conductance becomes positive. An understanding of the negative conductance will be useful in avoiding problems in the use of JFETs. In addition this is an indication of a limitation in the design of new short-channel JFETs since a shorter channel length, which has several desirable effects, leads to an increase in multiplication and greater possibility of stability difficulties.
(7)
Various values of R, are then used in the circuit and the procedure is repeated. At the threshold of oscillation g,, is equal to R, in parallel with R, which may be found by: R, = t/(g, - g,.).
DEVICE 3.81 3.82 3.81
1000 120 100
multiplication.
- I).
id = i&f,;
I
47
(Kohm) (ma) baa) The gate current
g,. of the FET.
(8)
This may be compared to the known value of R, to verify the value of g,. The data and results are shown in Table I for three n-channel JFETs. Two are 2N4220As and one was manufactured at the University of Florida. It should be noted that although measurements and results in Table I are for much reduced temperature, the same oscillation was observed in n-channel devices at room temperature. The amplitude of va, grew rapidly with slight increases of voo
Acknowledgemenf-The authors wish to thank Dr. A. Sutherland for helpful advice and suggestions. Necrrical Engineering Dept. C’niuersiry of Minnesota Minneapolis. MN 55455, U.S.A. Necrrical Engineering Depf. University of Florida Gainesville. FL 32611. U.S.A.
A. VAN DER ZlEL
L. M. RUCKER
REFERENCES I. E. P. Fowler, Electronics Lerr. 4(11), 216 (Nov. 19613). 2. R. D. Ryan, Proc. IEEE, 57(6), 1225-1226 (June 1%9).
Notes
lorlti 102
DRAIN DDl?REW?fmi&oanp)
Fig. 3. Io vs I,
’
for p-channel JFET T = 155°K. V, cycle; 0, 5% duty cycle.
= 45 volts.
x . 100%duty I
too
m,
zoo 250 TEWEFUTURE
300 CK)
350
400
Fig. 1. !o vs Temp. for typical JFETs at 1% duty V,, = 0. x . n-channel; 0, p-channel.
cycle and
104 ,
/
taking care to hold V, and V, constant and to avoid problems with transients. The pulse rate was 100 Hz with a duty cycle of l-5%. This is adequate to keep power levels in the range found in region A for the d.c. measurements. If self heating is the cause of the nonlinearity in region B. this power reduction should remove the nonlinearity. The pulse data (peak values) are shown in Figs. 2 and 3 for comparison with the d.c. data. Clearly k is very near unity. The same results were obtained for both n- and p-channel devices over a wide range of 1, Figures 2 and 3 show data for only two typical devices. For all devices tested region B of the d.c. curves show 0.78 < k < 0.88. For the pulse tests 0.97 < k < 1.03 over the entire curve. For the curve fit to only region B of the pulse data, similar values of k near unity were obtained indicating no significant nonlinearity. Also similar values of k were found for region A of the d.c. data. It is then concluded that the nonlinearities found earlier are due to self heating and that the only important mechanism generating 1, at low temperatures is impact ionization in the channel.
Acknowledgements-The A:van
4
.
,
DRAIN ‘%fWENT Fig. 2. lo v
,
Engineering Depf. University of Florida GainesuiNe, FL 32611, U.S.A.
Electrical
,
(&
for n-channel JFET T = IWK, V, x , 100% duty cycle; 0, 1% duty cycle. I,
authors wish to express thanks to Dr. der Ziel and Dr. A. Sutherland for assistance. L. M. RUCKER E. R. CHENEITE
= 40 volts.
first taken at d.c. Io was controlled by varying V, V, V, The shown Figs. and have nonat currents k 1). part the is B the At currents k is very near unity. This part of the curve is labeled A. The same measurements were made using pulse techniques
Depanment of Electronics Technology H-1521 Budapest Hungay
A. AUBROZY
REFEUFNCES 1. E. P. Fowler, Elecrron. Len. 4(1 I), (19W. 2. R. D. Ryan. Proc. IEEE, 1225 11%9). 3. A. Ambrozy, Periodica Polyrech Elect. Engng 14, 355 (1970).
OSCILLATIONS IN JFETs EXHIBITING CURRENT MULTIPLICATION IN THE CHANNEL (Received 18 July 1977; in revised form
It is the purpose of this a junction field effect multiplication exhibits method for calculating verify the calculation.
correspondence to show that the gate of transistor (JFET) experiencing channel a negative conductance, to present a the conductance and measurements to
1 September
1977)
In 1968 Fowlder[ I] reported an enhanced drain current in FETs and in I%9 Ryan[2] identified the mechanism as impact ionization in the channel. This is commonly referred to as multiplication and is most pronounced in short channel FETs at low temperature. The ionization process generates majority and
598
Notes
minority carriers in equal numbers. The majority carrier flows down the channel to contribute to the enhancement of drain current. The minority carrier is quickly removed from the channel by the gate depletion region. The gate current is then equal to the enhancement of the drain current. This assumes the thermal component of gate current to be negligible, which is reasonable since the multiplication phenomenon is generally studied at much reduced temperature. In our discussion the following polarities are chosen: I, and 1, print into the device and 1s prints out of the device. The minority carrier collected by the gate depletion region causes a negative gate conductance. The value of this conductance can be found as follows. The multiplication factor, M is defined as: M = IdI,.
II)
Fig. I. Circuit
used to measure
Table
R,
10
M
-g,,
Calculated
bmho)
R, (Kohm)
is: 1, = Is - lo
(2a)
= Is - MIS
(2b)
= -I&v
(2c)
- I).
1000 I20
For a small variation
of VGs then: (3)
‘d” = &lb,, where id0 and g,,,, are values of i, and g,,, without Hence the ax. currents id and i, are i, = -i,,(M
(4)
since the a.c. currents are multiplied by the same factors d.c. currents, which gives the input conductance as:
as the
g,, = i&‘
+ I) = -g,,u,,(M
= -g,,(M
- I).
(5)
This negative conductance can become sufficiently large to cause instabilities or oscillations in common amplifier circuits. To check the value of input conductance. the circuit of Fig. 1 was constructed. The FET is placed in liquid nitrogen CT= 77°K) to enhance the multiplication process. The resistor R, was removed and Voo adjusted to produce a small oscillation at the gate as observed on an oscilloscope. The amplitude of the oscillation was less than IOmv. The gate was then connected to the electrometer to measure &. fo was measured and M found from: M = fc&
- ro,
g,, is then found using eqn S(b). The tance of the tank, R,, is: R, = l/g,,
= I/g,.
(6) equivalent
parallel
resis-
M---2N4220A---g, 33.5 I .0089 34.5 1.0091 41.5 1.0110
= 4.64 mmho 40.80 41.92 50.66
DEVICE 1.68
N---2N4220A---g, 19.02 1.0114
= 4.18 mmho 47.87
19.45 22.27 22.98
I.0117 1.0133 1.0136
48.96 55.48 56.94
FH R-5 49.77 50.81 57.40 58.95
(U or F)--g, = 14.0 mmho 1.0039 52.95 1.0039 54.16 9-G 1.0044 61.14 123 1.0045 62.80 102
I.68 1.70 1.71
1000 120 100
DEVICE 13.2 13.2 13.2 13.2
894 102
913 131
I IO
to a peak value of 0.33 V for device N and 0.68 V for device M. Pinch off voltage for device N is 066V and for device M is 1.25 V. The mean value of spr is zero in each case. The data of Table I is a good demonstration that the multiplication mechanism produces a negative input conductance. The value of the conductance can be calculated using eqn (5b) and measured using the circuit of Fig. I. The negative conductance 5,. occurs in a wide frequency range, so that the circuit can oscillate over a wide frequency range when the turned circuit is properly adjusted. At very high frequencies transit time effects give use to a positive conductance in parallel to -g,(M - I), and oscillations cease when the total input conductance becomes positive. An understanding of the negative conductance will be useful in avoiding problems in the use of JFETs. In addition this is an indication of a limitation in the design of new short-channel JFETs since a shorter channel length, which has several desirable effects, leads to an increase in multiplication and greater possibility of stability difficulties.
(7)
Various values of R, are then used in the circuit and the procedure is repeated. At the threshold of oscillation g,, is equal to R, in parallel with R, which may be found by: R, = t/(g, - g,.).
DEVICE 3.81 3.82 3.81
1000 120 100
multiplication.
- I).
id = i&f,;
I
47
(Kohm) (ma) baa) The gate current
g,. of the FET.
(8)
This may be compared to the known value of R, to verify the value of g,. The data and results are shown in Table I for three n-channel JFETs. Two are 2N4220As and one was manufactured at the University of Florida. It should be noted that although measurements and results in Table I are for much reduced temperature, the same oscillation was observed in n-channel devices at room temperature. The amplitude of va, grew rapidly with slight increases of voo
Acknowledgemenf-The authors wish to thank Dr. A. Sutherland for helpful advice and suggestions. Necrrical Engineering Dept. C’niuersiry of Minnesota Minneapolis. MN 55455, U.S.A. Necrrical Engineering Depf. University of Florida Gainesville. FL 32611. U.S.A.
A. VAN DER ZlEL
L. M. RUCKER
REFERENCES I. E. P. Fowler, Electronics Lerr. 4(11), 216 (Nov. 19613). 2. R. D. Ryan, Proc. IEEE, 57(6), 1225-1226 (June 1%9).