Oxide field enhancement corrected time dependent dielectric breakdown of polyoxides

Oxide field enhancement corrected time dependent dielectric breakdown of polyoxides

Microelectronics Journal Microelectronics Journal 31 (2000) 663±666 www.elsevier.com/locate/mejo Oxide ®eld enhancement corrected time dependent die...

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Microelectronics Journal Microelectronics Journal 31 (2000) 663±666

www.elsevier.com/locate/mejo

Oxide ®eld enhancement corrected time dependent dielectric breakdown of polyoxides V.K. Gueorguiev a,*, Tz.E. Ivanov a, C.A. Dimitriadis b, S.K. Andreev a, L.I. Popova a a

Institute of Solid State Physics, Bulgarian Academy of Sciences, 72 Tzarigradsko Chaussee blvd., 1784 So®a, Bulgaria b Department of Physics, University of Thessaloniki, 54006 Thessaloniki, Greece Accepted 23 March 2000

Abstract Time-to-breakdown (tbd) of polysilicon/polyoxide/polysilicon structures is investigated on small and large area capacitors. The ln…tbd † versus 1=Eox projection lines are corrected by using an average oxide ®eld enhancement factor for the interface polysilicon/thermally grown polyoxide. A ®eld acceleration factor G < 320 MV=cm in the time-to-breakdown projection line is obtained. It is shown that the fast prediction of time-to-breakdown can be achieved with short stress time measurements in structures of different area. q 2000 Elsevier Science Ltd. All rights reserved. Keywords: Silicon dioxide±polysilicon interface; Thin ®lms; Reliability; Time-to-breakdown

1. Introduction Recently, several researchers have investigated the conductivity behaviour of thermally grown oxides on polycrystalline silicon (polyoxides) [1±3]. Long-term stability, time-to-breakdown and stress-induced instabilities have been also investigated [4±7]. These investigations were performed aiming to realise stable and reliable microelectronic devices, such as nonvolatile ¯oating gate electrically erasable memories, large-area integrated circuits with polysilicon thin-®lm transistors, etc. It is well established that the polyoxides conduct higher currents at much lower applied voltages than oxides grown on monocrystalline silicon. This effect is because of the oxide ®eld enhancement at the textured interface polysilicon±polyoxide. A satisfactory quantitative model for the conduction of polyoxides and for the reduction of ®eld enhancement as a result of electron capture in neutral traps into the polyoxide was published in Ref. [1]. Modelling of the conduction of hydrogen polyoxides, as-grown and hydrogenated by ion implantation was presented in Ref. [3]. In the reliability modelling of oxides on monocrystalline silicon it was mentioned that defects as surface asperities

* Corresponding author. Tel.: 1 359-2-779-217, fax: 1 359-2-9753632. E-mail address: [email protected] (V.K. Gueorguiev).

can in¯uence the interpretation of the data for gate oxide reliability [8]. The mean effect of these oxide defects was successfully modelled using the concept of ªeffective oxide thinningº for oxides grown on monocrystalline silicon. In the recently published investigations on the time-to-breakdown of polyoxides, the effect of the polyoxide ®eld enhancement was not taken into account [4±6]. They were obtained up to a twice higher ®eld acceleration factor in the time-to-breakdown than that for the oxides grown on monocrystalline silicon. This was not explained in terms of the existing theory [9,10]. Moreover, there is no data about the preexponential characteristics time t 0, which is of the order of 10 211 s for oxides on monocrystalline silicon. In this paper we present the experimental data for the time-to-breakdown of as-grown polyoxides which are obtained with constant voltage stress. In the time-to-breakdown calculations, the average polyoxide ®eld enhancement factor is included. 2. Experiment The test capacitors used for the measurements were processed as bottom n 1 polysilicon, thermally grown silicon dioxide and LPCVD deposited n 1 polysilicon. The bottom polysilicon was deposited on oxidised silicon wafers. To minimize the polysilicon depletion and the resistivity effect on the polyoxide ®eld reduction and oxide thickness measurements, a higher dose of ion implantation for the

0026-2692/00/$ - see front matter q 2000 Elsevier Science Ltd. All rights reserved. PII: S 0026-269 2(00)00043-4

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heim (FN) tunnelling takes place in the oxide. When the electrons interact with the oxide traps or when they reach the positive biased electrode, the dissipated electron energy can generate positive or negative charges [12,13]. The local oxide regions where such charges are accumulated are regions of increased lattice energy and the local oxide breakdown can be initiated. Based on FN tunnelling at a higher constant voltage, the reliability models predict an inverse dependence of the time-to-breakdown tbd on the applied electric ®eld across the oxide Eox, i.e.   G ; …1† tbd ˆ t0 exp Eox Fig. 1. Plots of ln…tbd † versus 1/Eox of the 1 £ unit area and 40 £ unit area polyoxide capacitors.

n 1 polysilicon electrodes was used. With the capacitance± voltage and optical techniques applied on the oxidised polysilicon deposited on monocrystalline silicon, a polyoxide thickness of 45 nm was measured. Capacitors with high boron doped bottom polysilicon have also been used. Details of the fabrication processes were published elsewhere [11]. The measurements were performed on two types of rectangular structures with area 0.0025 mm 2 (1 £ unit area) and 0.1 mm 2 (40 £ unit area). The 40 £ unit area structures were designed as a comb with a total edge length of about 0.6 cm. Although for each capacitor type, constant voltages stress at four positive voltages on the polysilicon deposited on top were applied, only the three high ®eld data points were used to determine the projection line. More than 40 capacitors were stressed at each stress voltage. 3. Experimental results and discussion Usually, the prediction of silicon dioxide reliability under low operating ®elds is based on high constant or ramp voltage stress. At higher applied voltages, Fowler±Nord-

Fig. 2. I±t charcteristics at different stress voltages of the 1 £ unit area polyoxide capacitor.

where G and t 0 are the slope and intercept of the ln…tbd † versus 1=Eox plot, respectively. For oxide ®lms grown on monocrystalline silicon, the experimental values of these parameters obtained at room temperature are G < 350 MV=cm and t0 < 1 £ 10211 s [9,10]. However, the quantity t 0 may vary from about 10 29 at low oxide ®elds to 10 213 at high oxide ®elds [9]. Defect-induced breakdown has been modelled in the 1/Eox ®eld dependence for oxide breakdown by using a correction term Dtox in the oxide thickness [8]. The concept of Dtox was used to model physically thin spots in the oxide ®lm, asperities at the oxide/ silicon interface (resulting in a higher oxide ®eld) and localised areas having a modi®ed chemical composition which may reduce the barrier height at the SiO2/Si interface (resulting in a lower B) or increase the charge trapping rate. For oxide grown on polycrystalline silicon, values of the parameter G varying from about 475 up to 679 MV/cm have been reported [4±6]. These values of G are too high and it is dif®cult to be explained on a physical basis. For our small and large area polyoxides, the experimental data of ln…tbd † versus 1=Eox are shown in Fig. 1. The lines of Fig. 1 correspond to the following relationships:   132:752 ; …2† tbd ˆ 3:92 £ 10212 exp Eox for the 1 £ unit area structure and   127:424 ; tbd ˆ 9:629 £ 10213 exp Eox

…3†

for the 40 £ unit area structure. Despite the fact that a reasonable value for the quantity t0 < 10212 s has been obtained for both structures, the calculated value of the ®eld acceleration factor G < 130 MV=cm is quite low in comparison with the theoretically predicted value of 320 MV/cm for the interface silicon/silicon dioxide [8,9]. For interpretation of the obtained low value of G, we will use the concept of the oxide ®eld enhancement caused by asperities at the interface between polysilicon/polyoxide. The most comprehensive model for current±time (I±t) and current±voltage (I±V) characteristics of polyoxides during the constant voltage or ramp voltage stress was published in Ref. [1]. This model was applied for oxide traps characterization of the as-grown and hydrogenated

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current conduction. This effect was modelled by considering a suitable area distribution function [1]. However, at low applied voltages, it is not accurate to use the term, ªmean enhancement factorº which is extended over the whole capacitor area. For applied voltage stress near the breakdown, nearly the total area of the capacitor participates in the current conduction. In this case, it is more realistic to use the average oxide ®eld enhancement factor m av which can be calculated from the FN equation:   2Ec 2 2 ; …4† J ˆ CEox mav exp …mav Eox † Fig. 3. Variation of the average oxide ®eld enhancement m factor with stress time at different applied stress voltages of the 1 £ unit area polyoxide capacitor.

where C ˆ 1:44 £ 1026 A=V2 and Ec ˆ 2:532 £ 108 V=cm [1]. Taking into account the ®led enhancement factor m av, the time-to-breakdown can be calculated using the relationship: tbd ˆ t0 exp‰G=…mav Eox †Š:

polyoxides [3]. Despite that the model describes the current±voltage characteristics of ªvirginº structures very well, it is dif®cult to obtain an average (or mean) oxide ®eld enhancement factor m av. Also, the computational sequence is quite complicated and the product of the electron traps characteristics as capture cross section and density of traps should be used. Because, the practically used time-to-breakdown is higher than a few hundred seconds when the stressed structures cannot be considered as ªvirginº, we will use a more simple method to derive an average oxide ®eld enhancement factor for the investigated polyoxides. Typical I±t characteristics for a 1 £ unit area structure are shown in Fig. 2 with the applied constant voltage increasing from 8 to 16 V. During the application of the lower voltage stress, only a certain percent of the total area of the capacitor exhibiting the higher ®eld acceleration factor takes place in the current conduction. Over this capacitor area, electrons trapped in neutral oxide traps partially compensate the initial ®eld in the oxide. By increasing the applied voltage, more and more of the capacitor area participates in the

…5†

The calculated values of m av as a function of stress time, derived from the data in Fig. 2, are shown in Fig. 3. First, the factor m av decreases very fast after the application of constant voltage, and then, when the stress proceeds further m av remains almost constant. For stress voltages higher than 16 V, the obtained values of mav , 3 are compatible with the recently published typical value of 3 for polyoxides [1,14]. Despite the fact that in Eq. (5) m av is included over the total area of the capacitors, it has been found that it satis®es the time-to-breakdown of polyoxides quite well. The ln…tbd † versus 1=Eox plots for typical 1 £ unit and 40 £ unit area capacitors with mav calculated at the higher stress voltages for time 100 and 250 s are shown in Figs. 4 and 5, respectively. The constants t 0 and G determined from Eq. (5) are listed in Table 1. It can be seen that the obtained values of t0 < 10212 s and G < 335 MV=cm are in good agreement with the theoretical values predicted by the 1/ Eox breakdown model [9,10]. Fig. 6 summarizes the time-to-breakdown data of Figs. 4 and 5, derived for stress time 100 and 250 s of 1 £ unit area and 40 £ unit area capacitor structures. As it is evident by this ®gure, for each stress time, the two data sets of ln…tbd † for small and large area structures are practically aligned. The extracted value of G < 320 MV=cm is in excellent agreement with the theory. This last feature infers the consistency of our approach to determine the time to breakdown of polyoxides. In addition, an important practical implication of Fig. 6 is that, instead of performing stress for long time to obtain more than 3 experimental points in the ln…tbd † versus 1=Eox plot, it is enough to perform measurements at a short stress time on structures of different area on the same wafer and at different stress voltages. 4. Conclusions

Fig. 4. Plots of ln…tbd † versus 1/Eox with mav ˆ 2:58 (for stress time 100 s) and mav ˆ 2:58 (for stress time 250 s) of the 1 £ unit area polyoxide capacitor.

Oxide ®eld enhancement factor caused by asperities at the polysilicon/polyoxide interface is demonstrated to affect the

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Fig. 5. Plots of ln…tbd † versus 1/Eox with mav ˆ 2:73 (for stress time 100 s) and mav ˆ 2:69 (for stress time 250 s) of the 40 £ unit area polyoxide capacitor.

Fig. 6. Plots of ln…tbd † versus 1/Eox of the 1 £ unit area and 40 £ unit area polyoxide capacitors for stress time 100 and 250 s.

Table 1 Parameters t 0 and G determined from ln…tbd † versus 1/Eox plots of Figs. 4 and 5 of the 1 £ unit area and 40 £ unit area capacitor structures, respectively. The parameters t 0 and G obtained by the combined data of the 1 £ unit area and 40 £ unit area capacitor structures (6 point curve) are also shown 1 £ unit area

mav t 0 (s) G (MV/cm)

2.53 3.99 £ 10 212 335.708

40 £ unit area 2.48 3.9 £ 10 213 329.119

2.73 9.64 £ 10 213 347.852

lifetime projection for polysilicon/polyoxide/polysilicon structures. Quantitative description of the average ®eld oxide enhancement factor m av can be established through the measurements of I±t oxide characteristics at high stress voltages. Correction of ln…tbd † versus 1=Eox curves results in the physically predicted values of the ®eld acceleration factor G < 320 MV=cm: Short stress time investigations of the time-to-breakdown can be performed with simultaneous measurements on small and large area capacitors. Acknowledgements Financial support from the Scienti®c Commission of the Bulgarian National Science Fund (contract P 708/97) and from the Greek General Secretariat of Science and Technology is gratefully acknowledged. References [1] G. Groeseneken, H.E. Maes, A quantitative model for the conduction in oxides thermally grown from polycrystalline silicon, IEEE Trans. Electron Devices ED-33 (1986) 1028±1041. [2] T.F. Lei, J.Y. Cheng, S.Y. Shiau, T.S. Chao, C.S. Lai, Improvement of polysilicon oxide by growing on polished polysilicon ®lm, IEEE Electron Device Lett. ED-18 (1997) 270±271. [3] V.K. Gueorguiev, Tz.E. Ivanov, C.A. Dimitriadis, L.I. Popova, S.K. Andreev, Electron trapping probabilities in hydrogen ion implanted silicon dioxide ®lms thermally grown on polycrystalline silicon, Microelectron. J. 31 (3) (2000) 207±211.

6 point curve 2.69 9.7 £ 10 213 342.666

mav (100 s) 2 £ 10 211 318.2

mav (250 s) 4.14 £ 10 212 328.5

[4] S.J. Wang, I.C. Chen, H.L. Tigelaar, TDDB on poly-gate single doping type capacitors, in: IEEE International Reliability Physics Symposium (IRPS'92), 1992, pp. 54±57. [5] A. Martin, P. O'Sullivan, A. Mathewson, A practical lifetime prediction method for inter-poly oxides, Electron Technol. 27 (1994) 55± 64. [6] A. Martin, P. O'Sullivan, A. Mathewson, B. Mason, C. Beech, Evaluation of the lifetime and failure probability for inter-poly oxides from RVS measurements, Microelectron. J. 25 (1994) 553±557. [7] A. Martin, P. O'Sullivan, A. Mathewson, Study of unipolar pulsed ramp and combined ramps/constant voltage stress on gate oxides, Microelectron. Reliability 37 (1997) 1045±1051. [8] J.C. Lee, I.-C. Chen, C. Hu, Modeling and characterization of gate oxide reliability, IEEE Trans. Electron Devices ED-35 (1988) 2268± 2277. [9] R.P. Vollertsen, Statistical modeling of time dependent oxide breakdown distributions, Microelectron. Reliability 33 (1993) 1665±1677. [10] R. Moazzami, C. Hu, Projecting gate oxide reliability and optimizing reliability screens, IEEE Trans. Electron Devices ED-37 (1990) 1643±1650. [11] C.T. Angelis, C.A. Dimitriadis, I. Samaras, J. Brini, G. Kamarinos, V.K. Gueorguiev, Tz.E. Ivanov, Study of leakage current in n-channel and p-channel polycrystalline silicon thin-®lm transistors by conduction and low frequency noise measurements, J. Appl. Phys. 15 (1997) 4095±4101. [12] C.T. Sah, Models and experiments on degradation of oxidized silicon, Solid State Electron. 33 (1990) 147±167. [13] K. Kobayashi, A. Teramoto, H. Miyoshi, Origin of positive charge generated in thin SiO2 ®lms during high-®eld electrical stress, IEEE Trans. Electron Devices ED-46 (1999) 947±952. [14] P.A. Heiman, S.P. Murarka, T.T. Sheng, Electrical conduction and breakdown in oxides of polycrystalline silicon and their correlation with interface structure, J. Appl. Phys. 53 (1982) 6240±6245.