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Panel Discussion
Panel Discussion
Be r g h a m mer: Consider that a complete computing centre will not become drastically smaller, even though it has been microminiaturized. Since microminiaturization, in general does not affect all the peripheral equipsystem.. ment, which takes a considerable volume portion of the complete system micron1iniaturized integrated circuit also occupies only Analogously the microminiaturized a small fraction of the volume of a total package. So, what is the technical econon1ical significance of microminiaturization? and economical D a vis: You are all well aware that there is both a technical and economic motivation for integrated circuits. Although the point has been well made.that the electronics contained in digital equipment represents probmade,that ably no more than a third of the cost of that equipment, it is this one-third technologies.. which is the most easily reduced through the use of improved technologies
only.. More reThe first integrated circuits were in the form of hybrids only n10nolithic cently, a great deal of effort has been directed towards silicon monolithic in1provement in this technology has been rather remarkcircuits, and the improvement years.. Thus Thus,, it might be appropriate to spend a able during the last few years lTIOments discussing the current status of these two technologies. few moments technology,, There has been a great deal of emotional discussion over which technology superior.. Let me begin by stating that it is clear monolithic or hybrid, is superior with us for the forethat both monolithic and hybrid circuits are going to be withusfortheforefuture.. And, neither technology will really dominate the circuit seeable future field for a number of years. However, there will be a gradual tendency to employ monolithic circuits in digital applications and hybrids in analogue applications. Although both technologies offer a reduction in cost over the generation of circuits that used discrete components, monolithic circuits lDng run, produce the lowest net circuit cost. Thus Thus,, there will will, in the long be an increased tendency to use digital circuits for functions currently percircuits. formed by analogue circuits, The current relative cost of digital circuits produced by monolithic and hybrid technologies is reflected, I believe, in Figure 11.. The circuit being considered here is a simple "and" gate. The cost figures have been normalized such that the silicon chip employed, which for the monolithic assigned one unit of cost. One technology contains the entire circuit, is aSSigned
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1 GATE/PACKAGE
TECHNOLOGY
MONOLITHIC
HYBRID
3 GATES/PACKAGE
MONOLITHIC
HYBRID
"CHIP COST!! COST"
~
1
3
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PACKAGING COST
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15 - 20
6
24
7
16 - 21
9
9
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TOTAL COST / CKT
Figure 1. Cost Comparison of Monolithic and Hybrid Circuits.
is then confronted with the appalling situation that current monolithic packaging techniques add 15 to 20 units of cost. Thus, the cost of the monolithic circuit today is mostly the cost of the package. The hybrid technology designer, in general, recognized early that the key to low circuit cost was in the package and thus applied himself to reducing this cost. One significant result was glass-passivated silicon semifor hermetic containers. The conductor devices, which eliminated the need needfor results are shown in Figure 1. The hybrid designer must employ three times the amount of silicon, since each chip contains only one or, at the most, a few devices. However, the packaging costs of the hybrid circuit, and this includes the cost of packaging the semiconductors, is only six units. The result is a lower total cost for the hybrid circuit than for the monolithic circuit. To reduce the cost of the lllonolithic monolithic chip contained in a hermetic seal package, one can obviously amortize the cost of the package over many circuits; this is generally what is being done in the industry today. The second column of Figure 1 illustrates this case. The monolithic chip has doubled in cost but now contains three gates. Its packaging cost, due to the increased number of leads, has also increased. Significantly, however, the cost per nUlllber circuit has been greatly reduced. Clearly, as the cost of monolithic chip packaging becomes less, monolithic circuit costs are going to become less than those of hybrids. The key then to inexpensive circuits is inexpensive device packaging. Figure 10. of my contribution (see paper 4.8) shows a deVices, including monolithic circuits, that have been variety of silicon chip devices, glass encapsulated to protect them from the atmosphere. Before continuing into the future cost picture, I would like to pause a moment and compare cOlllpare the performances of these various technologies. There is little doubt that at this time, hybrid circuits have higher performance than lllonolithics. 4.8), monolithics. Figure 11 of my paper (see 4. 8), for exalllple, example, shows a hybrid lllodule module containing four circuit gates that function in less than 1 nano-
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second. Such performance, although readily obtainable with hybrid technology, is beyond the current state of monolithic art. One of the more interesting questions the panel may wish to discuss is when this will cease Dr.. Kohn just spoke of the isolation problem and how hyto be the case. Dr brid circuits tend to be somewhat superior due to their ability to provide very good isolation capacitance. Also, interestingly enough, because of the packages currently used for monolithics, the effective circuit density of hybrids is equal to the best monolithics on the market today. Hybrid circuits also offer the advantage of more precise passive components. The future for monolithics, however, is very bright. There is certainly no reason why the same technologies that I have described for hybrids cannot be used for monolithics. In Figure 2, you see a chip containing
Figure 2. A Monolithic and a Single-Transistor Chip.
25 DTL circu~ts. circu~ts. It is compared with a chip 25 thousandth of an inch on a side containing one transistor. The monolithic chip has 24 ball contacts and three levels of interconnections. interconnections . Figure 3 shows these monolithic chips joined to a module approximately 1/2 inch square. This semiconductor chip is soldered to the lands of the module, eliminatingthereliminating thermo-compression bonding. The module also contains some "personality lands," that is, electrode patterns that are screened on the module to determine the logical statements represented by the module. There are a total of 54 circuits on this module.
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Figure 3.
J.Berghammer J. Berghammer
Monolithic Chips Mounted on a Half - Inch Square Ceramic Substrate
more precise passive components will be provided through a In addition, ll10re cOll1bination combination of hybrid and monolithic techniques, in which thin-film COll1components will be deposited on the silicon surface. An example is shown in Figure 4.
Figure 4. Monolithic Chip with Thin- Film Components
Also, in the future, very high circuit density will be achieved on ll1onomonolithic circuits. Figure 5 is a hundred-bit shift register. All the art work required to produce this shift register, containing over 1, 500 components, \vas was produced on an autoll1atic automatic art \vork work generating n1achine, machine, which is shown
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Figure 5. Large Array Produced Through Automatic Artwork Generating Equipment
deternline which in Figure 6. The ability to measure a monolithic wafer to determine importantfor units are operating and then to interconnect good units is very important for nlonolithic circuits. Such automatic artwork generatthe future of low cost monolithic ing equipment is the key to the complex problem of interconnecting the opcircuits.. erating circuits
Figure 6. Automatic Artwork Generating Equipment
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In conclusion, the future will offer many advances in the state of monolithic and hybrid art. Improvements Improvem~nts in packaging will be among the most significant of these technology advances. Be r g h a m mer: Thank you, Dr. Davis, I think you have given us an interesting view of the present status, and you have pointed out that the cost motive was one of the more essential ones and I wonder if the other panel-members share your view. Perhaps there are some other reasons, besides cost, which are of significance to lead to microminiaturization? S and San d bank: Thank you. Well, these gentlemen here have made the difficult decision of coming to see us rather than sample the night life of Munich, so I think I'd like to be honest and give my own personal opinion, but I hope you switch off the tape recorder first. Really what is the reason for microminiaturization, or going into microelectronics? With the exception of a very few users, the people who wanted to send rockets into space or put pacemakers and receivers down people's stomachs, most users don't want the small size. The systems manufacturers were not pressing the component manufacturers to make things smaller, or to make things in monolithic form or so on, they didn't care how it was made. They just wanted the function in a cheap and reliable form. The pressure, let's face it, has come from us, from the component manufacturers.
Why have the component manufacturers given this pressure? Not because they themselves want to do this, but mainly because they are afraid that somebody else will do it first. They are afraid that the next man will make transitors, resistors, reSistors, possibly capacitors, perhaps even inductors more cheaply than they can make components at the moment. Therefore they Circuits, sampling the market, and trying to perare going into integrated circuits, suade the user to buy their integrated circuits, so that, if and when they can make them cheaper than the present components, people will be using theirs, and not their competitor's. But let me conclude, Mr. Chairman, by saying that I believe that they are absolutely right. I believe that this will Situation, but it is not the situation yet, I don't think eventually be the situation, anybody in America or Europe is making a fortune out of monolithic circuits etc. it is mainly an inyestment in the future which must be made by people who want to be sure that they remain in the business. Ra de d e m a k e r s : Three arguments have always played a role in the trend to miniaturize electronic circuitry, which trend has led nowadays to the various kinds of integrated circuits. These arguments were reliability, volume and price, and in the beginning it seemed for some time as if the order of importance of the arguments
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was the same as that in which I mentioned them here. However, with the development of a normal market for integrated circuits, the price argument came forward very strongly, while on the other hand the volume argument lost in importance, since we have already reached the situation where the circuits themselves can be disappearingly small compared with the encapsulations and the means for interconnection. In most cases therefore, the choice between hybrid and semiconductor integrated circuits will be determined in the first place by the price-perfornlance price-performance argument, with reliability and volume in the second and third places. B Beerg r g h a m mer: We all think that the technology of integrated circuits has made considerable progress with respect to microminiaturization. Its products with 10 or 14 leads sticking out of a more or less empty can, have to be connected electrically and mechanically, to make electronic equipment. I wonder whether the possibilities for microminiaturization, as offered by integrated circuit technology, are already sufficiently exploited by the potential users, the equipment designers. Or in other words: can present-day interconnection techniques match integrated circuit technology with respect to microminiaturization? San db a nk: Well I was hoping you'd ask this question, because I have Sandbank: been sitting here sketching an answer to it. But first it is probably worth while thinking a moment why we are now all faced with the interconnection problem. Mter After all, it has hit us quite suddenly, and it isn't just because we have a component which has a lot of leads coming out of it. The industry has been quite used to handling things like small radio valves, which have had 8 to 10 leads. I think the real reason why we are faced problem is that we have this unit which has many with this interconnection problenl leads conling coming out of it, but has to be intimately connected with anything up to a dozen units, which are spread about the system. This is very different from the transistor or the radio valve, which, although it may have 8 or 10 leads coming fronl from it, only has an input, an output, HT and heaters which are connected to the immediately neighbouring circuitry. So there is this problem, that we have both the complex unit, which has a complex relat.ionship relationship with the rest of the system, and the fact that it is small. At -the the same time it still has to be handled by human beings, who throughout this period of microminiaturisation, have remained the same size. Small size in some cases is a disadvantage. It is the economic pressures which Dr. Davis has just mentioned, which force us to small size on the monolithic chip so that we can accommodate more components per unit area. Sooner or later we have to try to regain some of this size, and I put it to
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you that some of the most successful interconnection systems which are going to come along in the future are those which enable us to regain some of the ease of handling which we have lost for economic reasons in the active and passive components themselves. One of the techniques that we have investigated consists of a woven n1atmatrix of interconnections, (see Figs. 7 and 8). It comprises essentially a
Figure 7. Woven matrix with thin-film circuits
flexible epoxy glass strip with a conductor band on each, and these are woven like a piece of cloth so that the conductor always appears on top. This gives the equivalent of a double sided matrix, but the access is always from one face. The cross-points are obtained by laying on a connecting disc and breaks are obtained by cutting the conductor. This is a very convenient way of inter:connecting intesconnecting integrated circuits and is also quite suitable for automation. A computer can programme and control the places where the discs are put or the breaks are made. It is not intended to be a means of interconnecting a lot of integrated circuits closely together and illustrates the point that by putting the integrated circuits around the periphery, ease of handling is obtained at the expense of packing density.
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_ . .iliA) -0
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Fig;ure 8. Inter Inter-connection Figure -connection layout card: this card, which is in effect the logic diagram, can be used as a template for locating the connecting pellets on the woven matrix
Beerg r g h a m mer: I will turn the discussion to a problem that is related B to the interconnection problem, and it concerns standardization of the external dimensions, lead dimensions, as well as electrical functions. It would probably be beneficial to both the producer and the user if such standardization, at least of external dimensions, could be carried out. What is the current situation with regard to standardization in the United States? And an additional question that also belongs to this subject: which is the most useful container from the standpoint of the user: TO-5-can, flat-pack, dual-in-line, epoxy-can, etc.?
D a vis: The current situation in regard to packaging standards in the U. S. is chaotic. In the first place, there has been a great deal of individuality and invention shown on the part of users and manufacturers. As a result, we have few standard packages at this time, and neither the users nor the manufacturers have been happy with the defacto standards of the flat-pack or TO-5 packages. There has been a desire on the part of the users to find a package that is easier to handle and less expensive. In this regard, there has been con-
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siderable discussion on the relative merits of the in-line or planar package und a package containing pins. Also, there is a general trend toward increasing the number of terminals or leads on the package in order to reduce the effective circuit cost. Recently, a number of manufacturers in the U. S. have introduced packages with more than fourteen leads. Adding confusion to the packaging situation is the possibility of drastically reducing packaging costs by using non-hermetic sealing or epoxy packages. There are a number of committees and national organizations working on standard packages. The increasing complexity of monolithic circuits, however, only tends to heighten the standardization problem. Be r g h a m mer: Would you perhaps also make a remark on the optimum container to be used. D a vis: There is certainly no unique answer. Each user must consider such questions as: How expensive a throw-away package is he willing to use? How complex does he wish his logic functions to be? That is, does he want unit logic, where all the inputs and outputs of the circuits are brought to terminals, or highly functional blocks, where his testing difficulties will be greatly increased. Because of the diversity of user responses, manufacturers will probably produce packages with large numbers of leads, perhaps greater than 30, for those users who wish to employ unit logic and less expensive packages with fewer number of leads for those who wish to have either a few circuits or highly complex logical functions. Ra d e m a k e r s : I would like to start one step back in considering the problem. If we want to fill a certain space with electronics and make all the necessary interconnections, the normal way is to start filling planes with circuits and interconnections, and then stack these planes and interconnect them in one or more of the end faces of the space to be filled. I was interested to see that Dr. Kohn in his fundamental considerations on the lin1its assume that limits of packing denity used the same approach. If we aSSUffie n10n1ent this is the only practical way, then the circuit package at the moment n1ust syst~m. must be adapted to this systt;m. Practice then leads to the following requirements: a) The height of the mounted package must be such that the stacking of the planes can be as dense as allowed by the printed-circuit-board connectors. b) The package must make an economic use of the p-c-board area. c) Mounting, inspection and replacement must be easy. n1Y opinion that these demands will be met best by a rather flat packIt is my
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age with fixed pins in a standardized grid protruding from one of the large faces of the package. Ko h n: I think there is always a compromise or a trade-off between perKohn: formance and cost, and it can never be overemphasized, also in this respect, what has been said by Dr. Davis about the importance of packaging. For interconnections, better methods, such as light beam coupling, might be employed in the future. This could be a good discussion question for anyone wanting to comment on this. I myself feel, that the electric connection is a very good one and probably the best one. Va n San ten: I do agree with Dr. Kohn that the electrical connection Van is the best one. I think that you can use optical connections when one has no other possibility. But as long as the optical connection means that you lose in speed, and that you also lose in price, then I think that the electrical connection is the best one. Be r g h a m mer: Some remarks were made initially on hybrid circuits. In order to get a balanced view, I would like to ask the following question: What is the future development of monolithic circuits? Since reduction of cost, and increased performance are the prime reasons for further development, we ask: Is it likely that we will continue perhaps to integrate further, and if we integrate integrated circuits, or a number oflogicfunctions, of logic functions, (see for example the supplementary remarks by Seelbach in paper 6.3), I optimum number of "components" to be put on would like to know what is the optin1un1 a silicon chip, is it 50, 100, 1,000 or 10,000? Sandbank: San d ban k: Well, I think this is a question you shouldn't really ask, Mr. Chairman, because you talk in terms of components, and in myopinion it is a fallacy when thinking of integrated circuits to talk in terms of components rather than functions. In the paper that Mr. Horsley and I presented, we describe a cellular substrate, where we have the concept that each component function should consist of many cells, and that infact it is a sort of basic concept of the working of the method, that you don't use just one c.ell c€ll per component function. The analogy that we draw is with the reproduction of a colour picture on a shadow mask CRT, where the screen consists of cells, each having a red, green and blue dot. The whole system depends upon the basic concept, that you never try to reproduce a piece of information with only one cell. Now this is the concept that we have been looking for in the cellular substrate, but this isn't isn I t the ultimate. I think that in the future things will go even further than this. Many designers have been feeling instinctively that it is wrong to think of integratcon1ponents put together, and that ed circuits as a reproduction reprodUction of normal components
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we should somehow try and sidestep this completely. Now, in our cellular substrate we haven't done this yet, because we are still using many cells to produce a transistor function, a diode function, a resistor function, so really we haven't completely got away from the "component" concept. But very recently there has been work on the basic physics of bulk effects in solids, which is beginning to point the way to the direct realization of electronic functions without involving intermediate components. There isn't time, Mr. Chairman, to go into the various points here, but I'd like to give one example, namely the Piezo-electric amplifier. This consists of a piece of bulk semiconduction crystal, such as cadmium sulphide, with transducers at the input and output. A drift field across it causes the acoustic driftfield phonons in the semiconducting cadmium sulphide to interact with the electrons giving growing wave amplification as the electrons drift through the crystal. In practice, one can get as much as 100 dB per cm amplification completeampliat 100 megahertz within the crystal which comprises the complete amplifier. There are many other sorts of bulk effects in the solid which are coming along where I think we will not have to think in terms of components. So I think your question is not so much directed to the distant future, but the more immediate future. D a vis: A better understanding of the question of how many circuits one is likely to place in a monolithic chip can be developed from a very simple model. Consider the top surface of a silicon wafer into which a grid of monolithic circuits has been constructed. Each cell of this grid is indentical and, for the purposes of this model, contains a logic gate. Now the problem is how do we determine the best level of complexity for a single chip. Let us consider processing this wafer in three different ways after the ·circuit circuit grid has been produced. Each circuit in each of the cells of the grid, although complete, is not interconnected with its neighbours. One method of processing the wafer would be simply to cut up the wafer into individual or discrete chips, each containing one circuit. A second way would be to cut the wafer into chips containing four, six, eight, ten, or some other number of circuits. We would, of course, interconnect these circuits before cutting up the wafer. The third method would be to connect a large number of working circuits on the wafer proper. Let us now consider the economics of these various approaches. The price of the chip increases as the size of the chip and, thus, the number of cells on it rises, for two reasons. First, the chip contains more materials, and obviously a greater percentage of the total manufacturing investment is represented by the wafer. Secondly, and more importantly, the yield of the finished chip has been reduced, since it is now required that each individual cell contained within this chip in this non-redundant system be oper-
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able. (That is, for the complete chip to be acceptable, each individual unit cell must also be acceptable.) Note, however, that the cost also rises for very small chips containing very few cells because there is a minimum chip size that can be physically handled. Presently this chip size is larger than the amount of silicon required to produce a single circuit. currenttechnology, Thus, with current technology, a curve of number of circuits per chip (that is, number of generated cells per chip) versus cost shows a typical minimum somewhere between two and four circuits. The cost curve then generally rises slightly through seven to ten circuits, after which it begins to increase very rapidly. Unlike the cost per unit circuit at the silicon chip level, the cost 'per unit circuit of the package tends to descrease monotonically with increasing number of circuits within the package. When the silicon chip cost and the packaging cost are added together, the resulting curve has a minimum for packages containing three to fifteen circuits. In the future, the increasing yield of semiconductors, together with the decreasing size of the unit cells, will change the cost-versus-number-of-circuits curves. The increased yields will broaden the base, and the decreased unit cell size will tend to lower costs over a wider range flatten out the edges of these curves, giving lowercosts of circuit packages. Returning to the wafer, one may plot a cost curve for interconnection schemes where the individual circuits are tested on the wafer and the good circuits are interconnected in large arrays on the wafer before packaging. One must build some redundancy in circuit count on the wafers for such an approach. The cost curve for such "large scale integration" tends to offer low cost for wide ranges of circuit counts. semiconductor chip must be measurBecause every single circuit on the semiconduc.tor ed and the data from these measurements must pass through a computer, Circuits, this computer time rewhich in turn interwires the operating circuits, presents a major portion of the circuit cost. The feasibility of this approach will be determined by the cost of this measurement and the computer generated art work step. In the future, a bootstrapping situation may well take place, where the use of monolithic circuits will reduce the cost of computers, thus, making possible a further reduction in the cost of the circuits.
Be r g h a m mer: In the computer-field it has been customary to talk about generations of computers. Tubes, transistors and integrated circuits characterise the first, second and third generation of computers. It is fair to assume that a third generation will also have descendants.
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What will be the replacement for the conventional present-day integrated circuits? San d ban k: I think I've already given the answer really, Mr. ChairSandbank: man, in the sense that naturally I think our cellular substrate will be widely used and therefore this will be the next generation. The generation after this I think will be the bulk effect in the solid state which will not have intermediate components but will use the properties of the solid to achieve the function. D a vis: Yes, I disagree. Nothing is more precious on a silicon monolithic wafer than its area, and thus every effort is made to reduce the area employed per circuit to a bare minimum, especially for products that are to be produced in quantities. Thus, any approach such as the cellular substrate presented by Mr. Sandbank will prove to be more expensive than the unique masking processes, for two reasons: 1. The increase in area required to generate the circuit because of the compromises that are required in generating an array of identical cells that would be useful and in making more than one circuit configuration. 2. The interconnection problem produced by having the constraints of regular arrays of components without the ability to place resistors or under-passes or other cross-over methods wherever desired. This approach, however, appears excellent for breadboarding circuits or making medium quantities of circuits that are similar in their component requiren1ents. requirements. Sandbank: Sand bank: I completely agree that the most precious thing on an inteimportantthat grated circuit is the area and also that it is most important that one should be able to place resistors, etc. exactly where they are required. Reference to our paper will show Dr. Davis that the cellular concept does in fact achieve this object. The only area which we lose is the additional area that is taken up by the isolation between the cells. That is why we felt it was important to investigate the isolation methods and a large part of our paper was devoted to the method which we think will give us close packing of the cells. The basic argument for conserving area in a cellular substrate is that in a monolithic semiconductor circuit all the functions are made of components using one or more layers in the Z direction. Now I think your comments about wasting area can apply to the master slice which has specific components and there is a certain amount of wastage, because if a particular component is not needed, or if a particular component is not in the right position, pOSition, then it cannot be used. Now in our paper we are
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saying that every cell can be part of a resistor, part of a transistor or part 4. 3. If there is any of a capcitor. This is illustrated in figure 3 of paper 4. redundancy in space, the redundancy is in the Z direction, in other words, if this cell is used for a resistor, then there will be certain layers below the surface which will not have been used. That is a waste, but it is a waste in the Z direction, and I think Dr. Davis will agree with me, it is the XY area that we have to preserve. So I don't don I t think we lose any space except for the isolation and as far as putting components exactly where we want to, well we can certainly do this. D a vis: No, I did read your paper. However, I may not have stated clearly the points I wanted to make. Perhaps you can help me clarify this situation. As I understand it, you have an array of cells that can be utilized in different ways, depending on how the layers are finally interconnected. In order to obtain a large usage, the parameters of these unit cells will be dominated by the largest or most difficult components that you wish to produce, for example, physical size by the resistor. Likewise, the parameters and properties of the sub-layers and interconnecting electrodes by other compromises. will be determined by· San db a n k : The basis of the system is that the cell shall be so small that any component contains many cells, and therefore it is not correct to say that the unit cell is determined by the largest component. In other ohm-reSistor, then I use a number of cells to words, if I want a 100 ohm-resistor, make up a 100 ohms. If the unit of resistance of one cell is not quantised in a way which will add to the required value, i. e. suppose you want 106 1/4 ohms (incidentally this would be foolish in an integrated circuit because the tolerances are much wider) but assuming you did want this 106 1/4 ohms, then you would have to use a number of cells in series or value . In this case, I agree; you are probably using parallel to get this value. more space but as always, there is the usual compromise between tolerance, space and economics. Your basic point is not correct when applied to our cellular substrate. substrate . B erg Be r g h a m mer: Will hybrid or monolithic monolithiC circuits achieve the greater importance? Is it conceivable that monolithic circuits will be used predominantly in digital systems, and hybrid circuits predominantly in analogue applications? a n k : I would just really like to remind the meeting of the point San ddb ban that Dr. Davis made at the beginning, namely that one of the potential uses for the passive part of the hybrid will be as interconnecting medium for the monolithic chips. chips . The two techniques are obviously going to be com-
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plementary rather than competitive. I don't see that we will be able to handle these very small chips with hundreds of connections around the edges in future unless we lise \:lse some technique which is very similar to one being used for the passive components at the moment. Although the actual power in the main bulk of the device will still be very small, the "peripheral" equipment may have to handle more power and may be in hybrid form to accommodate this. Beerg r g h a m mer: There is a final question that I would very much like B to ask. The planar technology is nowadays perfected to a very high degree. It is well reproducable and has generally high yields. yields . In MOS-circuits one can obtain the same reliability and reproducability, as well as stability, with fewer processing steps. Furthermore, the MOS-technique lends itself easily to greater complexity and to large-scale integration. Thus one would expect very much lower costs per function. On cost alone it seems to me, MOS-technology appears to be an important integrated circuit technology. technology . What are the future chances of MOS-technology? Storm, (General Electric Company, Schenectady): I am quite sure, that as the Chairman pointed pOinted out, the ultimate cost of production of MOS FET' s bi - polar transistors. But as anybody knows who works will be lower than of bi-polar in this field, they have very formidable surface effects, and at the present time it is not yet quite certain how much cost will accrue on account of the many faults which occur due to surface effect problems. Now here is a question mark. If we may assume that surface effects will be solved then there is no question in my mind that MOS FET' s will be the lower cost elements . elements. baSiS, MOS devices will be less D a vis: I agree that, on a component basis, Unfortunately , they are poor SWitching switching expensive than bi-polar devices. Unfortunately, elements with relatively poor speed and power compared with bi-polar transistors. Thus, in those areas where performance per unit cost is the prinCiple concern, they may not be superior at all. principle Beerg r g h a m mer: I wish to express my sincere thanks to the panel memB bers and to all contributors to this discussion. The IFAC/IFIP IFAC/ IFIP Symposium will close with an invited paper by Prof. Tischner from the Technical University Hannover. His paper is entitled" Circuits of the Nervous System of Organisms as Compared to these of Microelectronics"; it will show how far away are physics and technology from the microminiaturization realized in many biological organisms. In a recent article in the July issue of the IEEE Spectrum, Camras suggests as a
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figure of merit for various storage systems, to multiply three important factors: the capacity (total bits) the density (bits/ cm 3 ) and speed (random access rate in bits/second). This so-called C-D-S (capacity-density-speed) rating is a measure of the overall merit of a system regardless of its size. The CDS figure of merit for a large core memory (2.10 77 bits) 3 X bits per second), whereas 13 (total bits X bits per cm 3 becomes 10 13 23 (total bits X the corresponding number of a human brain is about 10 23 bits per cm 33 X bits per second). The human brain surpasses computers by 10 orders of magnitude (1010), mainly because it is so well microminiaturized, and its high capacity is coupled with reasonable access time. Despite of the considerable progress attained in the field of microminiaturization within the last years, such comparisons between man-made products and natural organisms, such as the human brain, remind us to modesty. At the same time such comparison may be incentive to new deeds, to further research and development, since there is such a wide gap of 10 orders of magnitude, which homo sapiens has to bridge in order to surpass himself. The above comparison shows furthermore that at the present technical state of microminiaturization we can at most point out the tendency and possible directions of significance as well as theoretical limitations, yet the ultimate final goal of microminiaturization cannot be foreseen. With even less certainty can one today estimate the full effect that microminiaturization will exert on industry, on economy and on mankind, yet it is certain that with the advent of microminiaturization a new era has begun, an era of electronics that will pervade all segments of our society.
Be r g h a m mer: Consider that a complete computing centre will not become drastically smaller, even though it has been microminiaturized. Since microminiaturization, in general does not affect all the peripheral equipsystem.. ment, which takes a considerable volume portion of the complete system micron1iniaturized integrated circuit also occupies only Analogously the microminiaturized a small fraction of the volume of a total package. So, what is the technical econon1ical significance of microminiaturization? and economical D a vis: You are all well aware that there is both a technical and economic motivation for integrated circuits. Although the point has been well made.that the electronics contained in digital equipment represents probmade,that ably no more than a third of the cost of that equipment, it is this one-third technologies.. which is the most easily reduced through the use of improved technologies
only.. More reThe first integrated circuits were in the form of hybrids only n10nolithic cently, a great deal of effort has been directed towards silicon monolithic in1provement in this technology has been rather remarkcircuits, and the improvement years.. Thus Thus,, it might be appropriate to spend a able during the last few years lTIOments discussing the current status of these two technologies. few moments technology,, There has been a great deal of emotional discussion over which technology superior.. Let me begin by stating that it is clear monolithic or hybrid, is superior with us for the forethat both monolithic and hybrid circuits are going to be withusfortheforefuture.. And, neither technology will really dominate the circuit seeable future field for a number of years. However, there will be a gradual tendency to employ monolithic circuits in digital applications and hybrids in analogue applications. Although both technologies offer a reduction in cost over the generation of circuits that used discrete components, monolithic circuits lDng run, produce the lowest net circuit cost. Thus Thus,, there will will, in the long be an increased tendency to use digital circuits for functions currently percircuits. formed by analogue circuits, The current relative cost of digital circuits produced by monolithic and hybrid technologies is reflected, I believe, in Figure 11.. The circuit being considered here is a simple "and" gate. The cost figures have been normalized such that the silicon chip employed, which for the monolithic assigned one unit of cost. One technology contains the entire circuit, is aSSigned
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1 GATE/PACKAGE
TECHNOLOGY
MONOLITHIC
HYBRID
3 GATES/PACKAGE
MONOLITHIC
HYBRID
"CHIP COST!! COST"
~
1
3
2
9
PACKAGING COST
~
15 - 20
6
24
7
16 - 21
9
9
5
TOTAL COST / CKT
Figure 1. Cost Comparison of Monolithic and Hybrid Circuits.
is then confronted with the appalling situation that current monolithic packaging techniques add 15 to 20 units of cost. Thus, the cost of the monolithic circuit today is mostly the cost of the package. The hybrid technology designer, in general, recognized early that the key to low circuit cost was in the package and thus applied himself to reducing this cost. One significant result was glass-passivated silicon semifor hermetic containers. The conductor devices, which eliminated the need needfor results are shown in Figure 1. The hybrid designer must employ three times the amount of silicon, since each chip contains only one or, at the most, a few devices. However, the packaging costs of the hybrid circuit, and this includes the cost of packaging the semiconductors, is only six units. The result is a lower total cost for the hybrid circuit than for the monolithic circuit. To reduce the cost of the lllonolithic monolithic chip contained in a hermetic seal package, one can obviously amortize the cost of the package over many circuits; this is generally what is being done in the industry today. The second column of Figure 1 illustrates this case. The monolithic chip has doubled in cost but now contains three gates. Its packaging cost, due to the increased number of leads, has also increased. Significantly, however, the cost per nUlllber circuit has been greatly reduced. Clearly, as the cost of monolithic chip packaging becomes less, monolithic circuit costs are going to become less than those of hybrids. The key then to inexpensive circuits is inexpensive device packaging. Figure 10. of my contribution (see paper 4.8) shows a deVices, including monolithic circuits, that have been variety of silicon chip devices, glass encapsulated to protect them from the atmosphere. Before continuing into the future cost picture, I would like to pause a moment and compare cOlllpare the performances of these various technologies. There is little doubt that at this time, hybrid circuits have higher performance than lllonolithics. 4.8), monolithics. Figure 11 of my paper (see 4. 8), for exalllple, example, shows a hybrid lllodule module containing four circuit gates that function in less than 1 nano-
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second. Such performance, although readily obtainable with hybrid technology, is beyond the current state of monolithic art. One of the more interesting questions the panel may wish to discuss is when this will cease Dr.. Kohn just spoke of the isolation problem and how hyto be the case. Dr brid circuits tend to be somewhat superior due to their ability to provide very good isolation capacitance. Also, interestingly enough, because of the packages currently used for monolithics, the effective circuit density of hybrids is equal to the best monolithics on the market today. Hybrid circuits also offer the advantage of more precise passive components. The future for monolithics, however, is very bright. There is certainly no reason why the same technologies that I have described for hybrids cannot be used for monolithics. In Figure 2, you see a chip containing
Figure 2. A Monolithic and a Single-Transistor Chip.
25 DTL circu~ts. circu~ts. It is compared with a chip 25 thousandth of an inch on a side containing one transistor. The monolithic chip has 24 ball contacts and three levels of interconnections. interconnections . Figure 3 shows these monolithic chips joined to a module approximately 1/2 inch square. This semiconductor chip is soldered to the lands of the module, eliminatingthereliminating thermo-compression bonding. The module also contains some "personality lands," that is, electrode patterns that are screened on the module to determine the logical statements represented by the module. There are a total of 54 circuits on this module.
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Figure 3.
J.Berghammer J. Berghammer
Monolithic Chips Mounted on a Half - Inch Square Ceramic Substrate
more precise passive components will be provided through a In addition, ll10re cOll1bination combination of hybrid and monolithic techniques, in which thin-film COll1components will be deposited on the silicon surface. An example is shown in Figure 4.
Figure 4. Monolithic Chip with Thin- Film Components
Also, in the future, very high circuit density will be achieved on ll1onomonolithic circuits. Figure 5 is a hundred-bit shift register. All the art work required to produce this shift register, containing over 1, 500 components, \vas was produced on an autoll1atic automatic art \vork work generating n1achine, machine, which is shown
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Figure 5. Large Array Produced Through Automatic Artwork Generating Equipment
deternline which in Figure 6. The ability to measure a monolithic wafer to determine importantfor units are operating and then to interconnect good units is very important for nlonolithic circuits. Such automatic artwork generatthe future of low cost monolithic ing equipment is the key to the complex problem of interconnecting the opcircuits.. erating circuits
Figure 6. Automatic Artwork Generating Equipment
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In conclusion, the future will offer many advances in the state of monolithic and hybrid art. Improvements Improvem~nts in packaging will be among the most significant of these technology advances. Be r g h a m mer: Thank you, Dr. Davis, I think you have given us an interesting view of the present status, and you have pointed out that the cost motive was one of the more essential ones and I wonder if the other panel-members share your view. Perhaps there are some other reasons, besides cost, which are of significance to lead to microminiaturization? S and San d bank: Thank you. Well, these gentlemen here have made the difficult decision of coming to see us rather than sample the night life of Munich, so I think I'd like to be honest and give my own personal opinion, but I hope you switch off the tape recorder first. Really what is the reason for microminiaturization, or going into microelectronics? With the exception of a very few users, the people who wanted to send rockets into space or put pacemakers and receivers down people's stomachs, most users don't want the small size. The systems manufacturers were not pressing the component manufacturers to make things smaller, or to make things in monolithic form or so on, they didn't care how it was made. They just wanted the function in a cheap and reliable form. The pressure, let's face it, has come from us, from the component manufacturers.
Why have the component manufacturers given this pressure? Not because they themselves want to do this, but mainly because they are afraid that somebody else will do it first. They are afraid that the next man will make transitors, resistors, reSistors, possibly capacitors, perhaps even inductors more cheaply than they can make components at the moment. Therefore they Circuits, sampling the market, and trying to perare going into integrated circuits, suade the user to buy their integrated circuits, so that, if and when they can make them cheaper than the present components, people will be using theirs, and not their competitor's. But let me conclude, Mr. Chairman, by saying that I believe that they are absolutely right. I believe that this will Situation, but it is not the situation yet, I don't think eventually be the situation, anybody in America or Europe is making a fortune out of monolithic circuits etc. it is mainly an inyestment in the future which must be made by people who want to be sure that they remain in the business. Ra de d e m a k e r s : Three arguments have always played a role in the trend to miniaturize electronic circuitry, which trend has led nowadays to the various kinds of integrated circuits. These arguments were reliability, volume and price, and in the beginning it seemed for some time as if the order of importance of the arguments
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was the same as that in which I mentioned them here. However, with the development of a normal market for integrated circuits, the price argument came forward very strongly, while on the other hand the volume argument lost in importance, since we have already reached the situation where the circuits themselves can be disappearingly small compared with the encapsulations and the means for interconnection. In most cases therefore, the choice between hybrid and semiconductor integrated circuits will be determined in the first place by the price-perfornlance price-performance argument, with reliability and volume in the second and third places. B Beerg r g h a m mer: We all think that the technology of integrated circuits has made considerable progress with respect to microminiaturization. Its products with 10 or 14 leads sticking out of a more or less empty can, have to be connected electrically and mechanically, to make electronic equipment. I wonder whether the possibilities for microminiaturization, as offered by integrated circuit technology, are already sufficiently exploited by the potential users, the equipment designers. Or in other words: can present-day interconnection techniques match integrated circuit technology with respect to microminiaturization? San db a nk: Well I was hoping you'd ask this question, because I have Sandbank: been sitting here sketching an answer to it. But first it is probably worth while thinking a moment why we are now all faced with the interconnection problem. Mter After all, it has hit us quite suddenly, and it isn't just because we have a component which has a lot of leads coming out of it. The industry has been quite used to handling things like small radio valves, which have had 8 to 10 leads. I think the real reason why we are faced problem is that we have this unit which has many with this interconnection problenl leads conling coming out of it, but has to be intimately connected with anything up to a dozen units, which are spread about the system. This is very different from the transistor or the radio valve, which, although it may have 8 or 10 leads coming fronl from it, only has an input, an output, HT and heaters which are connected to the immediately neighbouring circuitry. So there is this problem, that we have both the complex unit, which has a complex relat.ionship relationship with the rest of the system, and the fact that it is small. At -the the same time it still has to be handled by human beings, who throughout this period of microminiaturisation, have remained the same size. Small size in some cases is a disadvantage. It is the economic pressures which Dr. Davis has just mentioned, which force us to small size on the monolithic chip so that we can accommodate more components per unit area. Sooner or later we have to try to regain some of this size, and I put it to
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you that some of the most successful interconnection systems which are going to come along in the future are those which enable us to regain some of the ease of handling which we have lost for economic reasons in the active and passive components themselves. One of the techniques that we have investigated consists of a woven n1atmatrix of interconnections, (see Figs. 7 and 8). It comprises essentially a
Figure 7. Woven matrix with thin-film circuits
flexible epoxy glass strip with a conductor band on each, and these are woven like a piece of cloth so that the conductor always appears on top. This gives the equivalent of a double sided matrix, but the access is always from one face. The cross-points are obtained by laying on a connecting disc and breaks are obtained by cutting the conductor. This is a very convenient way of inter:connecting intesconnecting integrated circuits and is also quite suitable for automation. A computer can programme and control the places where the discs are put or the breaks are made. It is not intended to be a means of interconnecting a lot of integrated circuits closely together and illustrates the point that by putting the integrated circuits around the periphery, ease of handling is obtained at the expense of packing density.
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_ . .iliA) -0
113 -I
- I
Fig;ure 8. Inter Inter-connection Figure -connection layout card: this card, which is in effect the logic diagram, can be used as a template for locating the connecting pellets on the woven matrix
Beerg r g h a m mer: I will turn the discussion to a problem that is related B to the interconnection problem, and it concerns standardization of the external dimensions, lead dimensions, as well as electrical functions. It would probably be beneficial to both the producer and the user if such standardization, at least of external dimensions, could be carried out. What is the current situation with regard to standardization in the United States? And an additional question that also belongs to this subject: which is the most useful container from the standpoint of the user: TO-5-can, flat-pack, dual-in-line, epoxy-can, etc.?
D a vis: The current situation in regard to packaging standards in the U. S. is chaotic. In the first place, there has been a great deal of individuality and invention shown on the part of users and manufacturers. As a result, we have few standard packages at this time, and neither the users nor the manufacturers have been happy with the defacto standards of the flat-pack or TO-5 packages. There has been a desire on the part of the users to find a package that is easier to handle and less expensive. In this regard, there has been con-
792
J. Berghammer
siderable discussion on the relative merits of the in-line or planar package und a package containing pins. Also, there is a general trend toward increasing the number of terminals or leads on the package in order to reduce the effective circuit cost. Recently, a number of manufacturers in the U. S. have introduced packages with more than fourteen leads. Adding confusion to the packaging situation is the possibility of drastically reducing packaging costs by using non-hermetic sealing or epoxy packages. There are a number of committees and national organizations working on standard packages. The increasing complexity of monolithic circuits, however, only tends to heighten the standardization problem. Be r g h a m mer: Would you perhaps also make a remark on the optimum container to be used. D a vis: There is certainly no unique answer. Each user must consider such questions as: How expensive a throw-away package is he willing to use? How complex does he wish his logic functions to be? That is, does he want unit logic, where all the inputs and outputs of the circuits are brought to terminals, or highly functional blocks, where his testing difficulties will be greatly increased. Because of the diversity of user responses, manufacturers will probably produce packages with large numbers of leads, perhaps greater than 30, for those users who wish to employ unit logic and less expensive packages with fewer number of leads for those who wish to have either a few circuits or highly complex logical functions. Ra d e m a k e r s : I would like to start one step back in considering the problem. If we want to fill a certain space with electronics and make all the necessary interconnections, the normal way is to start filling planes with circuits and interconnections, and then stack these planes and interconnect them in one or more of the end faces of the space to be filled. I was interested to see that Dr. Kohn in his fundamental considerations on the lin1its assume that limits of packing denity used the same approach. If we aSSUffie n10n1ent this is the only practical way, then the circuit package at the moment n1ust syst~m. must be adapted to this systt;m. Practice then leads to the following requirements: a) The height of the mounted package must be such that the stacking of the planes can be as dense as allowed by the printed-circuit-board connectors. b) The package must make an economic use of the p-c-board area. c) Mounting, inspection and replacement must be easy. n1Y opinion that these demands will be met best by a rather flat packIt is my
Panel1 Discussion Pane
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age with fixed pins in a standardized grid protruding from one of the large faces of the package. Ko h n: I think there is always a compromise or a trade-off between perKohn: formance and cost, and it can never be overemphasized, also in this respect, what has been said by Dr. Davis about the importance of packaging. For interconnections, better methods, such as light beam coupling, might be employed in the future. This could be a good discussion question for anyone wanting to comment on this. I myself feel, that the electric connection is a very good one and probably the best one. Va n San ten: I do agree with Dr. Kohn that the electrical connection Van is the best one. I think that you can use optical connections when one has no other possibility. But as long as the optical connection means that you lose in speed, and that you also lose in price, then I think that the electrical connection is the best one. Be r g h a m mer: Some remarks were made initially on hybrid circuits. In order to get a balanced view, I would like to ask the following question: What is the future development of monolithic circuits? Since reduction of cost, and increased performance are the prime reasons for further development, we ask: Is it likely that we will continue perhaps to integrate further, and if we integrate integrated circuits, or a number oflogicfunctions, of logic functions, (see for example the supplementary remarks by Seelbach in paper 6.3), I optimum number of "components" to be put on would like to know what is the optin1un1 a silicon chip, is it 50, 100, 1,000 or 10,000? Sandbank: San d ban k: Well, I think this is a question you shouldn't really ask, Mr. Chairman, because you talk in terms of components, and in myopinion it is a fallacy when thinking of integrated circuits to talk in terms of components rather than functions. In the paper that Mr. Horsley and I presented, we describe a cellular substrate, where we have the concept that each component function should consist of many cells, and that infact it is a sort of basic concept of the working of the method, that you don't use just one c.ell c€ll per component function. The analogy that we draw is with the reproduction of a colour picture on a shadow mask CRT, where the screen consists of cells, each having a red, green and blue dot. The whole system depends upon the basic concept, that you never try to reproduce a piece of information with only one cell. Now this is the concept that we have been looking for in the cellular substrate, but this isn't isn I t the ultimate. I think that in the future things will go even further than this. Many designers have been feeling instinctively that it is wrong to think of integratcon1ponents put together, and that ed circuits as a reproduction reprodUction of normal components
794
J. Berghammer
we should somehow try and sidestep this completely. Now, in our cellular substrate we haven't done this yet, because we are still using many cells to produce a transistor function, a diode function, a resistor function, so really we haven't completely got away from the "component" concept. But very recently there has been work on the basic physics of bulk effects in solids, which is beginning to point the way to the direct realization of electronic functions without involving intermediate components. There isn't time, Mr. Chairman, to go into the various points here, but I'd like to give one example, namely the Piezo-electric amplifier. This consists of a piece of bulk semiconduction crystal, such as cadmium sulphide, with transducers at the input and output. A drift field across it causes the acoustic driftfield phonons in the semiconducting cadmium sulphide to interact with the electrons giving growing wave amplification as the electrons drift through the crystal. In practice, one can get as much as 100 dB per cm amplification completeampliat 100 megahertz within the crystal which comprises the complete amplifier. There are many other sorts of bulk effects in the solid which are coming along where I think we will not have to think in terms of components. So I think your question is not so much directed to the distant future, but the more immediate future. D a vis: A better understanding of the question of how many circuits one is likely to place in a monolithic chip can be developed from a very simple model. Consider the top surface of a silicon wafer into which a grid of monolithic circuits has been constructed. Each cell of this grid is indentical and, for the purposes of this model, contains a logic gate. Now the problem is how do we determine the best level of complexity for a single chip. Let us consider processing this wafer in three different ways after the ·circuit circuit grid has been produced. Each circuit in each of the cells of the grid, although complete, is not interconnected with its neighbours. One method of processing the wafer would be simply to cut up the wafer into individual or discrete chips, each containing one circuit. A second way would be to cut the wafer into chips containing four, six, eight, ten, or some other number of circuits. We would, of course, interconnect these circuits before cutting up the wafer. The third method would be to connect a large number of working circuits on the wafer proper. Let us now consider the economics of these various approaches. The price of the chip increases as the size of the chip and, thus, the number of cells on it rises, for two reasons. First, the chip contains more materials, and obviously a greater percentage of the total manufacturing investment is represented by the wafer. Secondly, and more importantly, the yield of the finished chip has been reduced, since it is now required that each individual cell contained within this chip in this non-redundant system be oper-
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able. (That is, for the complete chip to be acceptable, each individual unit cell must also be acceptable.) Note, however, that the cost also rises for very small chips containing very few cells because there is a minimum chip size that can be physically handled. Presently this chip size is larger than the amount of silicon required to produce a single circuit. currenttechnology, Thus, with current technology, a curve of number of circuits per chip (that is, number of generated cells per chip) versus cost shows a typical minimum somewhere between two and four circuits. The cost curve then generally rises slightly through seven to ten circuits, after which it begins to increase very rapidly. Unlike the cost per unit circuit at the silicon chip level, the cost 'per unit circuit of the package tends to descrease monotonically with increasing number of circuits within the package. When the silicon chip cost and the packaging cost are added together, the resulting curve has a minimum for packages containing three to fifteen circuits. In the future, the increasing yield of semiconductors, together with the decreasing size of the unit cells, will change the cost-versus-number-of-circuits curves. The increased yields will broaden the base, and the decreased unit cell size will tend to lower costs over a wider range flatten out the edges of these curves, giving lowercosts of circuit packages. Returning to the wafer, one may plot a cost curve for interconnection schemes where the individual circuits are tested on the wafer and the good circuits are interconnected in large arrays on the wafer before packaging. One must build some redundancy in circuit count on the wafers for such an approach. The cost curve for such "large scale integration" tends to offer low cost for wide ranges of circuit counts. semiconductor chip must be measurBecause every single circuit on the semiconduc.tor ed and the data from these measurements must pass through a computer, Circuits, this computer time rewhich in turn interwires the operating circuits, presents a major portion of the circuit cost. The feasibility of this approach will be determined by the cost of this measurement and the computer generated art work step. In the future, a bootstrapping situation may well take place, where the use of monolithic circuits will reduce the cost of computers, thus, making possible a further reduction in the cost of the circuits.
Be r g h a m mer: In the computer-field it has been customary to talk about generations of computers. Tubes, transistors and integrated circuits characterise the first, second and third generation of computers. It is fair to assume that a third generation will also have descendants.
796
J. Berghammer
What will be the replacement for the conventional present-day integrated circuits? San d ban k: I think I've already given the answer really, Mr. ChairSandbank: man, in the sense that naturally I think our cellular substrate will be widely used and therefore this will be the next generation. The generation after this I think will be the bulk effect in the solid state which will not have intermediate components but will use the properties of the solid to achieve the function. D a vis: Yes, I disagree. Nothing is more precious on a silicon monolithic wafer than its area, and thus every effort is made to reduce the area employed per circuit to a bare minimum, especially for products that are to be produced in quantities. Thus, any approach such as the cellular substrate presented by Mr. Sandbank will prove to be more expensive than the unique masking processes, for two reasons: 1. The increase in area required to generate the circuit because of the compromises that are required in generating an array of identical cells that would be useful and in making more than one circuit configuration. 2. The interconnection problem produced by having the constraints of regular arrays of components without the ability to place resistors or under-passes or other cross-over methods wherever desired. This approach, however, appears excellent for breadboarding circuits or making medium quantities of circuits that are similar in their component requiren1ents. requirements. Sandbank: Sand bank: I completely agree that the most precious thing on an inteimportantthat grated circuit is the area and also that it is most important that one should be able to place resistors, etc. exactly where they are required. Reference to our paper will show Dr. Davis that the cellular concept does in fact achieve this object. The only area which we lose is the additional area that is taken up by the isolation between the cells. That is why we felt it was important to investigate the isolation methods and a large part of our paper was devoted to the method which we think will give us close packing of the cells. The basic argument for conserving area in a cellular substrate is that in a monolithic semiconductor circuit all the functions are made of components using one or more layers in the Z direction. Now I think your comments about wasting area can apply to the master slice which has specific components and there is a certain amount of wastage, because if a particular component is not needed, or if a particular component is not in the right position, pOSition, then it cannot be used. Now in our paper we are
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saying that every cell can be part of a resistor, part of a transistor or part 4. 3. If there is any of a capcitor. This is illustrated in figure 3 of paper 4. redundancy in space, the redundancy is in the Z direction, in other words, if this cell is used for a resistor, then there will be certain layers below the surface which will not have been used. That is a waste, but it is a waste in the Z direction, and I think Dr. Davis will agree with me, it is the XY area that we have to preserve. So I don't don I t think we lose any space except for the isolation and as far as putting components exactly where we want to, well we can certainly do this. D a vis: No, I did read your paper. However, I may not have stated clearly the points I wanted to make. Perhaps you can help me clarify this situation. As I understand it, you have an array of cells that can be utilized in different ways, depending on how the layers are finally interconnected. In order to obtain a large usage, the parameters of these unit cells will be dominated by the largest or most difficult components that you wish to produce, for example, physical size by the resistor. Likewise, the parameters and properties of the sub-layers and interconnecting electrodes by other compromises. will be determined by· San db a n k : The basis of the system is that the cell shall be so small that any component contains many cells, and therefore it is not correct to say that the unit cell is determined by the largest component. In other ohm-reSistor, then I use a number of cells to words, if I want a 100 ohm-resistor, make up a 100 ohms. If the unit of resistance of one cell is not quantised in a way which will add to the required value, i. e. suppose you want 106 1/4 ohms (incidentally this would be foolish in an integrated circuit because the tolerances are much wider) but assuming you did want this 106 1/4 ohms, then you would have to use a number of cells in series or value . In this case, I agree; you are probably using parallel to get this value. more space but as always, there is the usual compromise between tolerance, space and economics. Your basic point is not correct when applied to our cellular substrate. substrate . B erg Be r g h a m mer: Will hybrid or monolithic monolithiC circuits achieve the greater importance? Is it conceivable that monolithic circuits will be used predominantly in digital systems, and hybrid circuits predominantly in analogue applications? a n k : I would just really like to remind the meeting of the point San ddb ban that Dr. Davis made at the beginning, namely that one of the potential uses for the passive part of the hybrid will be as interconnecting medium for the monolithic chips. chips . The two techniques are obviously going to be com-
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J. Berghammer
plementary rather than competitive. I don't see that we will be able to handle these very small chips with hundreds of connections around the edges in future unless we lise \:lse some technique which is very similar to one being used for the passive components at the moment. Although the actual power in the main bulk of the device will still be very small, the "peripheral" equipment may have to handle more power and may be in hybrid form to accommodate this. Beerg r g h a m mer: There is a final question that I would very much like B to ask. The planar technology is nowadays perfected to a very high degree. It is well reproducable and has generally high yields. yields . In MOS-circuits one can obtain the same reliability and reproducability, as well as stability, with fewer processing steps. Furthermore, the MOS-technique lends itself easily to greater complexity and to large-scale integration. Thus one would expect very much lower costs per function. On cost alone it seems to me, MOS-technology appears to be an important integrated circuit technology. technology . What are the future chances of MOS-technology? Storm, (General Electric Company, Schenectady): I am quite sure, that as the Chairman pointed pOinted out, the ultimate cost of production of MOS FET' s bi - polar transistors. But as anybody knows who works will be lower than of bi-polar in this field, they have very formidable surface effects, and at the present time it is not yet quite certain how much cost will accrue on account of the many faults which occur due to surface effect problems. Now here is a question mark. If we may assume that surface effects will be solved then there is no question in my mind that MOS FET' s will be the lower cost elements . elements. baSiS, MOS devices will be less D a vis: I agree that, on a component basis, Unfortunately , they are poor SWitching switching expensive than bi-polar devices. Unfortunately, elements with relatively poor speed and power compared with bi-polar transistors. Thus, in those areas where performance per unit cost is the prinCiple concern, they may not be superior at all. principle Beerg r g h a m mer: I wish to express my sincere thanks to the panel memB bers and to all contributors to this discussion. The IFAC/IFIP IFAC/ IFIP Symposium will close with an invited paper by Prof. Tischner from the Technical University Hannover. His paper is entitled" Circuits of the Nervous System of Organisms as Compared to these of Microelectronics"; it will show how far away are physics and technology from the microminiaturization realized in many biological organisms. In a recent article in the July issue of the IEEE Spectrum, Camras suggests as a
Panel Discussion
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figure of merit for various storage systems, to multiply three important factors: the capacity (total bits) the density (bits/ cm 3 ) and speed (random access rate in bits/second). This so-called C-D-S (capacity-density-speed) rating is a measure of the overall merit of a system regardless of its size. The CDS figure of merit for a large core memory (2.10 77 bits) 3 X bits per second), whereas 13 (total bits X bits per cm 3 becomes 10 13 23 (total bits X the corresponding number of a human brain is about 10 23 bits per cm 33 X bits per second). The human brain surpasses computers by 10 orders of magnitude (1010), mainly because it is so well microminiaturized, and its high capacity is coupled with reasonable access time. Despite of the considerable progress attained in the field of microminiaturization within the last years, such comparisons between man-made products and natural organisms, such as the human brain, remind us to modesty. At the same time such comparison may be incentive to new deeds, to further research and development, since there is such a wide gap of 10 orders of magnitude, which homo sapiens has to bridge in order to surpass himself. The above comparison shows furthermore that at the present technical state of microminiaturization we can at most point out the tendency and possible directions of significance as well as theoretical limitations, yet the ultimate final goal of microminiaturization cannot be foreseen. With even less certainty can one today estimate the full effect that microminiaturization will exert on industry, on economy and on mankind, yet it is certain that with the advent of microminiaturization a new era has begun, an era of electronics that will pervade all segments of our society.