Parasitic effects and long term stability of InP-based HEMTs

MICROELECTRONICS RELIABILITY

PERGAMON

Microelectronics Reliability 40 (2000) 1715-1720 www.elsevier.com/locate/microrel

Parasitic effects and long term stability of InP-based HEMTs G. Meneghesso, R. Luise, D. Buttari, A. Chini, H. Yokoyama*, T. Suemitsu*, E. Zanoni Dipartimento di Elettronica e Informatica and INFM, Universita di Padova, Via Gradenigo 6/A 35131 PADOVA, Italy *NTT Photonics Laboratories, 3-1, Morinosato-Wakamiya Atsugi-shi, Kanagawa 243-01, Japan

Abstract

A sthdy of InP based HEMTs implemented with different process options will be reported. It will be demonstrated that devices with an InP etch stopper layer or with a narrow lateral gate recess region do not present any kink effect, neither any transconductance frequency dispersion, gin(f) and a stable behavior with respect to hot electron aging is observed. The opposite occurs in devices without.the InP etch stopper layer and a wide lateral gate recess region. The data presented confirm the effectiveness of an InP passivating layer in improving the reliability of advanced InP-HEMTs, and point out at the free InA1As surface as responsible for the observed instabilities (kink effects, gm(f) dispersion). © 2000 Elsevier Science Ltd. All rights reserved.

1. Introduction

The high performances properties of InA1As/ /InGaAs/InP High Electron Mobility Transistors (HEMTs) are already well known in particular for very high frequency and low noise applications [1,2]. Unfortunately, quite often, these devices suffer from parasitic phenomena like kinks in the output I-V curves and of parametric degradation after aging at high bias regime [3,4]. In MBE-grown InA1As/lnGaAs/InP HEMTs, Kruppa and Boos [5] have associated the decrease of transconductance as a function of frequency with surface traps in the gate recess region having activation energy of 0.17 eV. These traps were observed only in the presence of a double-recess structure. B. Georgescu et al. [6] have recently described kink effects in InAIAs/InGaAs/InP composite channel HEMTs, mainly related to trapping/detrapping processes in the top layers". The correlation between surface traps and kink in the output characteristics has

been demonstrated also by T. Suemitsu et al. [7] by means of two dimensional device simulation. The increased source resistance due to the presence of traps in the gate-to- source access region can be completely compensated by hole pile-up in the channel at the source side due to holes generated by impact - ionization. The pile up leads to an increase of Io and hence to the appearing of the kink. H. Wang et al. [8] have found that the kink in InA1As/InGaAs HFETs can be suppressed by using suitable-deposited silicon nitride passivation. Finally, R. Menozzi et al. have found a dependence of the hot-electron degradation of InA1As/InGaAs/InP HEMTs on the presence of PECVD SiN passivation [9], and on the geometry of the recess width [10]. All these results point to a crucial role of device surface layers, especially in the exposed gate recess region, in determining kink effects and low frequency transconductance dispersion and reliability problems. In this paper we will present a study concerning InA1As/InGaAs HEMT devices

0026-2714/00/$ - see front matter. © 2000 Elsevier Science Ltd. All rights reserved. PII: S0026-2714(00)00168-2

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G. Meneghesso et al./ Microelectmnics ReliabiliO,40 (2000) 1715-1720

Source

Gate

brain

5

t VGs:-0.4~ 0.2V,0.1V/step I T=20°C 4 T=-80°C

~ J

~'3

~2

0.5

1.5 VDS (V)

Fig.l: Schematic cross section of a standard InP-based HEMTs WITH an InP etch-stop layer grown on top of the InA1As barrier layer. All layers are MOCVD grown LM on InP. The standard device present a WIDE gate recess regions (Lgc = O. 1pro) and is called A1.

Fig.2: Output I-V curves obtained in a device without the InP stopper (removed with a second step etching procedure) and wide gate recess region (B2 device), measured at room (solid) and -80°C (dashed). VGS from --0.4 to 0.2V, step 0.1V.

With InP recess-etch stopper,( MOCVD I

with different process properties.

3

I

I

VGs: -0.4~ 0.1V,0.1V/step _ T=20oC ~ _ T = ' 8 ~0~ ~°-

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2 . Device description All the studied devices are 0.1 pm gate length and 10/~m gate width InP-based LM (lattice-matched) HEMTs [11]. The MOCVD grown basic epitaxial structure consists of a 2000/~ thick InAIAs buffer, a 150/~ thick InGaAs channel, a 30/~ InA1As spacer, a Si-8-doped plane, a 60 A InA1As Schottky barrier, a 50/~ InP-recess-etch stopper, and n+-InAIAs/n +InGaAs cap layers. We also studied HEMTs having the same structure except for the absence of the lnPrecess-etch stopper. In both devices the whole structure is covered by a SiO2/SiN bi-layer. Figure 1 shows a schematic cross section of the studied devices. The standard gate recess region width (distance between CAP and gate contact) is Lgc = O. 1pm. We have investigated five types of devices characterized mainly by the following differences: A) Devices W I T H the InP etch stopper layer; A1) The InP stopper layer cover all the gate access region and the gate is placed over the InP (see Fig. 1), or A2) the InP stopper cover all the ungated gate recess region, hence the gate directly contacts the InA1As barrier layer [12]. B) Devices W I T H O U T the InP etch stopper layer; B1) The InP stopper has not been grown during the device processing, these devices have a Lgc = 0.02pm (B1 devices have a narrow gate re-

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VDS (V) Fig.3: Output I-V curves obtained in a device with the InP stopper layer (A1 device) measured at room (solid) and -80°C (dashed). Vc,s from -0.4 to 0. IV, step of 0. IV.

cess region). A previously grown InP stopper layer, between the CAP and the barrier, has been removed in the access region by a subsequent etching process step. By using two different etching times, devices with standard Lgc B2) or Lgc = 0.02/~m B3) have been obtained.

3 . Parasitic effects Devices without InP recess-etch stopper layer and wide lateral recess region (device B2) are affected by a kink in the output I-V characteristics, which is enhanced at low temperature, see for instance Fig. 2.

G. Meneghesso et al./ Microelectronics Reliability 40 (2000) 1715-1720

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Fig.6: IG vs VGSat different VDSmeasured at +20°C (solid

Fig.4: Output I-V curves obtained in a device without the InP stopper layer (B1 device) measured at room (solid) and -80°C (dashed). VGSfrom 0 to 0.6V, step of 0. IV.

lines) and -80°C (dashed lines) in a device without the InP stopper and wide lateral recess region.

InP etch stop layer. A shift towards lower frequency is observed on the g,n (f) dispersion on decreasing the temperature. The characteristic frequency FM is the frequency where the dispersion is half of the total one. By plotting Fta(T)/T 2 as a function of 1/kT in an Arrhenius plot, a straight line is obtained; see inset of Fig. 7. From the slope of this line, an activation energy of 0.28 + 0.03eV has been obtained.

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Fig.5: Normalized trasconductance frequency dispersion in all the studied devices. Only in the B2 device (i.e. the one without the InP stopper layer and with wide gate recess region) present gm (f) dispersion.

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On the contrary, kink effect is almost not observed, even at low temperature, in the devices with InP etch stop layer (see Fig. 3 for the A1 device) or in devices with a narrow lateral recess region, see for instance measurements reported in Figure 4 carded out in a B1 device. Similarly to the kink effects, transconductance frequency dispersion has been observed only in the B2 device, i.e. in the device without the InP stopper layer and wide lateral recess region, see Fig. 5. On the other hand, the typical bell shape behaviour in the IG vS VGS curves, has been observed in all the devices demonstrating that impact ionization is always present, see for instance Fig. 6. In Fig. 7 the transconductance frequency dispersion is reported as a function of temperature for Vos = 100mV and V~s = - 6 0 0 m V in a device without

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Fig.7: gin(f) measured at different temperatures (VDs = 0.1V, VGS = -0.6V) in a device without the TnP stopper and wide lateral recess region. The corresponding Arrhenius plot is depicted in the inset. In devices having a wide lateral recess region without InP etch stopper layer, traps in the gate-source and gate-drain access region can become negatively charged due to capture of electrons. This trapped charge induces an increase of the parasitic drain and source resistances, Rs and Ro, reducing the Io at low Vos. At increasing VDS,several effects can lead to a change of the trapped charge and/or to the modification of potential profile in the gate-source and gate-drain recess

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G. Meneghesso et aL/Microelectronics Reliability 40 (2000) 1715-1720

region: • Compensation of the negative trapped charge at the source side by the accumulation of holes generated by impact ionization; • Field assisted electron detrapping in the high field gate-to-drain region;

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T 20"C

All these phenomena lead to a reduction of the parasitic resistances hence to a recovery of the drain current (thus originating the kink effect). Devices adopting the InP etch stopper layer are free from surface traps, and therefore kink effects are strongly reduced even in the presence of impact ionization. Recently, M. Somerville and coworkers [14], have presented a physical model for the kink effect in InA1As/InGaAs HEMTs. In their model, the kink effect results from a threshold voltage shift consequent to hole pile up at the device source access region. The authors in [ 14] believe that the more important effect is the change in channel potential beneath the source end of the gate, Vkink and they attribute a minor role to the parasitic source resistance Rs. The change in the channel potential due to hole accumulation is equivalent in their model to a threshold voltage shift, so that the amplitude of the kink id AID = gm" V k i n k ' ~ gm" AVth. In order to understand if the kink is due to a threshold voltage shift or to a reduction of the parasitic resistance, we have measured the transconductance in the device of Fig. 1 (B2 device) at Vos = 0.3 V and 0.7 V, i.e. before and after the kink, at two different temperatures, see Figure 8. As it can be observed, the main feature observed before and after the kink is a change in the transconductance peak without any apparent shift in the threshold voltage with respect to the "kink" region. This suggests that the parasitic resistance reduction is the main responsible for the Io increase (and then kink effect) rather than the threshold voltage shift. This confirms that, at least in these devices, the remarkable kink effect observed can not be ascribed to hole pile up alone (since impact ionization and

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• Impact-ionization of traps by hot electrons [13],

which would release trapped charge, thus reducing or suppressing the drain current decrease. This process requires lower energies than electron-hole pair creation by band-to-band ionization [13] and therefore can take place at substantially lower drain voltages.

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Fig.8: gm measured at VDS = 0.3 and 0.7 V (i.e. before and after the kink) at +20°C hence hole pile-up are present in all device technologies) but it is due to the simultaneous presence of traps in the access regions and hole pile-up at the source side. These results experimentally support the discussion in [7] and suggest that the kink effects are very sensitive to the gate recess geometry and technology. Nevertheless, it should be mentioned that other mechanisms can contribute to induce slighter kink effects in InP-based HEMTs such as holes generated by impact-ionization and/or deep levels in the substrate [15].

4 . Device reliability

Devices have been submitted to hot electron stress 6

5

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Stress test: 10hrs at Vos=2.5V, VGs=-0.3V

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o6 , o 2 v

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.5

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VDS (V)

Fig.9: Output characteristics before (solid line) and after (dashed) hot electron stress test in a device without the InP stopper and wide lateral recess region.

G. Meneghesso et al./ Microelectronics Reliability 40 (2000) 1715-1720

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4 - - VDS=0.3v unstressed / (solid)

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stressed (dashed)

3 - - B2) device

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-0.6

-0.4

-0.2

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0.2

YEs (V)

Fig. 10: t~ansconductancemeasuredbefore (solid line) and after (dash line) hot electron stress test (measured at VDS = 0.3 V) in a device without the InP stopper and wide lateral recess region (B2 device). 7

Stress test120hrs at Vo'~=2.5V, VGS=0.1V

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persion (not shown) were also observed in these devices. The activation energy, measured from gin(f) measurements in the stressed devices, was the same as in the virgin devices. All these features suggest surface state creation in the high field gate drain access region as degradation mechanism. The increased trap density leads to an amplification of the already present instabilities (i.e. kinks and gin(f) dispersion). These degradation effects were not observed both in devices with the InP etch stopper layer. In devices without the InP etch stopper layer and with narrow lateral recess region a slight degradation (without appearance of any kinks) takes place after hot-electron stress test (see Fig. 11). The degradation is completely recovered after a few hours of unbiased storage at room temperature.

5 . Conclusions

6 -VGs: 0 ~ 0'.6V, 0.1V/step

5

1719

f

2

Vvs (V) Fig. 11: Output characteristics before and after hot electron stress test in a device without the InP etch stopper and narrow lateral gate recess region. Before stress: solid lines. After stress (20h at VDS = 2.5V and VOS = 0.1V): dashed lines. After stress and few minutes of recovery: dash-dotted lines.

Data presented here demonstrate that the InP etch stopper layer, which is a viable solution to the problem of Vth reproducibility, also contributes to largely suppress kink effects and improves the long term stability of in InP-based HEMT's. This indicates the effectiveness of an InP "passivating" layer (improving the reliability of advanced InP-HEMTs) and points at the free InA1As surface as responsible for the observed instabilities (kink effects and gm ( f ) dispersion). A narrow gate recess region also suppress the kink without requiting any InP surface layer, but this induces a remarkable decrease in the breakdown voltage, which makes this solution un-practical.

Acknowledgements test in order to evaluate the device's long term stability. The bias conditions have been chosen in order to have the maximum impact ionization process (i.e. in the peak of the IG vs VGS bell shape). Figure 9 report the effect of 10 hrs of hot electron stress test carded out in a B2 device i.e. in a device without the InP stopper (removed with a further etching procedure) and wide gate recess region. The bias conditions were: VDS = 2.5 V, VGS = --0.3 V. Enhancement of the kink effects after hot electron life test can be observed. The hot electron stress induced a large increase in the parasitic resistance and some threshold voltage shift as suggested by Figure 10. Increase in the transconductance frequency dis-

This work was partially supported by the NTT Photonics Laboratory, ASI Project, MURST and Progetto Finalizzato CNR MADESS II.

References [1]

Nguyen L. D., Brown A. S., Thompson M. A. and L. M. Jelloian, 50-nm Self-Aligned-Gate Pseudomorphic AllnAs/GalnAs High Electron Mobility Transistors, IEEE Trans. on El. Dev. (39) p. 2007, 1992. [2] Enoki T., Arai K., Kohzen A. and Y. Ishii, InGaAs/InP double channel HEMT on InP, Proc. of Int. Symp. on Indium Phosphide and Rel. Mat. p. 371, 1992.

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[3] Menozzi R., Borgarino M., Baeyens Y., Van Hove M. and Fantini F., On the Effects of Hot Electrons on the DC and RF Characteristics of Lattice-Matched InAIAs/lnGaAs/InP HEMT's, IEEE Microw. and Guided Wave Lett. (7), p. 3, 1997. [4] Wakita A. S., Rohdin H., Su C. Y., Moll N., Nagy A. and Robbinset V. M., Drain Resistance Degradation Under Ultra High Fields in AllnAs/GalnAs MODFETs, Proc. of Int. Syrup. on Indium Phosphide and Rel. Mat. p.376, 1997. [5] Kruppa W. and Boos J. B., Low-Frequency Trasconductance Dispersion in InAIAs/InGaAs/InP HEMT's with Single- and Double-Recessed Gate Structures, IEEE Trans. on El. Dev. (44) p. 687, 1997. [6] Georgescu B., Py M. A., Soufi A., Post G. and Guillot G., New Aspect and Mechanism of Kink Effect in InAIAs/InGaAs/InP Inverted HFET's, IEEE El. Dev. Lett. (19), p. 154, 1998. [7] Suemitsu T., Enoki T., Tomizawa M., Shigekawa N. and Ishii Y., Mechanisms and Structural dependence of kink phenomena in InAIAS/InGaAs HEMTs, Proc. of Int. Syrup. on Indium Phosphide and Rel. Mat. p.365, 1997. [8] Wang H., Ng G.I., Gilbert M., O'Sullivan P.J., Suppression of I-V kink in doped channel InAIAs/InGaAs/InP heterojunction field-effect transistor (HFET) using silicon nitride passivation, IEE E1.Lett. (32), p. 2026, 1996. [9] Menozzi R., Borgarino M., Baeyens Y., Van der Zanden K., Van Hove M. and Fantini F.,The Effect of Passivation on the Hot Electron Degradation of LatticeMatched InAIAs/lnGaAs/InP HEMTs, Proc. of Int. Symp. on Indium Phosphide and Rel. Mat. p. 153, 1997.

[I0] Menozzi R., Borgarino M., van-dcr-Zanden K., Schrcurs D., On the correlation between drain-gate breakdown voltage and hot-electronreliabilityin InP HEMTs, IEEE El. Dev. Lett. (20),p. 152, 1999. [I I] Enoki T., Ito H. and IshiiY.,ReliabilityStudy on InAIAs/InGaAs HEMTs with an InP Recess-Etch Stopper and Refractory Gate Metal, Solid State Electronics,Vol. 41, No. 10, pp. 1651, 1997. [12] Suemitsu T., Enoki T., Yokoyama H., Ishii Y., Improved recessed-gate structure for sub-0.l-gm-gate InP-based high electron mobility transistors,Jpn. J. Appl. Phys. (37) p. 1365, 1998. [13] Partain L., Day D. and Powell R., Metastable Impact Ionizationof Traps Model for Lock-On in GaAs Photoconductive Switches, J. Appl. Phys., vol. 74, n. I, pp. 335-340, July 1993. [14] Somerville M. H., Ernst A., Del Alamo J. A., A physical model for the kink effect in InAIAs/InGaAs HEMTs, IEEE Trans. on El. Dev., vol. 47, no. 5, pp. 922-930, May 2000 [15] Haruyama J., Negishi H., Nishimura Y., Nashimoto Y., Substrate-Related Kink Effects with a Strong Light-Sensitivity in A1GaAs/lnGaAs PHEMT, IEEE Trans. on El. Dev. (44) p. 25, 1997.