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Performance analysis of a microprogrammed real-time operating system with an interrupt-and-abort discipline
R& D reports support and compares the implementations provided by these microprocessors.
Rauch, K 'Math chips: how they work' IEEE Spectrum Vol 24 No 7 (July 1987) pp 25-30
performance evaluation of parallel algorithms' Microprocess. Microprog. Vo119 No 3 (June 19~7) pp 179-192
interruptable. A pilot implementation has been performed on a DEC LSI-11 processor.
A single-shared-bus, shared-memory multiprocessing system based on Inte116-bit microcomputer boards is discussed.
Semicustom ICs
Natural language processing
'Programmable logic - - architectures and applications' J. Semicustom ICs Vol 4 No 4 (June 1987)
Bolton, M l D
Motion analysis Burnie, J, Taylor, M J and Yuen, P E l 'Microcomputing in motion analysis' J. Microcomput. Appl. Vol 10 No 2 (April 1987) pp 113-117 A system is described that analyses human movement patterns captured on film or video tape. Selected anatomical 'landmarks' are used to identify limb segments and movement phases. The system, which uses a sonic digitizer interfaced to a Commodore 4032 microcomputer, has been used to compare the gait patterns of muscular distrophy patients with those of a control group of matched subjects.
Multiprocessors Abou-Rabia, O and Birta, L G 'The design of a multimicrocomputer system for continuous system simulation' J. Microcomput. AppL Vo110 No 2 (April 1987) pp 137-151 Continuous system simulation using multiprocessor systems has traditionally used decomposition, whereby a set of n differential equations is broken down into Np subgroups to be allocated to Np processors. This approach creates problems in ensuring an even workload for all processors. This paper suggests an alternative approach using a parallel algorithm to solve the differential equations, and describes an implementation based on a series of Intel SBC86/05 single-board microcomputers communicating through an array of replicated memories.
Ghosal, D and Patnaik, L M 'SHAMP: an experimental shared memory multiprocessor system for
Vol 11 No 9 November 1987
Sanamrad, M A, Wada, K and Matsumoto, H 'A hardware syntactic analysis processor' IEEE Micro Vol 7 No 4 (August 1987) pp 73-80 Most natural language processing systems are implemented using highlevel languages such as LISPor PROLOG. However, an algorithm has been proposed (Dubinsky, S and Sanamrad, M A 'Binary coding of universal syntactic features for a natural language processor' Preprints
1984 Kansai Regional Joint Cony. Electrical Engineers Japan, Yamakatsu, Osaka, Japan (November 1984) p G270) that uses binary operations for certain levels of natural language processing, particularly syntactic processing, enabling microcomputer implementation of a syntactic analyser. The authors describe a hardware syntactic analysis processor design based on this algorithm. Realtime systems Tempelmeier, T 'Performance analysis of a microprogrammed real-time operating system with an interrupt-and-abort discipline' Microprocess. Microprog. Vo119 No3 (June 1987) pp 233-251 Response time rather than throughput or CPU utilization is the most important measure of efficiency in realtime systems. To speed up the operating system kernel functions and reduce operating system overhead in realtirne systems the author proposes shifting the operating system to the microprogramming level. This makes the kernel function executable in the manner of a typical machine instruction. The functions are also
Programmable logic devices (PLDs), in the form of memories, have always been essential in digital design, but other varieties such as those used in application-specific design are only now achieving wide use. The paper provides an overview of the current state of PLD evolution, discussing both device structures and design techniques.
Freeman, R 'The logic cell array: a new programmable gate array family' J. Semicustom ICs Vol 4 No 4 (June 1987) Describes Xilinx's new user programmable gate array that combines the usable density of gate arrays with the flexibility and ease of use of standard logic circuits.
Software engineering Card, D N, McGarry, F E and Page, GT 'Evaluating software engineering technologies' IEEE Trans. Software Eng. Vol SE-13 No 7 (July 1987) pp 845-851 Few software development practices, tools and techniques have been evaluated experimentally. This can be attributed to an insufficient understanding of the software development process, a lack of recognized standards for measurement, and the prohibitive costs of large-scale controlled experiments. This study measured the software engineering technologies in a production environment and developed a statistical model to evaluate their effectiveness. From a carefully matched sample of 22 projects it was found that the
505
Rauch, K 'Math chips: how they work' IEEE Spectrum Vol 24 No 7 (July 1987) pp 25-30
performance evaluation of parallel algorithms' Microprocess. Microprog. Vo119 No 3 (June 19~7) pp 179-192
interruptable. A pilot implementation has been performed on a DEC LSI-11 processor.
A single-shared-bus, shared-memory multiprocessing system based on Inte116-bit microcomputer boards is discussed.
Semicustom ICs
Natural language processing
'Programmable logic - - architectures and applications' J. Semicustom ICs Vol 4 No 4 (June 1987)
Bolton, M l D
Motion analysis Burnie, J, Taylor, M J and Yuen, P E l 'Microcomputing in motion analysis' J. Microcomput. Appl. Vol 10 No 2 (April 1987) pp 113-117 A system is described that analyses human movement patterns captured on film or video tape. Selected anatomical 'landmarks' are used to identify limb segments and movement phases. The system, which uses a sonic digitizer interfaced to a Commodore 4032 microcomputer, has been used to compare the gait patterns of muscular distrophy patients with those of a control group of matched subjects.
Multiprocessors Abou-Rabia, O and Birta, L G 'The design of a multimicrocomputer system for continuous system simulation' J. Microcomput. AppL Vo110 No 2 (April 1987) pp 137-151 Continuous system simulation using multiprocessor systems has traditionally used decomposition, whereby a set of n differential equations is broken down into Np subgroups to be allocated to Np processors. This approach creates problems in ensuring an even workload for all processors. This paper suggests an alternative approach using a parallel algorithm to solve the differential equations, and describes an implementation based on a series of Intel SBC86/05 single-board microcomputers communicating through an array of replicated memories.
Ghosal, D and Patnaik, L M 'SHAMP: an experimental shared memory multiprocessor system for
Vol 11 No 9 November 1987
Sanamrad, M A, Wada, K and Matsumoto, H 'A hardware syntactic analysis processor' IEEE Micro Vol 7 No 4 (August 1987) pp 73-80 Most natural language processing systems are implemented using highlevel languages such as LISPor PROLOG. However, an algorithm has been proposed (Dubinsky, S and Sanamrad, M A 'Binary coding of universal syntactic features for a natural language processor' Preprints
1984 Kansai Regional Joint Cony. Electrical Engineers Japan, Yamakatsu, Osaka, Japan (November 1984) p G270) that uses binary operations for certain levels of natural language processing, particularly syntactic processing, enabling microcomputer implementation of a syntactic analyser. The authors describe a hardware syntactic analysis processor design based on this algorithm. Realtime systems Tempelmeier, T 'Performance analysis of a microprogrammed real-time operating system with an interrupt-and-abort discipline' Microprocess. Microprog. Vo119 No3 (June 1987) pp 233-251 Response time rather than throughput or CPU utilization is the most important measure of efficiency in realtime systems. To speed up the operating system kernel functions and reduce operating system overhead in realtirne systems the author proposes shifting the operating system to the microprogramming level. This makes the kernel function executable in the manner of a typical machine instruction. The functions are also
Programmable logic devices (PLDs), in the form of memories, have always been essential in digital design, but other varieties such as those used in application-specific design are only now achieving wide use. The paper provides an overview of the current state of PLD evolution, discussing both device structures and design techniques.
Freeman, R 'The logic cell array: a new programmable gate array family' J. Semicustom ICs Vol 4 No 4 (June 1987) Describes Xilinx's new user programmable gate array that combines the usable density of gate arrays with the flexibility and ease of use of standard logic circuits.
Software engineering Card, D N, McGarry, F E and Page, GT 'Evaluating software engineering technologies' IEEE Trans. Software Eng. Vol SE-13 No 7 (July 1987) pp 845-851 Few software development practices, tools and techniques have been evaluated experimentally. This can be attributed to an insufficient understanding of the software development process, a lack of recognized standards for measurement, and the prohibitive costs of large-scale controlled experiments. This study measured the software engineering technologies in a production environment and developed a statistical model to evaluate their effectiveness. From a carefully matched sample of 22 projects it was found that the
505