- Email: [email protected]
Performance enhancement of GaN SB-MOSFET on Si substrate using two-step growth method
Microelectronic Engineering 88 (2011) 1221–1224
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Performance enhancement of GaN SB-MOSFET on Si substrate using two-step growth method Dong-Seok Kim a, Tae-Hyeon Kim a, Chul-Ho Won a, Hee-Sung Kang a, Ki-Won Kim a, Ki-Sik Im a, Yong Soo Lee a, Sung-Ho Hahm a, Jung-Hee Lee a,⇑, Jae-Hoon Lee b, Jong-Bong Ha c, Youngho Bae d, Sorin Cristoloveanu e a
School of Electrical Engineering & Computer Science, Kyungpook National University, Daegu 702-701, Republic of Korea GaN Power Research Group, Samsung LED Co., Ltd., Suwon 443-743, Republic of Korea Material and Device Research Center, SAIT, Samsung Electronics Co., Ltd., Yongin 446-712, Republic of Korea d Department of Electronics Engineering, Uiduk University, Gyeongju 780-713, Republic of Korea e IMEP, Grenoble Polytechnic Institute, Minatec, Grenoble, France b c
a r t i c l e
i n f o
Article history: Available online 30 March 2011 Keywords: Normally-off GaN SB-MOSFET Two-step growth MOCVD ITO Si(1 1 1)
a b s t r a c t We have grown high quality GaN layers on (1 1 1)-oriented silicon substrate using a two-step growth method and fabricated high-performance normally-off n-channel GaN Schottky-barrier MOSFET (SBMOSFET). Indium-tin-oxide (ITO) was used as Schottky-barrier contact for source and drain (S/D) because the work function of ITO is close to the electron affinity of GaN. Due to enhanced crystalline quality and reduced surface roughness of GaN layer grown by two-step process, the fabricated device exhibited much improved performances: sufficiently high threshold voltage of 3.75 V, subthreshold slope of 171 mV/dec, low specific on-resistance of 9.98 mX cm2, and very high field-effect mobility of 271 cm2/V s. This is the highest mobility value among the GaN MOSFETs ever reported so far. Ó 2011 Elsevier B.V. All rights reserved.
1. Introduction Gallium nitride (GaN) is very attractive material for high power, high frequency, and high temperature applications due to its superior properties [1]. AlGaN/GaN-based heterojunction field-effect transistors (HFETs) have already exhibited excellent device performances mainly due to the large polarization-induced two-dimensional electron gas (2-DEG) formed at the heterojunction. However, the device operation was mostly limited to normallyon mode, because the high 2DEG density makes it very difficult for the device to be operated in normally-off mode. For power electronic applications, the normally-off operation is needed to simplify the design of driving circuit and to reduce the power loss during switching. The normally-off device requires high threshold voltage above 3 V to prevent mis-operation caused by switching noise and high drain current needed for high switching speed. Recently, many efforts have been dedicated to developing normally-off devices such as gate injection transistor (GIT) [2], AlGaN/GaN HFET with F-ion treatment [3], metal-oxide-semiconductor field effect transistors (MOSFETs) [4,5], and AlGaN/GaNbased MOSFETs with appropriate recess etching in the gate region ⇑ Corresponding author. E-mail address: [email protected] (J.-H. Lee). 0167-9317/$ - see front matter Ó 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2011.03.119
[6–8]. GIT and AlGaN/GaN HFET with F-ion treatment show a high drain current but low threshold voltage, while MOSFETs exhibit a higher threshold voltage, large gate voltage swing, and better switching noise performance [9]; however, the drain current and transconductance are low. AlGaN/GaN-based MOSFETs with recess etching in gate region have relatively high threshold voltage and drain current, but they suffer from the decreased channel mobility due to increased interface scattering. The recess etching process increases the surface roughness and generates process-induced damage in the channel region, which significantly decrease the on-current of the devices. The design of source and drain (S/D) is also very important because it determines the on-current of the device. Ion-implanted or epitaxially re-grown n+-layer was usually used as S/D [10,11]. A Schottky-barrier S/D is attractive solution for achieving the normally-off operation because it excludes the use of high cost S/D ion-implantation process with very high temperature activation and complex re-growth process. Si substrate is one of the promising candidates for growing the GaN layers due to lower cost and larger size compared to sapphire and SiC substrates. However, the growth of GaN layer on Si substrate is made difficult by the large difference in lattice constant and thermal expansion coefficient between GaN and Si materials. The growth of optimized buffer layer structure is very important
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Fig. 3. The mechanism of dislocation reduction by two-step growth method.
2. Experiment
Fig. 1. (a) Cross-sectional schematic of fabricated SB-MOSFETs with ITO source and drain contact. (b) The fabrication process flow of SB-MOSFETs.
to obtain a crack-free thicker GaN layer [12]. Additional dislocation reduction technique in combination with optimized buffer layer structure is required [13–15], since the buffer layer itself cannot ensure the growth of high quality epitaxial GaN film with low dislocation density. In this work, we propose a two-step growth method for high quality GaN layer on Si substrate and demonstrate the performance enhancement of GaN SB-MOSFET on Si substrate. The field-effect mobility is the highest value among the GaN MOSFETs ever reported to the best of our knowledge.
The GaN layer was grown on Si(1 1 1) substrate by the closecoupled metalorganic chemical vapor deposition (MOCVD) using trimethylgallium (TMGa), trimethylaluminium (TMAl), and ammonia (NH3) as precursors for Ga, Al, and N, respectively. First, a 150 nm-thick high-temperature AlN buffer layer was grown, followed by step-graded AlGaN buffer layers to compensate the large tensile stress [16]. The buffer layers consisted of four stacks of AlGaN layers with different Al mole fractions from 73% to 12%. Finally, the 0.7 lm-thick active GaN layer with crack-free and mirror-like surface was grown by using either the one-step or two-step growth method. The GaN layer by one-step method was grown at 100 torr with low V/III ratio (under 10,000). The GaN layer by two-step method was grown at 300 with high V/III ratio (over 10,000) and 100 torr with low V/III ratio for 1st (300 Å) and 2nd GaN layer (6700 Å), respectively. Fig. 1(a) shows the schematic of a fabricated normally-off GaN SB-MOSFET. For Schottky-barrier S/D contact, a 1000 Å-thick ITO film was deposited by RF sputtering system. The detailed fabrication process is illustrated in Fig. 1(b). The gate length and width of fabricated device were 10 and 100 lm, respectively. 3. Results and discussion The FWHM of (0 0 2) and (1 0 2) X-ray rocking curves of GaN layer grown by two-step method is improved from 1067/2712 arcsec (corresponding to one-step growth method) to 891/ 2001 arcsec, as shown in Fig. 2. The surface roughness of GaN layer grown by two-step method, obtained from 2 2 lm2 scan area, is also improved from 0.78 to 0.45 nm. It is believed that the 1st GaN layer grown under high pressure with high V/III ratio results in three-dimensional islands which are effective in blocking dislocation propagation and promoting coalescence of 2nd GaN layer.
Fig. 2. The (0 0 2)/(1 0 2) X-ray rocking curves of GaN layer grown by one-step and two-step growth methods.
D.-S. Kim et al. / Microelectronic Engineering 88 (2011) 1221–1224
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Fig. 4. Cross-sectional (0 0 0 2) two-beam bright-field TEM images of (a) one-step growth method and (b) two-step growth method. The reduction of dislocations in GaN layer by two-step growth method is visibly confirmed.
Fig. 6. DC characteristics of the fabricated GaN MOSFETs; (a) output IDS–VDS characteristics and (b) transfer IDS–VGS characteristics and corresponding transconductance curves in the saturation region at VDS = 7 V.
Fig. 5. Ideal energy band diagram along the channel, from source to drain, for normally-off operation of the highly resistive n-type GaN-based SB-MOSFET proposed in this work. Before VGS and VDS biasing, the device is in off-state (a). After VGS and VDS biasing, the channel of MOSFET is inverted (b), and then, the device is in operation mode (c).
Therefore, a high quality GaN layer with smooth surface can be obtained by the two-step growth. Fig. 3 shows the mechanism of dislocation reduction using this two-step growth method. The cross-sectional (0 0 0 2) two-beam bright-field TEM images after one-step and two-step growth methods are shown in Fig. 4(a) and (b), respectively. They clearly demonstrate that the two-step growth effectively reduces the propagation of dislocations into the active GaN layer. Fig. 5 illustrates the energy band diagram along the source and drain for normally-off operation of GaN-based SB-MOSFET [17].
The work function of ITO, used for S/D electrode, is 4.3 eV that is close to the electron affinity of GaN (4.1 eV) and results in only a small conduction band barrier for electrons. This low barrier ensures easy electron injection from the source into the channel. Fig. 6 shows the comparison of DC characteristics of SB-MOSFETs processed with one-step and two-step growth methods. With two-step growth method, the device performance is greatly enhanced as demonstrated in the figure. The saturation drain current is 54 mA/mm at VGS = 7 V and maximum extrinsic transconductance is 20 mS/mm at VDS = 7 V for the two-step grown device. This represents an enhancement of about 2.5 times compared with device fabricated from one-step growth method, as shown in Fig. 6(b). The transfer characteristics measured in the linear region (at VDS = 0.5 V) is shown in Fig. 7. Both devices fabricated by one-step and two-step growth methods exhibit normally-off operation with high threshold voltages of 3.8 V. The subthreshold slope (SS) for devices with one-step and two-step growth method are 576 and 171 mV/dec, respectively. The interface trap density (Dit) extracted from the SS shows that two-step growth method reduces five folds the Dit value, from 6.1 1012 to 1.2 1012/cm2 eV. The interface trap density at the SiO2/GaN interface of the device with two-step growth method without annealing is comparable with other reported values obtained after annealing [18]. This is a consequence of improved surface roughness in our devices. The trap density can be possibly further reduced by optimizing the annealing conditions of SiO2 gate oxide. The field-effect mobility extracted from the maximum transconductance of linear transfer characteristics is improved from 109 (one-step growth method) to 271 cm2/V s for two-step growth method. This latter value is the highest mobility ever reported to best of our knowledge [7,11,19–21]. The on/off current ratio with
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uration drain current of 54 mA/mm, maximum extrinsic transconductance of 20 mS/mm, subthreshold slope of 171 mV/dec, and low specific on-resistance of 9.98 mX cm2. The extracted electron mobility is 271 cm2/V s which stands as a record value. Acknowledgements This work was supported by 2008 Brain Korea 21 (BK21), the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (Nos. M10600000273-06J0000-27310 and 2010-0001877), ‘‘Survey of high efficiency power devices and inverter system for power grid’’ project of Korea Ministry of Knowledge Economy, and WCU (World Class University) program through the Korea Science and Engineering Foundation funded by the Ministry of Education, Science and Technology (R33-10055). The authors acknowledge Prof. H.K. Cho at Sungkyunkwan University for TEM work. References
Fig. 7. Transfer IDS–VGS and transconductance characteristics in the linear region at VDS = 0.5 V; (a) fabricated SB-MOSFET using two-step growth method; (b) comparison of linear and logarithmical characteristics of SB-MOSFET fabricated with onestep and two-step growth methods.
two-step growth method is also approximately one order of magnitude higher than that with one-step growth method, as shown in Fig. 7. Also, the specific on-resistance of fabricated device with two-step growth method is 9.98 mX cm2, about 2 times lower than that of one-step growth method. It is concluded that the improved crystalline quality and surface roughness of the two-step grown GaN layer enhance remarkably the device performances. 4. Conclusion We have grown high quality GaN layers using a two-step growth method and fabricated normally-off GaN SB-MOSFETs with ITO S/D. The proposed device shows excellent DC characteristics, due to improved crystal quality with smooth surface, such as sat-
[1] T.P. Chow, Proc. Mater. Res. Soc. Symp. (2000) T1.1. [2] Y. Uemoto, M. Hikita, H. Ueno, H. Matsuo, H. Ishida, M. Yanagihara, T. Ueda, T. Tanaka, D. Ueda, IEEE Trans. Electron. Devices 54 (2007) 3393. [3] Y. Cai, Y. Zhou, K.J. Chen, K.M. Lau, IEEE Electron. Device Lett. 26 (2005) 435. [4] Y. Irokawa, Y. Nakano, M. Ishiko, T. Kachi, J. Kim, F. Ren, Appl. Phys. Lett. 84 (2004) 2919. [5] T. Nomura, H. Kambayashi, Y. Niiyama, S. Otomo, S. Yoshida, Solid State Electron. 52 (2008) 150. [6] T. Oka, T. Nozawa, IEEE Electron. Device Lett. 29 (2008) 668. [7] K.S. Im, J.B. Ha, K.W. Kim, J.S. Lee, D.S. Kim, S.H. Hahm, J.H. Lee, IEEE Electron. Device Lett. 31 (2010) 192. [8] D.S. Kim, J.B. Ha, S.N. Kim, E.H. Kwak, S.G. Lee, H.S. Kang, J.S. Lee, K.S. Im, K.W. Kim, J.H. Lee, in: Proc. Int. Symp. Power Semicond. Devices and ICs, 2010, pp. 229. [9] T. Kachi, in: Proc. IEEE Compd. Semicond. IC Symp. Tech. Dig., 2007, pp. 13. [10] H. Yu, L. MacCarthy, S. Rajan, S. Keller, S.P. DenBaars, J. Speck, U.K. Mishra, IEEE Electron. Device Lett. 26 (2005) 283. [11] H. Kambayashi, Y. Niiyama, S. Ootomo, T. Nomura, M. Iwami, Y. Satoh, S. Kato, S. Yoshida, IEEE Electron. Device Lett. 28 (2007) 1077. [12] N. Ikeda, Y. Niiyama, H. Kambayashi, Y. Sato, T. Nomura, S. Kato, S. Yoshida, Proc. IEEE 98 (2010) 1151. [13] K. Cheng, M. Leys, S. Degroote, M. Germain, G. Borghs, Appl. Phys. Lett. 92 (2008) 192111. [14] M. Häberlen, D. Zhu, C. McAleese, T. Zhu, M.J. Kappers, C.J. Hemphreys, Phys. Status Solidi B 247 (2010) 1753. [15] J.H. Lee, J.H. Lee, H.I. Cho, U.S. Patent No. 739064 B2, 15 January 2008. [16] K. Cheng, M. Leys, S. Degroote, B.V. Daele, S. Boeykens, J. Derluyn, M. Germain, G.V. Tendeloo, J. Engelen, G. Borghs, J. Electron. Mater. 35 (2006) 592. [17] H.B. Lee, H.I. Cho, H.S. An, Y.H. Bae, M.B. Lee, J.H. Lee, S.H. Hahm, IEEE Electron. Device Lett. 27 (2006) 81. [18] Y. Niiyama, S. Ootomo, H. Kambayashi, N. Ikeda, T. Nomura, S. Kato, in: Proc. IEEE Compd. Semicond. IC Symp. Tech. Dig., 2009. [19] K. Matocha, T.P. Chow, R.J. Gutmann, IEEE Trans. Electron. Devices 52 (2005) 6. [20] W. Huang, T. Khan, T.P. Chow, IEEE Electron. Device Lett. 27 (2006) 796. [21] Y. Niiyama, H. Kambayashi, S. Ootomo, T. Nomura, S. Yoshida, T.P. Chow, Jpn. J. Appl. Phys. 47 (2008) 7128.
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Performance enhancement of GaN SB-MOSFET on Si substrate using two-step growth method Dong-Seok Kim a, Tae-Hyeon Kim a, Chul-Ho Won a, Hee-Sung Kang a, Ki-Won Kim a, Ki-Sik Im a, Yong Soo Lee a, Sung-Ho Hahm a, Jung-Hee Lee a,⇑, Jae-Hoon Lee b, Jong-Bong Ha c, Youngho Bae d, Sorin Cristoloveanu e a
School of Electrical Engineering & Computer Science, Kyungpook National University, Daegu 702-701, Republic of Korea GaN Power Research Group, Samsung LED Co., Ltd., Suwon 443-743, Republic of Korea Material and Device Research Center, SAIT, Samsung Electronics Co., Ltd., Yongin 446-712, Republic of Korea d Department of Electronics Engineering, Uiduk University, Gyeongju 780-713, Republic of Korea e IMEP, Grenoble Polytechnic Institute, Minatec, Grenoble, France b c
a r t i c l e
i n f o
Article history: Available online 30 March 2011 Keywords: Normally-off GaN SB-MOSFET Two-step growth MOCVD ITO Si(1 1 1)
a b s t r a c t We have grown high quality GaN layers on (1 1 1)-oriented silicon substrate using a two-step growth method and fabricated high-performance normally-off n-channel GaN Schottky-barrier MOSFET (SBMOSFET). Indium-tin-oxide (ITO) was used as Schottky-barrier contact for source and drain (S/D) because the work function of ITO is close to the electron affinity of GaN. Due to enhanced crystalline quality and reduced surface roughness of GaN layer grown by two-step process, the fabricated device exhibited much improved performances: sufficiently high threshold voltage of 3.75 V, subthreshold slope of 171 mV/dec, low specific on-resistance of 9.98 mX cm2, and very high field-effect mobility of 271 cm2/V s. This is the highest mobility value among the GaN MOSFETs ever reported so far. Ó 2011 Elsevier B.V. All rights reserved.
1. Introduction Gallium nitride (GaN) is very attractive material for high power, high frequency, and high temperature applications due to its superior properties [1]. AlGaN/GaN-based heterojunction field-effect transistors (HFETs) have already exhibited excellent device performances mainly due to the large polarization-induced two-dimensional electron gas (2-DEG) formed at the heterojunction. However, the device operation was mostly limited to normallyon mode, because the high 2DEG density makes it very difficult for the device to be operated in normally-off mode. For power electronic applications, the normally-off operation is needed to simplify the design of driving circuit and to reduce the power loss during switching. The normally-off device requires high threshold voltage above 3 V to prevent mis-operation caused by switching noise and high drain current needed for high switching speed. Recently, many efforts have been dedicated to developing normally-off devices such as gate injection transistor (GIT) [2], AlGaN/GaN HFET with F-ion treatment [3], metal-oxide-semiconductor field effect transistors (MOSFETs) [4,5], and AlGaN/GaNbased MOSFETs with appropriate recess etching in the gate region ⇑ Corresponding author. E-mail address: [email protected] (J.-H. Lee). 0167-9317/$ - see front matter Ó 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2011.03.119
[6–8]. GIT and AlGaN/GaN HFET with F-ion treatment show a high drain current but low threshold voltage, while MOSFETs exhibit a higher threshold voltage, large gate voltage swing, and better switching noise performance [9]; however, the drain current and transconductance are low. AlGaN/GaN-based MOSFETs with recess etching in gate region have relatively high threshold voltage and drain current, but they suffer from the decreased channel mobility due to increased interface scattering. The recess etching process increases the surface roughness and generates process-induced damage in the channel region, which significantly decrease the on-current of the devices. The design of source and drain (S/D) is also very important because it determines the on-current of the device. Ion-implanted or epitaxially re-grown n+-layer was usually used as S/D [10,11]. A Schottky-barrier S/D is attractive solution for achieving the normally-off operation because it excludes the use of high cost S/D ion-implantation process with very high temperature activation and complex re-growth process. Si substrate is one of the promising candidates for growing the GaN layers due to lower cost and larger size compared to sapphire and SiC substrates. However, the growth of GaN layer on Si substrate is made difficult by the large difference in lattice constant and thermal expansion coefficient between GaN and Si materials. The growth of optimized buffer layer structure is very important
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Fig. 3. The mechanism of dislocation reduction by two-step growth method.
2. Experiment
Fig. 1. (a) Cross-sectional schematic of fabricated SB-MOSFETs with ITO source and drain contact. (b) The fabrication process flow of SB-MOSFETs.
to obtain a crack-free thicker GaN layer [12]. Additional dislocation reduction technique in combination with optimized buffer layer structure is required [13–15], since the buffer layer itself cannot ensure the growth of high quality epitaxial GaN film with low dislocation density. In this work, we propose a two-step growth method for high quality GaN layer on Si substrate and demonstrate the performance enhancement of GaN SB-MOSFET on Si substrate. The field-effect mobility is the highest value among the GaN MOSFETs ever reported to the best of our knowledge.
The GaN layer was grown on Si(1 1 1) substrate by the closecoupled metalorganic chemical vapor deposition (MOCVD) using trimethylgallium (TMGa), trimethylaluminium (TMAl), and ammonia (NH3) as precursors for Ga, Al, and N, respectively. First, a 150 nm-thick high-temperature AlN buffer layer was grown, followed by step-graded AlGaN buffer layers to compensate the large tensile stress [16]. The buffer layers consisted of four stacks of AlGaN layers with different Al mole fractions from 73% to 12%. Finally, the 0.7 lm-thick active GaN layer with crack-free and mirror-like surface was grown by using either the one-step or two-step growth method. The GaN layer by one-step method was grown at 100 torr with low V/III ratio (under 10,000). The GaN layer by two-step method was grown at 300 with high V/III ratio (over 10,000) and 100 torr with low V/III ratio for 1st (300 Å) and 2nd GaN layer (6700 Å), respectively. Fig. 1(a) shows the schematic of a fabricated normally-off GaN SB-MOSFET. For Schottky-barrier S/D contact, a 1000 Å-thick ITO film was deposited by RF sputtering system. The detailed fabrication process is illustrated in Fig. 1(b). The gate length and width of fabricated device were 10 and 100 lm, respectively. 3. Results and discussion The FWHM of (0 0 2) and (1 0 2) X-ray rocking curves of GaN layer grown by two-step method is improved from 1067/2712 arcsec (corresponding to one-step growth method) to 891/ 2001 arcsec, as shown in Fig. 2. The surface roughness of GaN layer grown by two-step method, obtained from 2 2 lm2 scan area, is also improved from 0.78 to 0.45 nm. It is believed that the 1st GaN layer grown under high pressure with high V/III ratio results in three-dimensional islands which are effective in blocking dislocation propagation and promoting coalescence of 2nd GaN layer.
Fig. 2. The (0 0 2)/(1 0 2) X-ray rocking curves of GaN layer grown by one-step and two-step growth methods.
D.-S. Kim et al. / Microelectronic Engineering 88 (2011) 1221–1224
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Fig. 4. Cross-sectional (0 0 0 2) two-beam bright-field TEM images of (a) one-step growth method and (b) two-step growth method. The reduction of dislocations in GaN layer by two-step growth method is visibly confirmed.
Fig. 6. DC characteristics of the fabricated GaN MOSFETs; (a) output IDS–VDS characteristics and (b) transfer IDS–VGS characteristics and corresponding transconductance curves in the saturation region at VDS = 7 V.
Fig. 5. Ideal energy band diagram along the channel, from source to drain, for normally-off operation of the highly resistive n-type GaN-based SB-MOSFET proposed in this work. Before VGS and VDS biasing, the device is in off-state (a). After VGS and VDS biasing, the channel of MOSFET is inverted (b), and then, the device is in operation mode (c).
Therefore, a high quality GaN layer with smooth surface can be obtained by the two-step growth. Fig. 3 shows the mechanism of dislocation reduction using this two-step growth method. The cross-sectional (0 0 0 2) two-beam bright-field TEM images after one-step and two-step growth methods are shown in Fig. 4(a) and (b), respectively. They clearly demonstrate that the two-step growth effectively reduces the propagation of dislocations into the active GaN layer. Fig. 5 illustrates the energy band diagram along the source and drain for normally-off operation of GaN-based SB-MOSFET [17].
The work function of ITO, used for S/D electrode, is 4.3 eV that is close to the electron affinity of GaN (4.1 eV) and results in only a small conduction band barrier for electrons. This low barrier ensures easy electron injection from the source into the channel. Fig. 6 shows the comparison of DC characteristics of SB-MOSFETs processed with one-step and two-step growth methods. With two-step growth method, the device performance is greatly enhanced as demonstrated in the figure. The saturation drain current is 54 mA/mm at VGS = 7 V and maximum extrinsic transconductance is 20 mS/mm at VDS = 7 V for the two-step grown device. This represents an enhancement of about 2.5 times compared with device fabricated from one-step growth method, as shown in Fig. 6(b). The transfer characteristics measured in the linear region (at VDS = 0.5 V) is shown in Fig. 7. Both devices fabricated by one-step and two-step growth methods exhibit normally-off operation with high threshold voltages of 3.8 V. The subthreshold slope (SS) for devices with one-step and two-step growth method are 576 and 171 mV/dec, respectively. The interface trap density (Dit) extracted from the SS shows that two-step growth method reduces five folds the Dit value, from 6.1 1012 to 1.2 1012/cm2 eV. The interface trap density at the SiO2/GaN interface of the device with two-step growth method without annealing is comparable with other reported values obtained after annealing [18]. This is a consequence of improved surface roughness in our devices. The trap density can be possibly further reduced by optimizing the annealing conditions of SiO2 gate oxide. The field-effect mobility extracted from the maximum transconductance of linear transfer characteristics is improved from 109 (one-step growth method) to 271 cm2/V s for two-step growth method. This latter value is the highest mobility ever reported to best of our knowledge [7,11,19–21]. The on/off current ratio with
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uration drain current of 54 mA/mm, maximum extrinsic transconductance of 20 mS/mm, subthreshold slope of 171 mV/dec, and low specific on-resistance of 9.98 mX cm2. The extracted electron mobility is 271 cm2/V s which stands as a record value. Acknowledgements This work was supported by 2008 Brain Korea 21 (BK21), the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (Nos. M10600000273-06J0000-27310 and 2010-0001877), ‘‘Survey of high efficiency power devices and inverter system for power grid’’ project of Korea Ministry of Knowledge Economy, and WCU (World Class University) program through the Korea Science and Engineering Foundation funded by the Ministry of Education, Science and Technology (R33-10055). The authors acknowledge Prof. H.K. Cho at Sungkyunkwan University for TEM work. References
Fig. 7. Transfer IDS–VGS and transconductance characteristics in the linear region at VDS = 0.5 V; (a) fabricated SB-MOSFET using two-step growth method; (b) comparison of linear and logarithmical characteristics of SB-MOSFET fabricated with onestep and two-step growth methods.
two-step growth method is also approximately one order of magnitude higher than that with one-step growth method, as shown in Fig. 7. Also, the specific on-resistance of fabricated device with two-step growth method is 9.98 mX cm2, about 2 times lower than that of one-step growth method. It is concluded that the improved crystalline quality and surface roughness of the two-step grown GaN layer enhance remarkably the device performances. 4. Conclusion We have grown high quality GaN layers using a two-step growth method and fabricated normally-off GaN SB-MOSFETs with ITO S/D. The proposed device shows excellent DC characteristics, due to improved crystal quality with smooth surface, such as sat-
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