- Email: [email protected]
pentacene interface modification using an electrostatically assembled PDDA monolayer
Solid-State Electronics 50 (2006) 129–133 www.elsevier.com/locate/sse
Performance improvement of organic thin film transistors by SiO2/pentacene interface modification using an electrostatically assembled PDDA monolayer Mo Zhu, Kody Varahramyan
*
Institute for Micromanufacturing, Louisiana Tech University, Ruston, LA 71272, USA Received 9 August 2004; received in revised form 26 October 2005; accepted 31 October 2005 Available online 27 December 2005
The review of this paper was arranged by Prof. S. Cristoloveanu
Abstract Pentacene-based organic thin film transistors have been fabricated with and without the presence of a modifying monolayer at the interface between the silicon dioxide insulator and the organic semiconductor. The monolayer consists of poly(dimethyldiallylammonium chloride) (PDDA), and is deposited by electrostatic self-assembly. The interface modification by the PDDA monolayer has resulted in improved device performance, including 33% higher effective hole mobility, 42% lower threshold voltage, about 50% lower subthreshold slope, and 100% higher on/off ratio. Scanning electron microscopy (SEM) profiles reveal the morphology of pentacene is affected by the insertion of the PDDA monolayer. The presence of this monolayer appears to improve the interface characteristics of the deposited pentacene layer, resulting in better thin film transistors. 2005 Elsevier Ltd. All rights reserved. Keywords: Pentacene thin film transistors (TFTs); Poly(dimethyldiallylammonium chloride) (PDDA); Electrostatically assembled PDDA monolayer
1. Introduction Organic microelectronics and optoelectronics have attracted extensive attention for their flexibility and largearea processability [1,2]. Pentacene, as one of the most investigated organic semiconductors, has been used to fabricate microelectronic devices, such as Schottky diodes [3,4], thin film transistors (TFTs) [5–7], and integrated circuits [8,9]. In addition to using advanced deposition methods [7] to improve the growth quality of pentacene thin films, various approaches may be employed to improve the characteristics of the insulator/pentacene interface and source/ drain contacts. Pentacene has been grown on a variety of substrates [5,10–13] and at different substrate temperatures
*
Corresponding author. Tel.: +1 318 2575107; fax: +1 318 2575104. E-mail address: [email protected] (K. Varahramyan).
0038-1101/$ - see front matter 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2005.10.040
[14,6,15]; buffer layers have been used to modify an adjoining insulator surface [16,17]; or a thermally grown SiO2 surface has been treated by oxygen plasma in [18]. Jackson et al., have used octadecyltrichlorosilane (OTS), a self-organizing material, to form a well-ordered monolayer on thermally grown SiO2 [19]. While Kymissis et al., have modified the surface potential of electrode contact by self-assembled 1-hexadecanethiol monolayer [20]. Various applications of self-assembled monolayer (SAM) in electronic devices have been reported, as in Refs. [21,22]. Due to the importance of the insulator/semiconductor interface in field effect transistors, it is necessary to investigate the effect of the interface properties on the device characteristics. In this work, we propose an electrostatic assembly method to assist in the surface and interface modification. In our investigation, an electrostatically assembled monolayer of PDDA is deposited on silicon dioxide (SiO2), before the deposition of pentacene. The
130
M. Zhu, K. Varahramyan / Solid-State Electronics 50 (2006) 129–133
SiO2/pentacene interface is modified by this process. The change of the interface affects the growth and morphology of pentacene. These changes have been observed to lead to significant improvements in the performance of the resulted field effect transistors. 2. Experimental A bottom-contact structure has been adopted for the fabricated devices, as schematically shown in Fig. 1. First, heavily doped n-type silicon wafers are prepared and cleaned, for use as substrate, as well as gate electrode. Second, 100 nm-thick layer of SiO2 is grown on silicon by dry thermal oxidation, and serving as gate dielectric material. Subsequently, a layer of Ti/Au (30 nm/80 nm) is deposited by sputtering (Ti in contact with the oxide), followed by photolithography and wet etching, to pattern the Au/Ti source and drain (S/D) contacts. The wafers are then separated into two groups. Group One, labeled as ‘‘without PDDA,’’ is ready for pentacene evaporation. Group Two is first treated with sulfuric acid and hydrogen peroxide solution (3:7) at 70 C for 3 min, before getting immersed in aqueous poly(dimethyldiallylammonium chloride) (PDDA, MW 200,000, Sigma) solution at a concentration of 15 mg/mL and pH of 8 for 20 min. PDDA is the positively charged polyion, while the SiO2 surface is hydrophilic and is negatively charged
after the treatment by the sulfuric acid and hydrogen peroxide solution [23–25]. During the immersion, a monolayer of PDDA is self-assembled through the electrostatic interaction and hydrogen bonding between PDDA nanoparticles and the SiO2 surface, as well as good adhesion of PDDA to a free surface [26]. Actually, PDDA is one of the commonly used materials to form precursor layers in layer-by-layer (LBL) self-assembly technique [27–30]. When this monolayer is built up, electrostatic self-assembly will stop accordingly. The thickness of the adsorbed PDDA monolayer is in precision of 1–2 nm and monitored by the Quartz Crystal Microbalance (QCM, USI-System, Japan) technique [25]. Then, Group Two is labeled as ‘‘with PDDA’’ and is ready for pentacene evaporation. Pentacene (Aldrich, without purification) is then deposited on the channel (75 lm length and 1000 lm width) and source/drain regions by thermal evaporation, at 1 · 106 Torr, through shadow mask, for both groups, at ˚ /s in room temperature for a deposition rate of about 6 A the substrates. The thickness of the pentacene thin film is 300 nm, as measured by a Tencor Surface Profiler. The fabricated devices are electrically tested with a Keithley Test System, at atmospheric ambient condition. The output and transfer characteristics of the fabricated pentacene TFTs have been measured for both sets of devices (i.e., with and without the PDDA monolayer). 3. Results and discussion
Fig. 1. Schematic structure of fabricated pentacene TFTs.
The SEM micrographs in Fig. 2(a) and (b) show the surface profile of pentacene, after deposition, on TFTs without and with the PDDA monolayer, respectively. The insertion of the PDDA monolayer appears to affect the growth of pentacene, resulting in different grain size. The surface profile without the PDDA monolayer shows irregular grain size, with clear grain boundaries (Fig. 2(a)), caused by the untreated surface. The presence of the PDDA monolayer, seems to have noticeably improved the surface condition, yielding a better surface
Fig. 2. SEM surface profile of pentacene after deposition on TFTs (a) without and (b) with electrostatically assembled monolayer of PDDA.
M. Zhu, K. Varahramyan / Solid-State Electronics 50 (2006) 129–133
profile for pentacene (Fig. 2(b)), with smoother grains, and more uniform grain size. Electrical measurements of the fabricated devices reveal that by adding a layer of electrostatically assembled PDDA at the channel/insulator interface, the device performance becomes significantly improved. The transfer characteristics (Ids–Vgs) of devices with and without PDDA are compared in Fig. 3, and the output characteristics (Ids–Vds) of both devices are provided in Fig. 4. Generally the following two conventional equations for inorganic transistors are employed to describe the behavior of organic transistors [31,32]: wC i V ds I ds ¼ l V gs V th ð1Þ V ds ðLinear-regionÞ; L 2 wC i 2 lðV gs V th Þ ðSaturation-regionÞ; I ds ¼ ð2Þ 2L where W and L are the channel width and length respectively, l is the carrier mobility for n-channel device, Ci is the capacitance per unit area of the dielectric layer, and Vth is the threshold voltage.
Fig. 3. Comparison of the transfer characteristics of pentacene TFTs without (squares) and with (stars) electrostatically assembled monolayer of PDDA.
131
Table 1 Comparison of the pentacene TFTs without and with electrostatically assembled monolayer of PDDAa
Without PDDA With PDDA
Vth (V)
leff (cm2/V s) S (V/decade) On/off ratio
4.20
0.015
2.45 (42%) 0.020 (33%)
4
104
2 (50%)
2 · 104 (100%)
a
Extracted from Ids–Vgs at Vds = 60 V. Mobility is calculated by Eq. (2) from Ids–Vgs curves at Vds = 60 V and Vgs = 40 V.
Based on the above equations and experimental data, the device parameters for both groups of pentacene TFTs have been extracted and compared, as demonstrated in Table 1. The extracted parameters include threshold voltage (Vth) by the linear extrapolation method from the Ids–Vgs data at saturation region (Vds = 60 V), effective hole mobility (leff) from the Ids–Vgs data at saturation region (Vds = 60 V and Vgs = 40 V), subthreshold slope (S), and on/off ratio. From Table 1 it can be seen that the SiO2/pentacene interface has been successfully improved by the presence of the PDDA monolayer. Particularly, the effective hole mobility leff increases from 0.015 cm2/V s to 0.02 cm2/V s (by 33%), the threshold voltage Vth decreases from 4.2 V to 2.45 V (by 42%), the subthreshold slope S is noticeably improved from 4 V/decade to 2 V/decade (by 50%), and the on/off ratio is improved from 1 · 104 to 2 · 104 (by 100%). The discrepancy exists between Figs. 3 and 4, which may be introduced in the measurement and need further investigation. Similar to the conventional insulated gate field effect transistors, in organic thin film transistors, the insulator/ semiconductor interface plays an important role on the device parameters, including mobility and subthreshold slope. It is generally known that mobility is improved by reduction in surface scattering mechanisms that may occur in the presence of a smoother interface. The presence of charge trapping [33] can influence the device subthreshold slope. Specifically, the subthreshold slope affected by interface traps can be expressed as [34],
-12 With PDDA:Vgs = -40 V
Drain Current (µA)
With PDDA:Vgs = -30 V
-8
and Without PDDA: Vgs = -40 V
-6
With PDDA:Vgs = -20 V
-4
With PDDA:Vgs = -10 V Vgs = -30 V
-2 0
Vgs = -20 V Vgs = -10 V
0
-10
-20 -30 -40 Drain Voltage (V)
-50
1 þ ðC S þ C it Þ=C i ; 1 þ C S =C i
ð3Þ
kT CS ln 10 1 þ ; q Ci
ð4Þ
S ¼ S0
-10
-60
Fig. 4. Comparison of the output characteristics of the pentacene TFTs without (solid) and with (dashed) electrostatically assembled monolayer of PDDA.
S0 ¼
where S0 is the subthreshold slope without interface traps, CS is the capacitance associated with the space charge layer in the organic semiconductor, Ci is the capacitance of the insulator, and Cit is the capacitance associated with the interface traps, and which is in parallel with CS. We assume here that the SiO2/pentacene interface has reduced interface traps after the treatment by the electrostatically assembled PDDA monolayer. In the device with PDDA monolayer, the insulator capacitance Ci may be substituted by Ci and
132
M. Zhu, K. Varahramyan / Solid-State Electronics 50 (2006) 129–133
the series capacitance of the PDDA monolayer, CPDDA. Since the PDDA monolayer is very thin (1–2 nm compared to SiO2 100 nm) and its dielectric constant is supposed to be very high (normally ten times higher for polyion films than thermally grown SiO2 [27,35]), the total capacitance of Ci and CPDDA is almost unchanged or about equal to Ci. Therefore Cit can be calculated by Eqs. (3) and (4), and the density of interface traps can be approximated by Ci12 2 eV1 t = eNit [33]. An effective density of 7.0 · 10 cm is calculated for the device without electrostatically assembled monolayer of PDDA. Interface traps show similar negative influences on effective hole mobility, and on/off ratio in thin film transistors. For the device modified by the PDDA monolayer, these parameters are improved. At the SiO2/pentacene interface, the PDDA monolayer appears to reduce the physical defects and create a smoother interface. 4. Conclusions The results presented in this paper show that an electrostatically assembled monolayer of PDDA can be used to modify and improve the interface between the insulator and active material in thin film transistors. In this work, the insulator and active material consisted of silicon dioxide and pentacene, respectively. By the immersion in the aqueous solution, PDDA nanoparticles form an ordered monolayer on SiO2 through electrostatic self-assembly. Introduction of the PDDA monolayer at the SiO2/pentacene interface has resulted in improved device performance, including higher effective mobility and lower subthreshold slope. Acknowledgements The authors acknowledge the laboratory and technical resources provided by the Institute for Micromanufacturing for the realization of this work. They also thank Dr. Yuri Lvov and Ms. Jingshi Shi for their assistance with the PDDA monolayer assembly. References [1] Angelopoulos M. Conducting polymers in microelectronics. IBM J Res Dev 2001;45(1):57–75. [2] Dimitrakopoulos CD, Malenfant PRL. Organic thin film transistors for large area electronics. Adv Mater 2002;14(2):99–117. [3] Lee YS, Park JH, Choi JS. Electrical characteristics of pentacenebased Schottky diodes. Opt Mater 2002;21:433–7. [4] Kuniyoshi S, Naruge S, Iizuka M, Nakamura M, Kudo K, Tanaka K. Thermally stimulated current of pentacene Schottky diode. Synth Met 2000;137:895–6. [5] Lin YY, Gundlach DJ, Jackson TN, Nelson SF. Pentacene-based organic thin film transistors. IEEE Trans Electron Dev 1997;44:1325–31. [6] Lee JH, Kim SH, Kim GH, Lim SC, Lee H, Jang J, et al. Pentacene thin film transistors fabricated on plastic substrates. Synth Met 2003;139:445–51.
[7] Dimitrakopoulos CD, Brown AR, Pomp A. Molecular beam deposited thin films of pentacene for organic field effect transistor applications. J Appl Phys 1996;80:2501–8. [8] Klauk H, Gundlach DJ, Jackson TN. Fast organic thin film transistor circuits. IEEE Electron Dev Lett 1999;20:289–91. [9] Loo YL, Someya T, Baldwin KW, Bao Z, Ho P, Dodabalapur A, et al. Soft, conformable electrical contacts for organic semiconductors: high-resolution plastic circuits by lamination. PNAS 2002;99:10252–6. [10] Klauk H, Gundlach DJ, Nichols JA, Jackson TN. Pentacene organic thin-film transistors for circuit and display applications. IEEE Trans Electron Dev 1999;46(6):1258–63. [11] Klauk H, Halik M, Zschieschang U, Schmid G, Radlik W. Highmobility polymer gate dielectric pentacene thin film transistors. J Appl Phys 2002;92(9):5259–63. [12] Knipp D, Street RA, Volkel A, Ho J. Pentacene thin film transistors on inorganic dielectrics: morphology, structural properties, and electronic transport. J Appl Phys 2003;93(1):347–55. [13] Puigdollers J, Voz C, Orpella A, Quidant R, Martin I, Vetter M, et al. Pentacene thin-film transistors with polymeric gate dielectric. Org Electron 2004;5(1–3):67–71. [14] Wang G, Moses D, Heeger AJ, Zhang H-M, Narasimhan M, Demaray RE. Poly(3-hexylthiophene) field-effect transistors with high dielectric constant gate insulator. J Appl Phys 2004;95(1):316–22. [15] Chang J-W, Kim H, Kim J-K, Ju BK, Jang J, Lee Y-H. Structure and morphology of vacuum-evaporated pentacene as a function of the substrate temperature. J Korean Phys Soc 2003;42:S268–72. [16] Jin SH, Yu JS, Kim JW, Lee CA, Park B-G, Lee JD et al. PMMA buffer-layer effects on electrical performance of pentacene OTFTs with a cross-linked PVA gate insulator on a flexible substrate. Society for information display 2003 digest. Baltimore, MD, USA. 2003. p. 1088–91. [17] Uemura S, Yoshida M, Hoshino S, Kodzasa T, Kamata T. Investigation for surface modification of polymer as an insulator layer of organic FET. Thin Solid Films 2003;438–439:378–81. [18] Liang G. Organic diodes, field-effect transistors, and an inverter circuit by microfabrication techniques. PhD dissertation. Louisiana Tech University, 2003. [19] Jackson TN, Lin Y-Y, Gundlach DJ, Klauk H. Organic thin-film transistors for organic light-emitting flat-panel display backplanes. IEEE J Sel Top Quantum Electron 1998;4(1):100–4. [20] Kymissis I, Dimitrakopoulos CD, Purushothaman S. High-performance bottom electrode organic thin-film transistors. IEEE Trans Electron Dev 2001;48(6):1060–4. [21] Parviz BA, Ryan D, Whitesides GM. Using self-assembly for the fabrication of nano-scale electronic and photonic devices. IEEE Trans Adv Pack 2003;26(3):233–41. [22] Ulman A. Formation and structure of self-assembled monolayers. Chem Rev 1996;96:1533–54. [23] Chiarelli PA, Johal MS, Casson JL, Roberts JB, Robinson JM, Wang H-L. Controlled fabrication of polyelectrolyte multilayer thin films using spin-assembly. Adv Mater 2001;13:1167–71. [24] Puiso J, Lindroos S, Tamulevicius S, Leskela M, Snitka V. The influence of the pretreatment of Si substrate on the growth of PbS thin films in the SILAR technique. Solid State Phenom 2003;94:261–4. [25] Cui T, Hua F, Lvov Y. FET fabricated by layer-by-layer nanoassembly. IEEE Trans Electron Dev 2004;51(3):503–6. [26] Ai H, Fang M, Lvov Y, Mills DK, Jones SA. Applications of the electrostatic layer-by-layer self-assembly technique in biomedical engineering. In: Annual international conference of the IEEE engineering in medicine and biology proceedings, vol. 1. 2002. p. 502–3. [27] Hua F, Shi J, Lvov Y, Cui T. Fabrication and characterization of metal–oxide–semiconductor capacitor based on layer-by-layer selfassembled thin film. Nanotechnology 2003;14:453–7. [28] Cui T, Liang G, Shi J. Fabrication of pentacene organic field-effect transistors containing SiO2 nanoparticle thin film as the gate dielectric. Int Electron Dev Meeting 2003:207–10.
M. Zhu, K. Varahramyan / Solid-State Electronics 50 (2006) 129–133 [29] Shi J, Cui T. Fabrication of indium resistors by layer-by-layer nanoassembly and microlithography techniques. Solid-State Electron 2003;47:2085–8. [30] Hua F, Lvov Y, Cui T. A lithographic approach of spatial separation for multiple types of layer-by-layer self-assembled nanoparticles. Thin Solid Films 2004;449:222–5. [31] Arora. MOSFET models for VLSI circuits simulation: theory and practice. Wien, New York: Springer-Verlag; 1993.
133
[32] Horowitz G. Organic field-effect transistors. Adv Mater 1998;10:365–77. [33] Schon JH, Batlogg B. Trapping in organic field-effect transistors. J Appl Phys 2001;89(1):336–42. [34] Sze SM. Physics of semiconductor devices. New York: Wiley; 1981. [35] Tedeschi C, Mohwald H, Kirstein S. Polarity of layer-by-layer deposited polyelectrolyte films as determined by pyrene fluorescence. J Am Chem Soc 2001;123:954–60.
Performance improvement of organic thin film transistors by SiO2/pentacene interface modification using an electrostatically assembled PDDA monolayer Mo Zhu, Kody Varahramyan
*
Institute for Micromanufacturing, Louisiana Tech University, Ruston, LA 71272, USA Received 9 August 2004; received in revised form 26 October 2005; accepted 31 October 2005 Available online 27 December 2005
The review of this paper was arranged by Prof. S. Cristoloveanu
Abstract Pentacene-based organic thin film transistors have been fabricated with and without the presence of a modifying monolayer at the interface between the silicon dioxide insulator and the organic semiconductor. The monolayer consists of poly(dimethyldiallylammonium chloride) (PDDA), and is deposited by electrostatic self-assembly. The interface modification by the PDDA monolayer has resulted in improved device performance, including 33% higher effective hole mobility, 42% lower threshold voltage, about 50% lower subthreshold slope, and 100% higher on/off ratio. Scanning electron microscopy (SEM) profiles reveal the morphology of pentacene is affected by the insertion of the PDDA monolayer. The presence of this monolayer appears to improve the interface characteristics of the deposited pentacene layer, resulting in better thin film transistors. 2005 Elsevier Ltd. All rights reserved. Keywords: Pentacene thin film transistors (TFTs); Poly(dimethyldiallylammonium chloride) (PDDA); Electrostatically assembled PDDA monolayer
1. Introduction Organic microelectronics and optoelectronics have attracted extensive attention for their flexibility and largearea processability [1,2]. Pentacene, as one of the most investigated organic semiconductors, has been used to fabricate microelectronic devices, such as Schottky diodes [3,4], thin film transistors (TFTs) [5–7], and integrated circuits [8,9]. In addition to using advanced deposition methods [7] to improve the growth quality of pentacene thin films, various approaches may be employed to improve the characteristics of the insulator/pentacene interface and source/ drain contacts. Pentacene has been grown on a variety of substrates [5,10–13] and at different substrate temperatures
*
Corresponding author. Tel.: +1 318 2575107; fax: +1 318 2575104. E-mail address: [email protected] (K. Varahramyan).
0038-1101/$ - see front matter 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2005.10.040
[14,6,15]; buffer layers have been used to modify an adjoining insulator surface [16,17]; or a thermally grown SiO2 surface has been treated by oxygen plasma in [18]. Jackson et al., have used octadecyltrichlorosilane (OTS), a self-organizing material, to form a well-ordered monolayer on thermally grown SiO2 [19]. While Kymissis et al., have modified the surface potential of electrode contact by self-assembled 1-hexadecanethiol monolayer [20]. Various applications of self-assembled monolayer (SAM) in electronic devices have been reported, as in Refs. [21,22]. Due to the importance of the insulator/semiconductor interface in field effect transistors, it is necessary to investigate the effect of the interface properties on the device characteristics. In this work, we propose an electrostatic assembly method to assist in the surface and interface modification. In our investigation, an electrostatically assembled monolayer of PDDA is deposited on silicon dioxide (SiO2), before the deposition of pentacene. The
130
M. Zhu, K. Varahramyan / Solid-State Electronics 50 (2006) 129–133
SiO2/pentacene interface is modified by this process. The change of the interface affects the growth and morphology of pentacene. These changes have been observed to lead to significant improvements in the performance of the resulted field effect transistors. 2. Experimental A bottom-contact structure has been adopted for the fabricated devices, as schematically shown in Fig. 1. First, heavily doped n-type silicon wafers are prepared and cleaned, for use as substrate, as well as gate electrode. Second, 100 nm-thick layer of SiO2 is grown on silicon by dry thermal oxidation, and serving as gate dielectric material. Subsequently, a layer of Ti/Au (30 nm/80 nm) is deposited by sputtering (Ti in contact with the oxide), followed by photolithography and wet etching, to pattern the Au/Ti source and drain (S/D) contacts. The wafers are then separated into two groups. Group One, labeled as ‘‘without PDDA,’’ is ready for pentacene evaporation. Group Two is first treated with sulfuric acid and hydrogen peroxide solution (3:7) at 70 C for 3 min, before getting immersed in aqueous poly(dimethyldiallylammonium chloride) (PDDA, MW 200,000, Sigma) solution at a concentration of 15 mg/mL and pH of 8 for 20 min. PDDA is the positively charged polyion, while the SiO2 surface is hydrophilic and is negatively charged
after the treatment by the sulfuric acid and hydrogen peroxide solution [23–25]. During the immersion, a monolayer of PDDA is self-assembled through the electrostatic interaction and hydrogen bonding between PDDA nanoparticles and the SiO2 surface, as well as good adhesion of PDDA to a free surface [26]. Actually, PDDA is one of the commonly used materials to form precursor layers in layer-by-layer (LBL) self-assembly technique [27–30]. When this monolayer is built up, electrostatic self-assembly will stop accordingly. The thickness of the adsorbed PDDA monolayer is in precision of 1–2 nm and monitored by the Quartz Crystal Microbalance (QCM, USI-System, Japan) technique [25]. Then, Group Two is labeled as ‘‘with PDDA’’ and is ready for pentacene evaporation. Pentacene (Aldrich, without purification) is then deposited on the channel (75 lm length and 1000 lm width) and source/drain regions by thermal evaporation, at 1 · 106 Torr, through shadow mask, for both groups, at ˚ /s in room temperature for a deposition rate of about 6 A the substrates. The thickness of the pentacene thin film is 300 nm, as measured by a Tencor Surface Profiler. The fabricated devices are electrically tested with a Keithley Test System, at atmospheric ambient condition. The output and transfer characteristics of the fabricated pentacene TFTs have been measured for both sets of devices (i.e., with and without the PDDA monolayer). 3. Results and discussion
Fig. 1. Schematic structure of fabricated pentacene TFTs.
The SEM micrographs in Fig. 2(a) and (b) show the surface profile of pentacene, after deposition, on TFTs without and with the PDDA monolayer, respectively. The insertion of the PDDA monolayer appears to affect the growth of pentacene, resulting in different grain size. The surface profile without the PDDA monolayer shows irregular grain size, with clear grain boundaries (Fig. 2(a)), caused by the untreated surface. The presence of the PDDA monolayer, seems to have noticeably improved the surface condition, yielding a better surface
Fig. 2. SEM surface profile of pentacene after deposition on TFTs (a) without and (b) with electrostatically assembled monolayer of PDDA.
M. Zhu, K. Varahramyan / Solid-State Electronics 50 (2006) 129–133
profile for pentacene (Fig. 2(b)), with smoother grains, and more uniform grain size. Electrical measurements of the fabricated devices reveal that by adding a layer of electrostatically assembled PDDA at the channel/insulator interface, the device performance becomes significantly improved. The transfer characteristics (Ids–Vgs) of devices with and without PDDA are compared in Fig. 3, and the output characteristics (Ids–Vds) of both devices are provided in Fig. 4. Generally the following two conventional equations for inorganic transistors are employed to describe the behavior of organic transistors [31,32]: wC i V ds I ds ¼ l V gs V th ð1Þ V ds ðLinear-regionÞ; L 2 wC i 2 lðV gs V th Þ ðSaturation-regionÞ; I ds ¼ ð2Þ 2L where W and L are the channel width and length respectively, l is the carrier mobility for n-channel device, Ci is the capacitance per unit area of the dielectric layer, and Vth is the threshold voltage.
Fig. 3. Comparison of the transfer characteristics of pentacene TFTs without (squares) and with (stars) electrostatically assembled monolayer of PDDA.
131
Table 1 Comparison of the pentacene TFTs without and with electrostatically assembled monolayer of PDDAa
Without PDDA With PDDA
Vth (V)
leff (cm2/V s) S (V/decade) On/off ratio
4.20
0.015
2.45 (42%) 0.020 (33%)
4
104
2 (50%)
2 · 104 (100%)
a
Extracted from Ids–Vgs at Vds = 60 V. Mobility is calculated by Eq. (2) from Ids–Vgs curves at Vds = 60 V and Vgs = 40 V.
Based on the above equations and experimental data, the device parameters for both groups of pentacene TFTs have been extracted and compared, as demonstrated in Table 1. The extracted parameters include threshold voltage (Vth) by the linear extrapolation method from the Ids–Vgs data at saturation region (Vds = 60 V), effective hole mobility (leff) from the Ids–Vgs data at saturation region (Vds = 60 V and Vgs = 40 V), subthreshold slope (S), and on/off ratio. From Table 1 it can be seen that the SiO2/pentacene interface has been successfully improved by the presence of the PDDA monolayer. Particularly, the effective hole mobility leff increases from 0.015 cm2/V s to 0.02 cm2/V s (by 33%), the threshold voltage Vth decreases from 4.2 V to 2.45 V (by 42%), the subthreshold slope S is noticeably improved from 4 V/decade to 2 V/decade (by 50%), and the on/off ratio is improved from 1 · 104 to 2 · 104 (by 100%). The discrepancy exists between Figs. 3 and 4, which may be introduced in the measurement and need further investigation. Similar to the conventional insulated gate field effect transistors, in organic thin film transistors, the insulator/ semiconductor interface plays an important role on the device parameters, including mobility and subthreshold slope. It is generally known that mobility is improved by reduction in surface scattering mechanisms that may occur in the presence of a smoother interface. The presence of charge trapping [33] can influence the device subthreshold slope. Specifically, the subthreshold slope affected by interface traps can be expressed as [34],
-12 With PDDA:Vgs = -40 V
Drain Current (µA)
With PDDA:Vgs = -30 V
-8
and Without PDDA: Vgs = -40 V
-6
With PDDA:Vgs = -20 V
-4
With PDDA:Vgs = -10 V Vgs = -30 V
-2 0
Vgs = -20 V Vgs = -10 V
0
-10
-20 -30 -40 Drain Voltage (V)
-50
1 þ ðC S þ C it Þ=C i ; 1 þ C S =C i
ð3Þ
kT CS ln 10 1 þ ; q Ci
ð4Þ
S ¼ S0
-10
-60
Fig. 4. Comparison of the output characteristics of the pentacene TFTs without (solid) and with (dashed) electrostatically assembled monolayer of PDDA.
S0 ¼
where S0 is the subthreshold slope without interface traps, CS is the capacitance associated with the space charge layer in the organic semiconductor, Ci is the capacitance of the insulator, and Cit is the capacitance associated with the interface traps, and which is in parallel with CS. We assume here that the SiO2/pentacene interface has reduced interface traps after the treatment by the electrostatically assembled PDDA monolayer. In the device with PDDA monolayer, the insulator capacitance Ci may be substituted by Ci and
132
M. Zhu, K. Varahramyan / Solid-State Electronics 50 (2006) 129–133
the series capacitance of the PDDA monolayer, CPDDA. Since the PDDA monolayer is very thin (1–2 nm compared to SiO2 100 nm) and its dielectric constant is supposed to be very high (normally ten times higher for polyion films than thermally grown SiO2 [27,35]), the total capacitance of Ci and CPDDA is almost unchanged or about equal to Ci. Therefore Cit can be calculated by Eqs. (3) and (4), and the density of interface traps can be approximated by Ci12 2 eV1 t = eNit [33]. An effective density of 7.0 · 10 cm is calculated for the device without electrostatically assembled monolayer of PDDA. Interface traps show similar negative influences on effective hole mobility, and on/off ratio in thin film transistors. For the device modified by the PDDA monolayer, these parameters are improved. At the SiO2/pentacene interface, the PDDA monolayer appears to reduce the physical defects and create a smoother interface. 4. Conclusions The results presented in this paper show that an electrostatically assembled monolayer of PDDA can be used to modify and improve the interface between the insulator and active material in thin film transistors. In this work, the insulator and active material consisted of silicon dioxide and pentacene, respectively. By the immersion in the aqueous solution, PDDA nanoparticles form an ordered monolayer on SiO2 through electrostatic self-assembly. Introduction of the PDDA monolayer at the SiO2/pentacene interface has resulted in improved device performance, including higher effective mobility and lower subthreshold slope. Acknowledgements The authors acknowledge the laboratory and technical resources provided by the Institute for Micromanufacturing for the realization of this work. They also thank Dr. Yuri Lvov and Ms. Jingshi Shi for their assistance with the PDDA monolayer assembly. References [1] Angelopoulos M. Conducting polymers in microelectronics. IBM J Res Dev 2001;45(1):57–75. [2] Dimitrakopoulos CD, Malenfant PRL. Organic thin film transistors for large area electronics. Adv Mater 2002;14(2):99–117. [3] Lee YS, Park JH, Choi JS. Electrical characteristics of pentacenebased Schottky diodes. Opt Mater 2002;21:433–7. [4] Kuniyoshi S, Naruge S, Iizuka M, Nakamura M, Kudo K, Tanaka K. Thermally stimulated current of pentacene Schottky diode. Synth Met 2000;137:895–6. [5] Lin YY, Gundlach DJ, Jackson TN, Nelson SF. Pentacene-based organic thin film transistors. IEEE Trans Electron Dev 1997;44:1325–31. [6] Lee JH, Kim SH, Kim GH, Lim SC, Lee H, Jang J, et al. Pentacene thin film transistors fabricated on plastic substrates. Synth Met 2003;139:445–51.
[7] Dimitrakopoulos CD, Brown AR, Pomp A. Molecular beam deposited thin films of pentacene for organic field effect transistor applications. J Appl Phys 1996;80:2501–8. [8] Klauk H, Gundlach DJ, Jackson TN. Fast organic thin film transistor circuits. IEEE Electron Dev Lett 1999;20:289–91. [9] Loo YL, Someya T, Baldwin KW, Bao Z, Ho P, Dodabalapur A, et al. Soft, conformable electrical contacts for organic semiconductors: high-resolution plastic circuits by lamination. PNAS 2002;99:10252–6. [10] Klauk H, Gundlach DJ, Nichols JA, Jackson TN. Pentacene organic thin-film transistors for circuit and display applications. IEEE Trans Electron Dev 1999;46(6):1258–63. [11] Klauk H, Halik M, Zschieschang U, Schmid G, Radlik W. Highmobility polymer gate dielectric pentacene thin film transistors. J Appl Phys 2002;92(9):5259–63. [12] Knipp D, Street RA, Volkel A, Ho J. Pentacene thin film transistors on inorganic dielectrics: morphology, structural properties, and electronic transport. J Appl Phys 2003;93(1):347–55. [13] Puigdollers J, Voz C, Orpella A, Quidant R, Martin I, Vetter M, et al. Pentacene thin-film transistors with polymeric gate dielectric. Org Electron 2004;5(1–3):67–71. [14] Wang G, Moses D, Heeger AJ, Zhang H-M, Narasimhan M, Demaray RE. Poly(3-hexylthiophene) field-effect transistors with high dielectric constant gate insulator. J Appl Phys 2004;95(1):316–22. [15] Chang J-W, Kim H, Kim J-K, Ju BK, Jang J, Lee Y-H. Structure and morphology of vacuum-evaporated pentacene as a function of the substrate temperature. J Korean Phys Soc 2003;42:S268–72. [16] Jin SH, Yu JS, Kim JW, Lee CA, Park B-G, Lee JD et al. PMMA buffer-layer effects on electrical performance of pentacene OTFTs with a cross-linked PVA gate insulator on a flexible substrate. Society for information display 2003 digest. Baltimore, MD, USA. 2003. p. 1088–91. [17] Uemura S, Yoshida M, Hoshino S, Kodzasa T, Kamata T. Investigation for surface modification of polymer as an insulator layer of organic FET. Thin Solid Films 2003;438–439:378–81. [18] Liang G. Organic diodes, field-effect transistors, and an inverter circuit by microfabrication techniques. PhD dissertation. Louisiana Tech University, 2003. [19] Jackson TN, Lin Y-Y, Gundlach DJ, Klauk H. Organic thin-film transistors for organic light-emitting flat-panel display backplanes. IEEE J Sel Top Quantum Electron 1998;4(1):100–4. [20] Kymissis I, Dimitrakopoulos CD, Purushothaman S. High-performance bottom electrode organic thin-film transistors. IEEE Trans Electron Dev 2001;48(6):1060–4. [21] Parviz BA, Ryan D, Whitesides GM. Using self-assembly for the fabrication of nano-scale electronic and photonic devices. IEEE Trans Adv Pack 2003;26(3):233–41. [22] Ulman A. Formation and structure of self-assembled monolayers. Chem Rev 1996;96:1533–54. [23] Chiarelli PA, Johal MS, Casson JL, Roberts JB, Robinson JM, Wang H-L. Controlled fabrication of polyelectrolyte multilayer thin films using spin-assembly. Adv Mater 2001;13:1167–71. [24] Puiso J, Lindroos S, Tamulevicius S, Leskela M, Snitka V. The influence of the pretreatment of Si substrate on the growth of PbS thin films in the SILAR technique. Solid State Phenom 2003;94:261–4. [25] Cui T, Hua F, Lvov Y. FET fabricated by layer-by-layer nanoassembly. IEEE Trans Electron Dev 2004;51(3):503–6. [26] Ai H, Fang M, Lvov Y, Mills DK, Jones SA. Applications of the electrostatic layer-by-layer self-assembly technique in biomedical engineering. In: Annual international conference of the IEEE engineering in medicine and biology proceedings, vol. 1. 2002. p. 502–3. [27] Hua F, Shi J, Lvov Y, Cui T. Fabrication and characterization of metal–oxide–semiconductor capacitor based on layer-by-layer selfassembled thin film. Nanotechnology 2003;14:453–7. [28] Cui T, Liang G, Shi J. Fabrication of pentacene organic field-effect transistors containing SiO2 nanoparticle thin film as the gate dielectric. Int Electron Dev Meeting 2003:207–10.
M. Zhu, K. Varahramyan / Solid-State Electronics 50 (2006) 129–133 [29] Shi J, Cui T. Fabrication of indium resistors by layer-by-layer nanoassembly and microlithography techniques. Solid-State Electron 2003;47:2085–8. [30] Hua F, Lvov Y, Cui T. A lithographic approach of spatial separation for multiple types of layer-by-layer self-assembled nanoparticles. Thin Solid Films 2004;449:222–5. [31] Arora. MOSFET models for VLSI circuits simulation: theory and practice. Wien, New York: Springer-Verlag; 1993.
133
[32] Horowitz G. Organic field-effect transistors. Adv Mater 1998;10:365–77. [33] Schon JH, Batlogg B. Trapping in organic field-effect transistors. J Appl Phys 2001;89(1):336–42. [34] Sze SM. Physics of semiconductor devices. New York: Wiley; 1981. [35] Tedeschi C, Mohwald H, Kirstein S. Polarity of layer-by-layer deposited polyelectrolyte films as determined by pyrene fluorescence. J Am Chem Soc 2001;123:954–60.