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Phase change and electrical characteristics of Ge–Se–Te alloys
Microelectronic Engineering 86 (2009) 1950–1953
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Phase change and electrical characteristics of Ge–Se–Te alloys Eui-Bok Lee a,b, Byeong-Kwon Ju b, Yong-Tae Kim a,* a b
Semiconductor Materials and Device Lab, Korea Institute of Science and Technology, P.O. Box 131, Cheongryang, Seoul 130-650, Republic of Korea Display and Nanosystem Lab., Korea University, Republic of Korea
a r t i c l e
i n f o
Article history: Received 4 March 2009 Received in revised form 9 March 2009 Accepted 10 March 2009 Available online 19 March 2009
a b s t r a c t Effects of Se contents in Ge–Se–Te ternary systems are investigated using edge contact type phase change random access memory cell structures. Increasing the Se content from 6 to 35 at% crystallization temperature and Ovonic switching threshold voltage are increased due to the large grain growth of hexagonal microstructure in the Ge–Se–Te alloys. Ó 2009 Elsevier B.V. All rights reserved.
Keywords: Phase change materials Ge–Se–Te alloys Chalcogenide
1. Introduction Since the 1990s, tellurium-based chalcogenide materials have been extensively studied for the applications to semiconductor memories [1–4]. Ge2Sb2Te5 (GST) is one of the best materials for the phase change random access memory (PRAM) because the GST has two stable states, namely, high and low resistance values, which correspond to the amorphous and crystalline phases of GST, respectively. However, achieving the fast operation speed at lower current requires an alternative chalcogenide material to replace the GST [5]. The critical requirements for the new phase change material are summarized as follows: amorphous stability at room temperature, short crystallization time, big margin in the resistance difference between amorphous and crystalline states, and lower reset current. So far, various ways have been suggested to solve the above mentioned problems, for example, changing crystallization behaviour doping typical elements into the GST [6–9], and shrinking the dimension of programmable volume [10,11]. However, it is more important to understand the behaviour of Te based chalcogenide material than developing some empirical method to improve the performance of PRAM cell. In this study, we have studied Ge–Se–Te alloys changing stoichiometry according to the stable and unstable regions in the phase diagram of Ge–Se–Te system. From experimental results of melting and crystallization temperatures, I–V characteristics, and transmission electron microscopy we have explained how the phase change behavior of Ge–Se–Te alloy is influenced by the Se
* Corresponding author. Tel.: +82 2 958 5745; fax: +82 2 958 5739. E-mail address: [email protected] (Y.-T. Kim). 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.03.089
contents, and discussed the relationship between microstructure and electrical characteristics of Ge–Se–Te alloys.
2. Experiment Ge–Se–Te alloys were deposited on SiO2/Si substrate by rf magnetron sputter. The high-purity Ge (99.99%), Te (99.99%), Se (99.99%), GeTe (99.99%), GeSe (99.99%), GeSe2 (99.99%), Se1Te9 (99.99%), and Se3Te7 (99.99%) were used as sputtering targets. The edge contact type PRAM cells were fabricated to measure electrical characteristics of chalcogenide alloy. The TiN bottom electrode with the thickness of 100 nm and the width is 2–10 lm was deposited on the SiO2 substrate. To prepare the heat dissipation layer between the bottom and top electrodes, SiO2–ZnS was covered on the patterned bottom electrode and the edge contact dimension was defined with the etch stop process at the SiO2 protection layer. Ge–Se–Te alloys and the top electrode were deposited by rf sputtering and finally, the contact hole was opened, forming the top electrode. The thickness of Ge–Se–Te layer is 200 nm and the contact dimension is 0.2–1 lm2. The electrical characteristics of PRAM cells were measured with a steady state DC I–V test and transient pulse test. A semiconductor parameter analyzer (Agilent 4155B) and pulse generator (Agilent 81101A) were connected to the bottom and top electrode for DC and pulse test, respectively. The input and output pulse were also measured by an oscilloscope (LeCroy 104Xs). For the DC test, a positive current of zero to several mA is applied to the top electrode and the voltage change in both ends of the device is measured. For the pulse test, the I–V characteristic is measured to calculate the resistance change with increasing a positive pulse voltage and
E.-B. Lee et al. / Microelectronic Engineering 86 (2009) 1950–1953
applying higher pulse voltage if there is no change in the DC resistance. 3. Results and discussion Fig. 1 shows the XRD patterns of the GexTe100 x (x = 17, 25 and 50) thin films as a function of annealing temperature at 250, 300 and 350 °C for 10 min. A cubic structured GeTe peak is observed in the Ge50Te50 thin film at all annealing conditions. However, in Ge17Te83 and Ge25Te75 thin films both peaks of GeTe (cubic structure) and Te (hexagonal structure) are appeared at 250 and 300 °C and at the higher annealing temperature of 350 °C Te peak is only observed. This means that as increasing Te content metallic bonding becomes stronger due to the Te–Te bonds besides of Se–Te bonds and Te hexagonal crystallization is easily enhanced by the number of Te–Te bonds which is increased by the higher content of Te. Fig. 2 shows the bright-field TEM images and fast-Fourier transformation (FFT) lattice images of the Ge17Te83(a), Ge25Te75(b), Ge50Te50(c) and high-resolution TEM image of the Ge50Te50 (d). Fig. 2a and b revealed that phase separation occurs in the Ge25Te75, forming the cubic structured Ge50Te50 and the hexagonal structured Te phase. These separated phases are identified with the distance ratio of each diffraction spot of the TEM diffraction pattern image. Fig. 3 shows the resistance changes with the crystallization temperature for the Ge–Te alloys. This measurement is done with the temperatures ranges from room temperature to 350 °C and the rising speed of temperature is 3 °C/min and every temperature step is holding for 1 min. The resistance of as-deposited films is very high due to the amorphous phase at the room temperature. The crystallization temperature (Tx) of the Ge17Te83, Ge25Te75 and Ge50Te50 thin films is 240, 230 and 200 °C, respectively. And, Fig. 3 suggests that the crystallization process of Ge50Te50 film is relatively slow comparing the cases of higher Te content. This
Fig. 1. X-ray diffraction pattern of the (a) Ge17Te85, (b) Ge25Te75 and (c) Ge50Te50 thin films. The samples were annealed at 250, 300 and 350 °C for 10 min.
1951
result implies that the Ge50Te50 film has demerit of slow crystallization since it has the stable single phase of Ge–Te. However, increasing the Te content the crystallization is also occurred at higher temperature. Takamori also reported that the crystallization temperature is increased when the Te content is over than 80 at% [12]. According to his report, the crystallization of Ge–Te binary system depends on the heating rate and as increasing the heating rate the crystallization has proportionally increased with the composition ratio of Te to Ge, but decreasing the heating rate, the crystallization temperature is ratherly increased at the 80 at% of Te.
Fig. 2. Bright-field TEM images and diffraction patterns of (a) Ge17Te83, (b) Ge25Te75 and (c) Ge50Te50 thin films annealed at 350 °C for 10 min, and high-resolution TEM image of (d) Ge50Te50 film.
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E.-B. Lee et al. / Microelectronic Engineering 86 (2009) 1950–1953
Fig. 3. The resistance changes with the crystallization temperature for the Ge–Te alloys.
Fig. 4. The resistance changes with the crystallization temperature for the Se–Te alloys.
Fig. 4 shows the resistance characteristics of SexTe100 x corresponding to the crystallization temperature. When the Se content increases from 15, 23, to 35, the crystallization temperature is also changed from 60, 70 to 85 °C. Generally, it is known that the Se–Te binary alloy has lower crystallization temperature and Te hexagonal phase is normally appeared in the Se–Te binary alloys with various composition [13]. Since the Te content causes lower
Fig. 5. Current–voltage characteristics the edge contact type cell structures with Se15Te85, Se23Te77 and Se33Te65. The threshold voltage increases as the increasing of Se content.
crystallization temperature and the binding energy of Se–Te is lower than that of Te–Te bonds, the SexTe100 x (x = 15, 23, 35) has low crystallization temperature because the Te content is relatively higher than the Se content in this SexTe100 x (x = 15, 23, 35). Therefore, the crystallization temperature of Se15Te85 is lower than those of Se23Te77 and Se35Te65. However, in the case of higher content of Te the crystallization temperature is lower than 100 °C, which means that the crystallization temperature of Se15Te85 is too low to be used for the practical application of PRAM. Fig. 5 also shows that the threshold switching voltage is in the range of 2–4 V, which is relatively higher than the case of lower Se content. In other words, the threshold voltage of the Se–Te alloy containing the Te hexagonal phase seems to be increased with the higher crystallization temperature. In this work, we have tried to improve the slow crystallization process of Ge–Te alloy and to rise the crystallization temperature of the Se–Te that is below than 100 °C by using Ge–Se–Te ternary system and measured the microstructure and the electrical performance of Ge–Se–Te PRAM cell devices. Fig. 6 is the HR-TEM image of Ge49Se35Te16. In this figure, the lattice constant of ( 1 10) oriented GeTe is 3.46 A, d( 200) = 3.00 A. And, the lattice constant of (1 1 0) Se plane is 2.19 A, which equals to d ( 120). This result reveals that FCC structured Ge–Te and Hexagonal structured Se–Te are co-existed in the Ge49Se35Te16. Therefore, it is plausible that the threshold voltage and the crystallization temperature are increased with the increase of Se content due to the existence of hexagonal structured Se–Te. Fig. 7 shows the crystallization temperature characteristics of Ge–Se–Te alloys. The crystallization
Fig. 6. The cross-sectional TEM image and SAED pattern of the Ge49Se35Te16 thin films.
E.-B. Lee et al. / Microelectronic Engineering 86 (2009) 1950–1953
1953
cause, the crystallization temperature is also greatly increased comparing the other cases where the Se contents are less than 40 at%. From Fig. 8, it is found that the threshold voltage of the Ge50Te50 is 2.1 V, adding the Se element in the Ge50Te50, Ge52Se06Te44 is 1.4 V and increasing the Se content from 15 to 35, Ge47Se15Te38 and Ge49Se35Te16 is 1.8 and 1.9 V, respectively. These experimental results indicate that the switching voltage of PRAM can be reduced by adding the Se into the Ge–Te binary system and the higher crystallization temperature can be obtained with the Se content. The microstructure analysis suggests that the stable FCC single phase and the hexagonal Te influence on the threshold voltage as well as the crystallization temperature. 4. Conclusion
Fig. 7. The resistance changes with the crystallization temperature for the Ge–Se– Te alloys.
The switching threshold voltage and the crystallization temperature of Ge–Se–Te ternary alloy are increased with the Se content. The reason for such increases of switching voltage and crystallization temperature is ascribed to the hexagonal structured Se–Te phase due to the high Se content. However, the switching voltages of Ge–Se–Te alloys are still relatively lower than that of Ge50Te50, which improves the power consumption of PRAM. And, the higher crystallization temperature with the Se content is good for the stable operation of PRAM. Therefore, these results are important for understanding the phase change behaviour of Ge–Te binary alloys and the effects of Se in the Ge–Se–Te ternary alloys. Acknowledgements
Fig. 8. Current–voltage characteristics the edge contact type cell structures with Ge50Te50, Ge52Se06Te42, Ge47Se15Te38 and Ge49Se35Te16. The threshold voltage increases as the increasing of Se content.
temperatures of Ge52Se06Te44, Ge47Se15Te38, and Ge49Se35Te16 are 220, 246 and 255 °C, respectively. As shown in Fig. 3, the crystallization temperature of Ge50Te50 is increased from 200 °C to the higher temperature by increasing the Se content. In the practical devices, switching speed depends on the time for the crystallization. If the crystallization temperature is increased, it is simply concluded that more time is necessary for reaching at the crystallization temperature, which means that the switching speed may be delayed due the higher crystallization temperature. Although the switching speed should be carefully measured with the PRAM cell devices, we did not measure the switching speed in this work. However, the switching speed can be estimated with the slope of resistance change depending on the crystallization temperature since the resistance changes abruptly from high to low when the crystallization occurs quickly. Comparing Figs. 3 and 7, the slope of resistance changes in the Ge–Te and the Ge–Sb–Te alloys seems to be not different. However, increasing the Se content over than about 40 at% the slope is not steep but easy, meaning that the crystallization is slowly occurred in the wide temperature ranges. Of
This research was supported by the National Research Project for Phase-Change Random Access Memory Development sponsored by the Korean Ministry of Knowledge Economy and Samsung Electronics and supported by the National Research Laboratory (NRL, R0A-2007-000-20111-0) Program of the Ministry of Education, Science and Technology (Korea Science and Engineering Foundation, KOSEF). References [1] K. Nakayama, T. Kitagawa, M. Ohmura, M. Suzuki, Jpn. J. Appl. Phys. 32 (1993) 564. [2] J. Maimon, E. Spall, R. Quinn, S. Schnur, in: Proc. 2001 IEEE Aerospace Conf., Big Sky, vol. 5, 2000, p. 2289. [3] S. Lai, T. Lowrey, IEDM Tech. Dig. (2001) 803. [4] A. Pirovano, A.L. Lacaita, D. Merlani, A. Benvenuti, F. Pellizzer, R. Bez, IEDM Tech. Dig. (2002) 923. [5] M.S. Youm, Y.T. Kim, M.Y. Sung, Phys. Status Solidi A 205 (2008) 1636–1640. [6] N. Matsuzaki, K. Kurotsuchi, Y. Matsui, O. Tonomura, N. Yamamoto, Y. Fujisaki, N. Kitai, R. Takemura, K. Osada, S. Hanazawa, H. Moriya, T. Iwasaki, T. Kawahara, N. Takaura, M. Terao, M. Matsuoka, M. Moniwa, IEDM Tech. Dig. (2005) 738. [7] T.-T. Yeh, T.-E. Hsieh, H.-P.D. Shieh, Thin Solid Films 488 (2005) 211–216. [8] K. Kim, J.-C. Park, J.-G. Chung, S.A. Song, M.-C. Jung, Y.M. Lee, H.-J. Shin, B. Kuh, Y. Ha, J.-S. Noh, Appl. Phys. Lett. 89 (24) (2006) 243520–243523. [9] K. Wang, D. Wamwangi, S. Ziegler, C. Steimer, M. Wuttig, J. Appl. Phys. 96 (10) (2004) 5557–5562. [10] Y.H. Ha, J.H. Yi, H. Horii, J.H. Park, S.H. Joo, S.O. Park, in: Symposium on VLSI Technology, 2003. [11] J.M. Shin, Y.J. Song, D.W. Kang, C.W. Jeong, K.C. Ryoo, J.H. Park, J.H. Oh, J.H. Kong, J. Park, Y. Fai, Y.T. Oh, J.I. Kim, D.W. Lim, S.S. Park, J.H. Kim, J.S. Kim, Y.T. Kim, G.H. Koh, G.T. Jeong, H.S. Jeong, K. Kim, Integr. Ferroelectr. 90 (1) (2007) 88–94. [12] T. Takamori, R. Roy, G.J. McCarthy, Mater. Res. Bull. 5 (7) (1970) 529–540. [13] E.T. Kim, J.Y. Lee, Y.T. Kim, Jpn. J. Appl. Phys. 46 (11) (2007) 7392–7395.
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Phase change and electrical characteristics of Ge–Se–Te alloys Eui-Bok Lee a,b, Byeong-Kwon Ju b, Yong-Tae Kim a,* a b
Semiconductor Materials and Device Lab, Korea Institute of Science and Technology, P.O. Box 131, Cheongryang, Seoul 130-650, Republic of Korea Display and Nanosystem Lab., Korea University, Republic of Korea
a r t i c l e
i n f o
Article history: Received 4 March 2009 Received in revised form 9 March 2009 Accepted 10 March 2009 Available online 19 March 2009
a b s t r a c t Effects of Se contents in Ge–Se–Te ternary systems are investigated using edge contact type phase change random access memory cell structures. Increasing the Se content from 6 to 35 at% crystallization temperature and Ovonic switching threshold voltage are increased due to the large grain growth of hexagonal microstructure in the Ge–Se–Te alloys. Ó 2009 Elsevier B.V. All rights reserved.
Keywords: Phase change materials Ge–Se–Te alloys Chalcogenide
1. Introduction Since the 1990s, tellurium-based chalcogenide materials have been extensively studied for the applications to semiconductor memories [1–4]. Ge2Sb2Te5 (GST) is one of the best materials for the phase change random access memory (PRAM) because the GST has two stable states, namely, high and low resistance values, which correspond to the amorphous and crystalline phases of GST, respectively. However, achieving the fast operation speed at lower current requires an alternative chalcogenide material to replace the GST [5]. The critical requirements for the new phase change material are summarized as follows: amorphous stability at room temperature, short crystallization time, big margin in the resistance difference between amorphous and crystalline states, and lower reset current. So far, various ways have been suggested to solve the above mentioned problems, for example, changing crystallization behaviour doping typical elements into the GST [6–9], and shrinking the dimension of programmable volume [10,11]. However, it is more important to understand the behaviour of Te based chalcogenide material than developing some empirical method to improve the performance of PRAM cell. In this study, we have studied Ge–Se–Te alloys changing stoichiometry according to the stable and unstable regions in the phase diagram of Ge–Se–Te system. From experimental results of melting and crystallization temperatures, I–V characteristics, and transmission electron microscopy we have explained how the phase change behavior of Ge–Se–Te alloy is influenced by the Se
* Corresponding author. Tel.: +82 2 958 5745; fax: +82 2 958 5739. E-mail address: [email protected] (Y.-T. Kim). 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.03.089
contents, and discussed the relationship between microstructure and electrical characteristics of Ge–Se–Te alloys.
2. Experiment Ge–Se–Te alloys were deposited on SiO2/Si substrate by rf magnetron sputter. The high-purity Ge (99.99%), Te (99.99%), Se (99.99%), GeTe (99.99%), GeSe (99.99%), GeSe2 (99.99%), Se1Te9 (99.99%), and Se3Te7 (99.99%) were used as sputtering targets. The edge contact type PRAM cells were fabricated to measure electrical characteristics of chalcogenide alloy. The TiN bottom electrode with the thickness of 100 nm and the width is 2–10 lm was deposited on the SiO2 substrate. To prepare the heat dissipation layer between the bottom and top electrodes, SiO2–ZnS was covered on the patterned bottom electrode and the edge contact dimension was defined with the etch stop process at the SiO2 protection layer. Ge–Se–Te alloys and the top electrode were deposited by rf sputtering and finally, the contact hole was opened, forming the top electrode. The thickness of Ge–Se–Te layer is 200 nm and the contact dimension is 0.2–1 lm2. The electrical characteristics of PRAM cells were measured with a steady state DC I–V test and transient pulse test. A semiconductor parameter analyzer (Agilent 4155B) and pulse generator (Agilent 81101A) were connected to the bottom and top electrode for DC and pulse test, respectively. The input and output pulse were also measured by an oscilloscope (LeCroy 104Xs). For the DC test, a positive current of zero to several mA is applied to the top electrode and the voltage change in both ends of the device is measured. For the pulse test, the I–V characteristic is measured to calculate the resistance change with increasing a positive pulse voltage and
E.-B. Lee et al. / Microelectronic Engineering 86 (2009) 1950–1953
applying higher pulse voltage if there is no change in the DC resistance. 3. Results and discussion Fig. 1 shows the XRD patterns of the GexTe100 x (x = 17, 25 and 50) thin films as a function of annealing temperature at 250, 300 and 350 °C for 10 min. A cubic structured GeTe peak is observed in the Ge50Te50 thin film at all annealing conditions. However, in Ge17Te83 and Ge25Te75 thin films both peaks of GeTe (cubic structure) and Te (hexagonal structure) are appeared at 250 and 300 °C and at the higher annealing temperature of 350 °C Te peak is only observed. This means that as increasing Te content metallic bonding becomes stronger due to the Te–Te bonds besides of Se–Te bonds and Te hexagonal crystallization is easily enhanced by the number of Te–Te bonds which is increased by the higher content of Te. Fig. 2 shows the bright-field TEM images and fast-Fourier transformation (FFT) lattice images of the Ge17Te83(a), Ge25Te75(b), Ge50Te50(c) and high-resolution TEM image of the Ge50Te50 (d). Fig. 2a and b revealed that phase separation occurs in the Ge25Te75, forming the cubic structured Ge50Te50 and the hexagonal structured Te phase. These separated phases are identified with the distance ratio of each diffraction spot of the TEM diffraction pattern image. Fig. 3 shows the resistance changes with the crystallization temperature for the Ge–Te alloys. This measurement is done with the temperatures ranges from room temperature to 350 °C and the rising speed of temperature is 3 °C/min and every temperature step is holding for 1 min. The resistance of as-deposited films is very high due to the amorphous phase at the room temperature. The crystallization temperature (Tx) of the Ge17Te83, Ge25Te75 and Ge50Te50 thin films is 240, 230 and 200 °C, respectively. And, Fig. 3 suggests that the crystallization process of Ge50Te50 film is relatively slow comparing the cases of higher Te content. This
Fig. 1. X-ray diffraction pattern of the (a) Ge17Te85, (b) Ge25Te75 and (c) Ge50Te50 thin films. The samples were annealed at 250, 300 and 350 °C for 10 min.
1951
result implies that the Ge50Te50 film has demerit of slow crystallization since it has the stable single phase of Ge–Te. However, increasing the Te content the crystallization is also occurred at higher temperature. Takamori also reported that the crystallization temperature is increased when the Te content is over than 80 at% [12]. According to his report, the crystallization of Ge–Te binary system depends on the heating rate and as increasing the heating rate the crystallization has proportionally increased with the composition ratio of Te to Ge, but decreasing the heating rate, the crystallization temperature is ratherly increased at the 80 at% of Te.
Fig. 2. Bright-field TEM images and diffraction patterns of (a) Ge17Te83, (b) Ge25Te75 and (c) Ge50Te50 thin films annealed at 350 °C for 10 min, and high-resolution TEM image of (d) Ge50Te50 film.
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E.-B. Lee et al. / Microelectronic Engineering 86 (2009) 1950–1953
Fig. 3. The resistance changes with the crystallization temperature for the Ge–Te alloys.
Fig. 4. The resistance changes with the crystallization temperature for the Se–Te alloys.
Fig. 4 shows the resistance characteristics of SexTe100 x corresponding to the crystallization temperature. When the Se content increases from 15, 23, to 35, the crystallization temperature is also changed from 60, 70 to 85 °C. Generally, it is known that the Se–Te binary alloy has lower crystallization temperature and Te hexagonal phase is normally appeared in the Se–Te binary alloys with various composition [13]. Since the Te content causes lower
Fig. 5. Current–voltage characteristics the edge contact type cell structures with Se15Te85, Se23Te77 and Se33Te65. The threshold voltage increases as the increasing of Se content.
crystallization temperature and the binding energy of Se–Te is lower than that of Te–Te bonds, the SexTe100 x (x = 15, 23, 35) has low crystallization temperature because the Te content is relatively higher than the Se content in this SexTe100 x (x = 15, 23, 35). Therefore, the crystallization temperature of Se15Te85 is lower than those of Se23Te77 and Se35Te65. However, in the case of higher content of Te the crystallization temperature is lower than 100 °C, which means that the crystallization temperature of Se15Te85 is too low to be used for the practical application of PRAM. Fig. 5 also shows that the threshold switching voltage is in the range of 2–4 V, which is relatively higher than the case of lower Se content. In other words, the threshold voltage of the Se–Te alloy containing the Te hexagonal phase seems to be increased with the higher crystallization temperature. In this work, we have tried to improve the slow crystallization process of Ge–Te alloy and to rise the crystallization temperature of the Se–Te that is below than 100 °C by using Ge–Se–Te ternary system and measured the microstructure and the electrical performance of Ge–Se–Te PRAM cell devices. Fig. 6 is the HR-TEM image of Ge49Se35Te16. In this figure, the lattice constant of ( 1 10) oriented GeTe is 3.46 A, d( 200) = 3.00 A. And, the lattice constant of (1 1 0) Se plane is 2.19 A, which equals to d ( 120). This result reveals that FCC structured Ge–Te and Hexagonal structured Se–Te are co-existed in the Ge49Se35Te16. Therefore, it is plausible that the threshold voltage and the crystallization temperature are increased with the increase of Se content due to the existence of hexagonal structured Se–Te. Fig. 7 shows the crystallization temperature characteristics of Ge–Se–Te alloys. The crystallization
Fig. 6. The cross-sectional TEM image and SAED pattern of the Ge49Se35Te16 thin films.
E.-B. Lee et al. / Microelectronic Engineering 86 (2009) 1950–1953
1953
cause, the crystallization temperature is also greatly increased comparing the other cases where the Se contents are less than 40 at%. From Fig. 8, it is found that the threshold voltage of the Ge50Te50 is 2.1 V, adding the Se element in the Ge50Te50, Ge52Se06Te44 is 1.4 V and increasing the Se content from 15 to 35, Ge47Se15Te38 and Ge49Se35Te16 is 1.8 and 1.9 V, respectively. These experimental results indicate that the switching voltage of PRAM can be reduced by adding the Se into the Ge–Te binary system and the higher crystallization temperature can be obtained with the Se content. The microstructure analysis suggests that the stable FCC single phase and the hexagonal Te influence on the threshold voltage as well as the crystallization temperature. 4. Conclusion
Fig. 7. The resistance changes with the crystallization temperature for the Ge–Se– Te alloys.
The switching threshold voltage and the crystallization temperature of Ge–Se–Te ternary alloy are increased with the Se content. The reason for such increases of switching voltage and crystallization temperature is ascribed to the hexagonal structured Se–Te phase due to the high Se content. However, the switching voltages of Ge–Se–Te alloys are still relatively lower than that of Ge50Te50, which improves the power consumption of PRAM. And, the higher crystallization temperature with the Se content is good for the stable operation of PRAM. Therefore, these results are important for understanding the phase change behaviour of Ge–Te binary alloys and the effects of Se in the Ge–Se–Te ternary alloys. Acknowledgements
Fig. 8. Current–voltage characteristics the edge contact type cell structures with Ge50Te50, Ge52Se06Te42, Ge47Se15Te38 and Ge49Se35Te16. The threshold voltage increases as the increasing of Se content.
temperatures of Ge52Se06Te44, Ge47Se15Te38, and Ge49Se35Te16 are 220, 246 and 255 °C, respectively. As shown in Fig. 3, the crystallization temperature of Ge50Te50 is increased from 200 °C to the higher temperature by increasing the Se content. In the practical devices, switching speed depends on the time for the crystallization. If the crystallization temperature is increased, it is simply concluded that more time is necessary for reaching at the crystallization temperature, which means that the switching speed may be delayed due the higher crystallization temperature. Although the switching speed should be carefully measured with the PRAM cell devices, we did not measure the switching speed in this work. However, the switching speed can be estimated with the slope of resistance change depending on the crystallization temperature since the resistance changes abruptly from high to low when the crystallization occurs quickly. Comparing Figs. 3 and 7, the slope of resistance changes in the Ge–Te and the Ge–Sb–Te alloys seems to be not different. However, increasing the Se content over than about 40 at% the slope is not steep but easy, meaning that the crystallization is slowly occurred in the wide temperature ranges. Of
This research was supported by the National Research Project for Phase-Change Random Access Memory Development sponsored by the Korean Ministry of Knowledge Economy and Samsung Electronics and supported by the National Research Laboratory (NRL, R0A-2007-000-20111-0) Program of the Ministry of Education, Science and Technology (Korea Science and Engineering Foundation, KOSEF). References [1] K. Nakayama, T. Kitagawa, M. Ohmura, M. Suzuki, Jpn. J. Appl. Phys. 32 (1993) 564. [2] J. Maimon, E. Spall, R. Quinn, S. Schnur, in: Proc. 2001 IEEE Aerospace Conf., Big Sky, vol. 5, 2000, p. 2289. [3] S. Lai, T. Lowrey, IEDM Tech. Dig. (2001) 803. [4] A. Pirovano, A.L. Lacaita, D. Merlani, A. Benvenuti, F. Pellizzer, R. Bez, IEDM Tech. Dig. (2002) 923. [5] M.S. Youm, Y.T. Kim, M.Y. Sung, Phys. Status Solidi A 205 (2008) 1636–1640. [6] N. Matsuzaki, K. Kurotsuchi, Y. Matsui, O. Tonomura, N. Yamamoto, Y. Fujisaki, N. Kitai, R. Takemura, K. Osada, S. Hanazawa, H. Moriya, T. Iwasaki, T. Kawahara, N. Takaura, M. Terao, M. Matsuoka, M. Moniwa, IEDM Tech. Dig. (2005) 738. [7] T.-T. Yeh, T.-E. Hsieh, H.-P.D. Shieh, Thin Solid Films 488 (2005) 211–216. [8] K. Kim, J.-C. Park, J.-G. Chung, S.A. Song, M.-C. Jung, Y.M. Lee, H.-J. Shin, B. Kuh, Y. Ha, J.-S. Noh, Appl. Phys. Lett. 89 (24) (2006) 243520–243523. [9] K. Wang, D. Wamwangi, S. Ziegler, C. Steimer, M. Wuttig, J. Appl. Phys. 96 (10) (2004) 5557–5562. [10] Y.H. Ha, J.H. Yi, H. Horii, J.H. Park, S.H. Joo, S.O. Park, in: Symposium on VLSI Technology, 2003. [11] J.M. Shin, Y.J. Song, D.W. Kang, C.W. Jeong, K.C. Ryoo, J.H. Park, J.H. Oh, J.H. Kong, J. Park, Y. Fai, Y.T. Oh, J.I. Kim, D.W. Lim, S.S. Park, J.H. Kim, J.S. Kim, Y.T. Kim, G.H. Koh, G.T. Jeong, H.S. Jeong, K. Kim, Integr. Ferroelectr. 90 (1) (2007) 88–94. [12] T. Takamori, R. Roy, G.J. McCarthy, Mater. Res. Bull. 5 (7) (1970) 529–540. [13] E.T. Kim, J.Y. Lee, Y.T. Kim, Jpn. J. Appl. Phys. 46 (11) (2007) 7392–7395.