PixFEL: developing a fine pitch, fast 2D X-ray imager for the next generation X-FELs

PixFEL: developing a fine pitch, fast 2D X-ray imager for the next generation X-FELs

Nuclear Instruments and Methods in Physics Research A 796 (2015) 2–7 Contents lists available at ScienceDirect Nuclear Instruments and Methods in Ph...

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Nuclear Instruments and Methods in Physics Research A 796 (2015) 2–7

Contents lists available at ScienceDirect

Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima

PixFEL: developing a fine pitch, fast 2D X-ray imager for the next generation X-FELs L. Ratti a,b,n, D. Comotti a,b, L. Fabris b,c, M. Grassi a,b, L. Lodola a,b, P. Malcovati a,b, M. Manghisoni b,c, V. Re b,c, G. Traversi b,c, C. Vacchi a,b, S. Bettarini d,e, G. Casarosa d,e, F. Forti d,e, F. Morsani e, A. Paladino d,e, E. Paoloni d,e, G. Rizzo d,e, M.A. Benkechkache f,g, G.-F. Dalla Betta f,g, R. Mendicino f,g, L. Pancheri f,g, G. Verzellesi h,g, H. Xu f,g a

Università di Pavia, Dipartimento di Ingegneria Industriale e dell'Informazione, I-27100 Pavia, Italy INFN, Sezione di Pavia, I-27100 Pavia, Italy Università di Bergamo, Dipartimento di Ingegneria e Scienze Applicate, I-24044 Dalmine (BG), Italy d Università di Pisa, Dipartimento di Fisica, I-56127, Italy e INFN, Sezione di Pisa, I-56127 Pisa, Italy f Università di Trento, Dipartimento di Ingegneria Industriale, I-38123 Trento, Italy g TIFPA, I-38123 Trento, Italy h Università di Modena e Reggio, I-41121 Modena, Italy b c

art ic l e i nf o

a b s t r a c t

Available online 18 March 2015

The PixFEL project is conceived as the first stage of a long term research program aiming at the development of advanced X-ray imaging instrumentation for applications at the free electron laser (FEL) facilities. The project aims at substantially advancing the state-of-the-art in the field of 2D X-ray imaging by exploring cutting-edge solutions for sensor development, for integration processes and for readout channel architectures. The main focus is on the development of the fundamental microelectronic building blocks for detector readout and on the technologies for the assembly of a multilayer module with minimum dead area. This work serves the purpose of introducing the main features of the project, together with the simulation results leading to the first prototyping run. & 2015 Elsevier B.V. All rights reserved.

Keywords: X-ray FELs Active edge detectors CMOS deep submicron Low noise readout

1. Introduction Investigating the extremely small and fast phenomena taking place at the nanometer scale and the complex structure of organic and inorganic materials is one of the main trends of modern scientific research. Free electron lasers (FEL) are considered among the most powerful probing tools for the exploration of natural phenomena in this research framework. In free electron lasers, a beam of relativistic electrons is made to wiggle through an undulator eventually producing a coherent and collimated X-ray beam. The minimum wavelength, of the order of one Angstrom, and the intensity of the laser beam made available in FEL systems make it possible to observe objects with nanometer feature size. Laser flash duration, from some tens to some hundreds of femtoseconds, is short enough that the influence of the laser pulse itself on the time evolution of the investigated phenomena is negligible.

n Corresponding author at: Universitàdi Pavia, Dipartimento di Ingegneria Industriale e dell'Informazione, I-27100 Pavia, Italy. E-mail address: [email protected] (L. Ratti).

http://dx.doi.org/10.1016/j.nima.2015.03.022 0168-9002/& 2015 Elsevier B.V. All rights reserved.

A number of research centers, in Europe, the United States and Japan, have started studying, designing and building free electron laser facilities. Some of these facilities, like the SLAC Linear Coherent Light Source (LCLS), in Stanford, or the SPring-8 Compact SASE Source (SCSS), in Japan, are already operational. Others, for example the European XFEL, are currently under construction or, like in the case of the SwissFEL or LCLSII, the foreseen upgrade of the LCLS FEL, are finalizing their proposed design. A broad set of research programs in several different fields, such as structural biology, chemistry, material science, atomic and molecular science (AMO), is being outlined. To take advantage of the potential of X-ray FELs, electronic instrumentation has to be compliant with the X-ray beam properties (which may vary from one facility to the other, or from one beam line to the other within the same facility) and with the experiment specifications. More details about the experiments and measurement techniques deployed at FELs can be found in conceptual and technical design reports and publications easily found on the World Wide Web [1–3]. A wide set of measurements performed at FEL experiments are based on the scattering of coherent X-rays and the detection of the resulting coherent diffraction pattern. In this case, the electronic

L. Ratti et al. / Nuclear Instruments and Methods in Physics Research A 796 (2015) 2–7

instrumentation consists mainly of two-dimensional pixelated X-ray detectors, performing coherent X-ray diffraction imaging (CXDI). The readout electronics has to satisfy severe requirements in terms of space and amplitude resolution, frame rate, input dynamic range and frame storage capability. The PixFEL project is conceived as the first stage of a research program aiming at the development of advanced (with respect to the state-of-the-art) imaging instrumentation for applications at FELs. The main purpose of the project is to study the manufacturing technologies, develop the building microelectronic blocks and investigate the readout architectures enabling the design of an advanced, versatile detection system for imaging at FELs. This work will discuss the main features of the project and present a significant set of the simulation results leading to the first prototyping run.

2. The PixFEL detector The long term goal of the research activity starting with the PixFEL project is the fabrication of an advanced 2D X-ray camera for CXDI measurements, targeting the stringent requirements of experiments at future X-ray FEL facilities. The European XFEL actually represents the most challenging environment among the ones already operational, under construction or just being proposed worldwide. The challenge comes in particular from the beam structure, featuring a high rate burst operation mode where the pulses are delivered in bunch trains lasting 600 μs and containing 2700 bunches, with an inter-train period of 100 ms. However, the final result of the R&D activity will have to retain the needed flexibility to be compatible also with the continuous operation mode typical of other X-FEL facilities, among which the pulse rate may vary by many orders of magnitude, from 100 Hz (like in the LCLS) to 106 Hz (consider for instance the case of the LCLSII). More generally, the detector will have to comply with the following specifications: Pitch: 100 μm Dynamic range: from 1 to 104 photons in the 1–10 keV energy interval Resolution: single photon resolution at small signals, r 20 photons, and a resolution much better than the Poisson limit for larger numbers of photons In-pixel analog-to-digital conversion: 10 bit resolution ( Z 9 bit effective resolution)

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Readout operation: burst mode at 4.5 MHz, 1% duty cycle (like at the Eu-XFEL), or continuous mode In-pixel memory: 1 kframe/pixel (which can be exploited whenever the pulse rate exceeds the chip readout rate) Dead area: r 5% (significantly better than the present implementations based on hybrid pixel technology [4]) Radiation resistance: tolerance to 1 GGy for the sensitive layer, to 10 MGy for the readout electronics In order to develop a high performance X-ray imaging system satisfying the above specifications, cutting-edge microelectronic fabrication processes will have to be fully exploited. An overview of such enabling technologies is provided in Fig. 1, showing a matrix (part of a larger area detection system) of nine 4-side buttable modules. Each module features a multilayer structure resulting from the vertical interconnection of the sensor to a dual-tier front-end chip. Active edge pixel technology, which has been proposed as a possible solution to sizeably reduce the gap between the active area and the edge of the detector [5,6], is investigated in the PixFEL project as an interesting option to minimize the sensor dead area. Specific optimization steps are required for operation with X-rays in the 1–10 keV range. Interconnection between the sensing layer and the front-end chip, given the relatively large pitch of 100 μm, can be easily achieved through bump-bonding techniques. The use of a dual-tier approach for the design of the front-end chip has the main purpose of increasing the functional density. In particular, the upper layer can be used to accommodate the analog front-end channel and the ADC, while in the bottom layer, the memory cells and the digital readout electronics can be integrated. If, like in the case considered in Fig. 1, the sensor is directly bonded to the front-side of the analog layer, a through silicon via (TSV) technology is needed to provide the electrical interconnection to the circuits in the second layer. Depending on the aspect ratio and on the diameter of the TSVs (whose choice, in turn, depends on the number of interconnections per pixel), a more or less aggressive thinning step will be required for the upper tier. On the other side of the vertically integrated structure, low density TSVs represent another key ingredient of a four-side buttable chip. By accessing the input/output pads through the substrate, the use of wire bonds can be avoided and tight side-byside placement of the elementary tiles is made possible. A less aggressive thinning step than in the previous case is required here, since the TSV diameter can be of the order of a few tens of micrometers. As far as the front-end chip fabrication is concerned, the design is being carried out in a 65 nm CMOS technology. Choice

active edge sensor

high density interconnect bond pads bump bonding

low density peripheral TSVs

low density bump bond

high density TSVs

readout chip

active edge sensor

front-end+ADC hybrid board Fig. 1. Conceptual view of the PixFEL detector.

memory+digital readout

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of a nanometer scale CMOS technology is of crucial importance in order to include the required amount of onboard intelligence in the target pitch of 100 μm. Synergy with the wide spectrum of activities going on in the particle physics community, with a focus on microelectronic developments in the same technology, is another compelling motivation for this option. The main detector building blocks (not including the in-pixel memory) are described in the following in more detail.

2.1. Active edge sensor In an active edge sensor, deep trenches are etched around the active area by deep reactive ion etching (DRIE) and then heavily doped to act as wall (ohmic) electrodes. A support wafer is needed to hold different sensors together once the trenches have been etched, and has to be removed at the end of the process. With this approach, planar sensors with a 20 μm gap between the active area and the detector edge were fabricated and successfully tested [7]. As anticipated, for operation in the foreseen energy range, specific process optimization steps are needed. Detection of hard X-rays at 10 keV with a quantum efficiency larger than 90% requires a minimum substrate thickness in excess of 400 μm. At the other end of the energy spectrum, 1 keV, where X-rays have an attenuation length of the order of 1 μm, a thin entrance window (a few hundred of nanometer thick) is needed for acceptable detection efficiency. One serious issue with the detection of a large number of photons is the so-called plasma effect, taking place when a huge concentration of

charge, which may be as high as 2:8  107 in the case of 104 10 keV photons, is released in the sensitive volume [8]. Plasma effect can lead to a performance degradation affecting charge collection distance and time. Two-dimensional device simulations have been performed to evaluate the detector behavior in such extreme conditions. The simulated structure is a p-on-n detector consisting of a 100 μm pitch pixel with two half-pixels on each side (resulting in a total width of 200 μm). The doping concentration of the N-type substrate is 5  1011 cm3 . An optical model was used to emulate the energy dependence of the X-ray beam attenuation in silicon, illuminating the backside of the detector at the centre of the structure. Fig. 2 shows the charge collection time as a function of the applied bias voltage for two values of the detector thickness (300 and 450 μm) and two values of the photon energy (1 and 12 keV) in the case of a 104 photon signal. Collection time never exceeds 30 ns for a bias voltage of 400 V or larger, whatever the photon energy and the detector thickness are. Simulations of the same structure with a cylindrical geometry, currently in progress, seem to indicate that a mitigation of the plasma effect can be obtained with an even smaller bias voltage. Other simulations also show that a breakdown voltage larger than 400 V can be maintained over the entire lifetime of the detector (after exposure to a 1 GGy total ionising dose and an accumulated surface oxide charge density of 3  1012 cm  2 [9,10]) using four floating guard rings with external plate, a 2:4 μm deep junction for the collecting diffusion and a 300 nm thick oxide. Assuming a sensor made up of ladders 2.56  5.12 cm2 in area and a dead region of 200 μm on each of the four sides (including the guard ring structure and the mechanical tolerance in the detector assembly), an overall dead area as small as 2.3% can be achieved.

2.2. Readout channel

Fig. 2. Charge collection time as a function of the applied bias voltage in the case of a 104 photon signal.

The readout channel for the PixFEL detector has to comply with very severe requirements in terms of dynamic range and conversion speed. The block diagram of the front-end circuit is shown in Fig. 3. The first stage is a charge sensitive amplifier with a dynamic compression feature based on the non-linear behavior of the MOS capacitor in the feedback network. The integrated charge is reset through the switch SR. The voltage at the preamplifier output is converted to a current by means of a transconductor with enhanced linearity properties. Trapezoidal, time-variant shaping of the signal is performed through a so-called flip-capacitor filter [11], whose operation is based on a suitable choice for the timing of switches S0 to S4. The sample at the channel output is converted to a 10 bit word by means of a SAR (successive approximation register) ADC with time-interleaved architecture. Operation of the channel at a 5 MHz sampling rate has been successfully simulated. The overall power consumption is less than 350 μW. A description of the single blocks follows, including some simulation results. S3

SR S1 CF

gnd

S4

S0

Vtt

-

S2 Gm

IN

-

b0

-

+

+

10-bit ADC b9

Vts

transconductor

shaper

Fig. 3. Readout channel for the PixFEL detector.

SAR ADC

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2.2.1. Dynamic compression feature Covering the wide (1–10,000 photons) input dynamic range while preserving single photon resolution at small signals is one of the most challenging tasks set by applications at FELs. Single photon detection requires that suitable noise performance be implemented in the charge preamplifier as the first stage of the analog processing chain. On the other hand, such a resolution cannot be preserved over the entire input signal range, due to the limited resolution of the analog-to-digital converter (more than 13 bits would be necessary) and the extremely severe noise constraints. The solution typically adopted consists of providing the system with a non-linear input/ output characteristic, resulting in a charge sensitivity changing with the input signal amplitude. In the AGIPD (adaptive gain integrating pixel detector) front-end channel for applications to the experiments at the Eu-XFEL, a dynamic gain switching technique is used to cover the large dynamic range of the input signal [12]. The approach of the LPD (large pixel detector) project to the issue of large input dynamic range involves employing three different channels in parallel, each with a different gain setting [10]. A similar compression technique is used in the Percival (Pixellated Energy Resolving CMOS Imager, Versatile and Large) detector, based on CMOS monolithic sensor technology. The DEPFET Sensor with Signal Compression (DSSC) uses instead a nonlinear response in the sensing element of the pixel, consisting of a DEPFET device [13]. The solution proposed for the PixFEL readout channel is based on the non-linear capacitance of a MOSFET operated in inversion mode [14], with the gate providing one terminal of the capacitor, the other being the source shortcircuited to the drain, and the P-type bulk (respectively, the N-well) connected to ground (respectively, to VDD) in the case of an Nchannel (respectively, of a P-channel) device. In an inversion-mode MOSFET, the overall capacitance is given by the sum of the gate-tosource and gate-to-drain overlap capacitances when the gate-tosource is much smaller than the threshold voltage. The capacitance may increase even by a few orders of magnitude, depending on the channel size, when the threshold voltage is exceeded. In this case, the predominant contribution comes from the gate-to-channel capacitance, adding to the negligible overlap terms. As a result, the charge sensitivity in the preamplifier changes with the output voltage which in turn depends on the input charge. Fig. 4 shows the voltage signal Vout at the preamplifier output as a function of the input signal in the case of 1 keV photons, when the NMOS in the feedback network has W=L ¼ 40 μm=4 μm. Operation with 10 keV photons yields a virtually identical input/output characteristic, once the channel width of the MOS capacitor has been accordingly scaled. The full output range

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Fig. 5. Charge sensitivity as a function of the input signal.

Fig. 6. Signal at the shaper output for different values of the number of photons at the channel input.

of the preamplifier is 500 mV. The bi-linear characteristic of the preamplifier, with a knee at an output voltage of about 250mV, is apparent. The charge sensitivity G, defined as G ¼ dV out =dQ (Q is the input charge, 1 photon@1 keV C 278 electronsC0.445 fC), is shown in Fig. 5. The value goes from about 20 mV/fC for a single photon input to well below 1 mV/fC for 10,000 photons at 1 keV. The equivalent noise charge (ENC) contributed by the charge sensitive amplifier, about 50 electrons, is compatible with single photon resolution at 1 keV. The dissipated power is 90 μW.

Fig. 4. Signal at the charge sensitive amplifier output as a function of the input signal.

2.2.2. Transconductor and shaper The voltage signal from the charge preamplifier is converted to a current with a transconductor, or V-to-I converter, and then processed by means of a time variant-filter. The choice of a time-variant shaping stage, in the case of events with a known repetition rate as in X-FEL experiments, may provide some advantages over continuous time processing, for instance from the standpoint of time to return to base. Moreover, when in-pixel analog-to-digital conversion is envisioned, the shaper may be designed in such a way to provide the sample to convert directly at its own output, with no intermediate dedicated sample and hold and/or buffering stages. The operation of

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discriminator SPLIT C-DAC SAR LOGIC From the shaper V tc

b9

b0

SPLIT C-DAC Fig. 7. Block diagram of the time-interleaved SAR ADC.

the shaping filter can be described by considering the time evolution of its output signal, as shown in Fig. 6 for different values of the number of photons at the channel input. The 200 ns period allocated for signal shaping and A/D conversion is subdivided into four 50 ns sub-intervals, whose timing is defined through suitable operation of switches S0 to S4 (see Fig. 3). In the first sub-interval, following the preamplifier reset, the preamplifier output baseline is integrated (S0, S1 and S4 are closed, and S2 and S3 are open). Following the baseline integration, while the signal is processed by the charge preamplifier (S0 is open), capacitor CF is flipped (S1 and S4 open and S2 and S3 close). In the third sub-interval, the signal at the preamplifier output is integrated (S0 is closed). During the fourth sub-interval (S0 is open) the shaper output level is sampled by the ADC, and then reset. The voltage variation ΔV s produced at the filter output during the signal integration interval is given by

ΔV s ¼ 

V out Gm τint ; CF

ð1Þ

where Gm is the transconductance of the V-to-I converter and τint is the duration of the signal (and baseline) integration interval. The double integration carried out by the filter, besides providing a trapezoidal shaping, also results in a correlated double sampling operation performed on the preamplifier output signal, mitigating the effects of low frequency noise and of offset contributions at the filter input. The ENC of the overall channel, including the contributions from the charge preamplifier, the transconductor and the shaper, is close to 60 electrons for small signals, yielding a signalto-noise ratio of about 4.6 for 1 photon at 1 keV. The channel gain is 1.6 mV/photon in the high gain (small signal) region, 40 μV/photon in the low gain region. The dissipated power is 120 μW for the transconductor and 40 μW for the filter. 2.2.3. Time-interleaved SAR ADC Both analog [8,10] and digital [13] solutions for in-pixel data storage have been explored in the X-ray imagers currently under the development for applications at the Eu-XFEL. The digital approach seems actually to provide a higher storage capability than the analog one. Also, off-chip transmission of analog data, or transfer of analog samples from the pixel to the periphery of the chip for digitization before data output, is more prone to corruption as compared to the case of in-pixel conversion. The downside of immediate digitization is the need for an ADC inside each pixel, which requires some area and power and a clock distribution scheme. The impact on the readout channel design depends on the ADC resolution and on the adopted architecture. A 10 bit SAR ADC has been chosen for the PixFEL readout channel, as it provides an advantageous trade-off between clock frequency and resolution as compared to other architectures. The block diagram of the circuit is shown in Fig. 7. It is based on a charge redistribution architecture, with a capacitive DAC, which can provide sizeably better accuracy than resistive ladders or mixed capacitiveresistive DAC networks at the chosen 10 bit resolution. The discriminator is a three stage circuit including a preamplification stage, a

second gain stage and a latch. In order to reduce the DAC area, a splitcapacitor architecture has been implemented [15]. Also, a timeinterleaving approach has been adopted to speed up the ADC operation [16] while avoiding large current peaks during the charging phase of the capacitive DAC. In the time-interleaved architecture shown in Fig. 7, during each sampling period, one DAC is pre-charged directly by the shaper output stage, while the sample stored in the other during the previous sampling period is being converted. This leaves one entire sampling period available for A-to-D conversion of each sample. One obvious drawback of the time-interleaved architecture is the area increase which, anyway, is found to be compatible with the pitch specifications of the PixFEL readout channel. Transient noise simulations yield an equivalent number of bits (ENOB) of 9.6, with a figure of merit (FOM) of 21 fJ/conversion step. Integral and differential non-linearities are smaller than 0.5 LSB. The power consumption at a 5 MHz sampling rate is 85 μW, with a static 70 μW contribution from the discriminator and 15 μW of dynamic power consumption from the SAR logic and DAC switches.

3. Conclusions In this paper, the main features of the PixFEL project have been presented. The long term goal of the collaboration is the production of an X-ray pixel camera for applications to experiments at the X-FEL facilities with advanced features as compared to the stateof-the-art in terms of space resolution, dead area and on-chip functionalities. The first part of the project is expressly focused on the development of the main microelectronic building blocks of the camera, including the sensor and the front-end electronics. Promising results have been obtained from device and circuit simulations. The first prototypes, including test structures with the individual blocks (charge preamplifier, shaper, ADC) and an 8  8 array of readout channels have been submitted for fabrication in a 65 nm CMOS technology in the last quarter of 2014. Submission of the active edge sensors is expected before the end of the year. Characterization of the prototypes will include radiation tolerance tests with ionising doses up to 10 MGy for the readout electronics, up to 100 MGy in the case of the active edge sensor.

Acknowledgments The research activity presented in this paper has been carried out in the framework of the PixFEL experiment funded by Istituto Nazionale di Fisica Nucleare (INFN). References [1] LCLS-II New Instruments Workshops Report (Online). Available: 〈http://slac. stanford.edu/pubs/slacreports/reports19/slac-r-993.pdf〉.

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