Planar topological routing of pad nets

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Planar topological routing of pad nets Jan-Ming Ho Institute of Information Science, Academia Sinica, Taipei, Taiwan

G. Vijayan and C.K. W o n g I B M Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York 10598, NY, USA

Received 24 november 1989

Abstract. This paper discusses the problem of single-layer topological routing of pad nets. A pad net is one that connects a set of module pins to a pad on the boundary of the chip. An important application arises in VLS1 designs with many different power sources, in which case there may be multiple power and ground nets to be routed on a single layer. We present an O(n) algorithm for checking the feasibility of a single-layer routing of pad nets, and an O(m x n) algorithm for constructing a planar topological routing, where n is the total number of pad-net pins on all the modules, and m is the number of modules. The feasibility algorithm exploits the special structure of the problem, and is based on a distribution sorting technique rather than being a general planarity checking algorithm. The topological routing algorithm first forms a chain of the modules, and then performs a permutation routing of the nets using the chain as a guide.

Keywords. VLSI, topological routing, pad nets, planar routing, routing algorithm, complexity.

1. Introduction

A pad net is defined to be a net which connects a pad located on the b o u n d a r y of the chip, to a set of pins located on the boundaries of the modules placed in the interior of the chip. This paper discusses the problem of single-layer topological routing of pad nets. An important special case of this problem arises in chip designs with three or more different power sources, where it is desirable to route Elsevier INTEGRATION, the VLSI journal 11 (1991) 295-316 0167-9260/91/$03.50 © 1991 - Elsevier Science Publishers B.V.

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all the power nets on a single layer, i.e., on the metal layer of least resistivity. In a more general situation the pad nets to be routed on a single layer may include multiple power and ground nets as well as other i n p u t / o u t p u t nets. The case where the number of pad nets is two (e.g., one power net and one ground net) is discussed in Kuh and Xiong [4], Moulton [7], and Syed and Gamal [10]. Marek-Sadowska and Tarng [6] discuss a more general problem of routing all n e t s , i n c l u d i n g i n t e r n a l n e t s , o n a single layer. Baker and Pinter [1] discuss the topological and detailed routing of pad nets from a ring of pads to the pins of a single module. We are given a rectangle called the chip boundary, enclosing a number of other rectangles called modules. We assume that the modules have a given fixed placement. A ring of pads is placed on the chip boundary. We assume that there is one distinct pad on the chip boundary for each pad net. The modules have pins placed on their boundaries. A module pin belonging to a pad net is referred to as

Jan-Ming Ho received his Ph.D. degree in electrical engineering and computer science from Northwestern University in 1989. He received his B.S. in elctrical engineering from National Cheng Kung University in 1978 and his M.S. in electronic engineering from National Chiao Tung University in 1980. He is currently an Associate Research Fellow of the Institute of Information Science, Academia Sinica, Taiwan, R.O.C. his research interests include Computational Geometry, VLSI design algorithms, Implementation and Testing of VLSI algorithms on real designs, Computer Architectures, and Operating Systems.

GopalakrishnanVijayan received the B.Sc. degree in mathematics from the University of Madras, in 1975, the B.E. degree in electronics and communication engineering in 1978 and the M.E. degree in automation in 1980 from the Indian Institute of Science, and the M.A. and Ph.D. degrees in electrical engineering and computer science, from Princeton University, in 1982 and 1983 respectively. He is currently a research staff member in the VLSI Design Algorithms group at IBM T.J. Watson Research Center. Previously, he was an assistant professor of computer science at the Georgia Institute of Technology. His current research interests include VLSI design methodologies and algorithms, combinatorial optimization, and graph theory.

C.K. Wong received the Ph.D. degree in mathematics from Columbia University in 1970. He joined the IBM T.J. Watson Research Center in 1969 as a Research Staff Member and is currently manager of the VLSI Design Algorithms group in the Computer Sciences Department. He was Visiting Professor of Computer Science at University of Illinois, Urbana in 1972-73 and at Columbia University in 1978-79. His most recent research is on VLSI design algorithms. He holds four U.S. patents and has published over 120 papers. He is author of the book "Algorithmic Studies in Mass Storage Systems", published by Computer Science Press, 1983. He received two Outstanding Achievement Awards and four Invention Awards from IBM. Dr. Wong is a Fellow of IEEE and a member of the Association for Computing Machinery. He was Editor of IEEE Transactions on Computers from 1982 'to 1985 and is Chair, the IEEE Computer Society Technical Committee on VLSI. He is on the editorial board of the international journal, "Fuzzy Sets and Systems", and is the founding Editor-in-Chief of the international journal "Algorithmica".

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a pad-net pin. For each module we are given a cyclic ordering of its pad-net pins on its boundary. The single-layer pad nets routing problem is to test whether there exists a planar embedding of the pad nets in the region between the module boundaries and the chip boundary. If such a planar embedding exists, we want to construct a planar topological routing of the pad nets. Checking whether a planar embedding exists can be reduced to testing the planarity of an underlying connection graph, in which each module or pad is represented as a vertex, and a connection from a module pin to a pad is represented as an edge (see Section 2 for formal definition). A vertex in the graph which corresponds to a pad is referred to as a pad vertex. A vertex which corresponds to a module is referred to as a module vertex. The planar embedding of the connection graph must satisfy the following two conditions: (1) the pad vertices must appear in the given cyclic order on the boundary of the external face; (2) the cyclic ordering of the edges at each module vertex must correspond to the given cyclic ordering of its pad-net pins. A linear time algorithm for this restricted planarity problem can be derived by transformation to the general planarity problem (similar to Pinter [8]). General planarity testing algorithms, such as [3], have the drawback of being difficult to implement. Also, in the case when the input graph is non-planar, it is difficult to identify the source of non-planarity using such algorithms. In the single layer pad nets routing problem, the underlying connection graph has a very special structure, which enables the derivation of a simple necessary and sufficient condition for the existence of a planar embedding. An abstract planar embedding of the connection graph is simply given by the cyclic orderings of the incident edges at each vertex. These cyclic orderings determine the faces of the planar embedding. Since the cyclic orderings at the module vertices are already given, the only new information in a planar embedding is the ordering of the edges at the pad vertices. The planarity testing algorithm, described in Section 3, generates the only possible candidate ordering of the edges at each pad vertex, and checks whether the combined linear ordering of all the edges at the pad vertices corresponds to a "properly nested" sequence. If the connection graph is non-planar, the algorithm can identify the pad vertex at which the "properly nested" property fails, which can then be used to remedy the non-planarity. A planar topological routing of the pad nets is given by a non-crossing drawing of the edges of the connection graph, such that the orderings of the edges at the vertices are preserved. The modules act as rectangular obstacles in the routing. An important consideration related to the time complexity of the routing algorithm is the total number of turns in the topological paths for the wires of the routing. Let us consider a naive routing algorithm which operates as follows: take the next wire to be inserted, and find a path for it in the current partial routing. Since we start with an abstract planar embedding of the routing, this wire has to be inserted within a particular face of the current partial realization of the embedding, which contains on its boundary the two end points of the wire. In a bad situation, the simple polygon bounding this face might be a complicated maze with many turns. In such a case, the routing of the wire into this face may

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Fig. 1. Example of a naive routing. also have many turns, and thus creating a new face with almost twice the number of turns. If this bad situation repeats for each wire to be inserted, the algorithm will create an exponential number of turns in the routing. Such an example is illustrated in Fig. 1. In this example each module M i is to be connected to a distinct pad P,. Suppose we have already inserted the wires connecting the pairs (M,, P~) for i-- 1, 2, 3, 4 as shown by the solid wires in the figure. These wires have been inserted sequentially by a simple shortest path type algorithm. Consider the insertion of a wire connecting M s and Ps- The only route for this wire is shown by the dotted wire, which weaves in and out of the maze created by the first 4 wires. We leave it to the reader to find the path between M 6 and P6 in the maze created by the first 5 wires. This example can be generalized for any number of modules and pads by playing an adversary game. After each insertion of a wire, place the next module and pad at opposite ends of the current maze. We present a topological routing algorithm that runs in O(m x n) time, where m is the number of modules, and n is the total number of pins. The algorithm guarantees that the total number of turns used in the topological routing is bounded by c x m x n for a small constant c. The algorithm routes all the wires simultaneously in the form of a "pipe", thus avoiding the mazes that can be created by a sequential insertion method. The algorithm first constructs a permutation of the modules by chaining them together. Next, it uses this chain as a pipe to carry all the wires from the pads, and thus constructs a permutation layout between the chain of pads and the chain of modules. The topological routing algorithm is described in Sections 4, 5, and 6. In the case of just two nets, the algorithm can be simplified to run in O(m log m) time. Kuh and Xiong [4] also give an O(m log m) algorithm for this special case. Moulton [7] presents a heuristic algorithm for this case, whose time complexity is unknown.

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Permutation layouts were introduced by Cutler and Shiloach [2]. We point out some differences between the model in [2] and the model used in this paper for the topological routing. In [2], there are two sets of terminals which are linearly placed opposite each other, and corresponding terminals of the two sets are to be connected to each other without any crossings. The model in [2] allows the layout to extend on either side of the two rows of terminals. In the permutation layout application of this paper, the ring of pads correspond to one set of terminals, and the pins on the modules correspond to the other set. The two sets of terminals are not linearly placed. In addition, the layout is not allowed to extend outside the ring of pads. The idea of chaining has been used by Moulton [7] to route a single power net and a single ground net. It is based on the fact that when there are only two pad nets, there is always a planar routing in which one net is routed in the interior of the chain, and the other routed in the exterior. In the case of more than two pad nets, planarity can no longer be guaranteed. Therefore the connection graph has to be tested for planarity. However, when the connection graph is planar, the chain of modules can still be used to guide the topological routing of the pad nets. We also note that [7] gives only a heuristic for constructing a chain of the modules. Therefore no upper bound on either the number of turns in the chain, or the time complexity can be guaranteed. The chaining algorithm described in this paper is very general, and guarantees that the number of turns is O(m), where m is the n u m b e r of modules. Given a topological routing of the pad nets, one can use a detailed routing algorithm such as the one presented by Maley and Leiserson [5] to obtain a detailed routing of these nets. The detailed routing step m a y have to give special consideration to the power and ground nets, paying attention to factors such as voltage drops along these nets, power loss, and overlap capacitances.

2. Statement of the problem We are given the following: 1. A placement of a list of pads P = / 1 , P2 . . . . . Pp in cyclic counter-clockwise order on a rectangular boundary; 2. A placement of a set M = M1, M 2. . . . . M,, of rectangular modules inside the rectangular boundary; 3. For each M i we are given in cyclic counter-clockwise order a list Ci of pins on its boundary, to be connected to specified pads. Let the total n u m b e r of pins be n. We label an edge connecting pad Pj to module M i as (M,, Pj). The underlying connection graph G(V, E) is defined by

1. V = P U M ; 2. E={(Pp, P1)} U { ( P i , P~+l) l l < ~ i < ~ p - 1 } w ( ( M i , ~ ) l M i , connected } ;

Pj

are to be

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~ THE LINEAR ORDER P;-,

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Fig. 2. Linear ordering of edges at a pad.

3. For each module M i we are also given a cyclic ordering Ci of the set of edges:

E~= ((Mi, Py)[(M,, Pj)~E) The single-layer pad nets routing problem is to realize the pad-module connections on a single layer. This is equivalent to checking whether the graph G has a planar embedding which preserves the specified cyclic orderings C, of the edges incident at each module vertex M~, such that the pads appear on the external face of the embedding in the cyclic order given by the list P. Once an embedding is obtained, we have, at each pad Pj, a linear ordering of the edges incident on it from the modules. The first edge in this ordering is the one which is closest to the edge (/',-1, Pi), last one is the one closest to (Pi, P t + l ) (see Fig. 2). In the following sections, we describe algorithms for 1. testing whether a planar embedding exists and generating such a planar embedding (Section 3); and 2. topological routing of the embedding given the placement of pads and the modules (Sections 4, 5, and 6). In section 7, we discuss how to modify the basic model and the algorithms to include the case of equivalent pins on the modules, and the case of over-the-module routing. We also discuss some questions regarding the detailed routing of pad nets.

3. Pianarity testing and generation of planar embedding A planar embedding can be described by giving the cyclic ordering of the incident edges at each vertex of the embedding. These cyclic orderings determine the faces of the embedding and thus the embedding itself. In the single layer pad routing problem, we are given cyclic orderings of edges at the module vertices. The planarity testing problem reduces to that of checking whether there exists linear orderings of the edges incident on the pad vertices, such that the result is a planar embedding of the connection graph. A connection graph is almost a bipartite graph in which the edges run between the two parts, M the module vertices, and P the pad vertices. The edges that make this graph not bipartite are those which chain the pad vertices together. This structural property of the connection graph enables us to obtain a simple necessary and sufficient condition for planarity, which can be tested in linear time.

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We will assume that no two pins on the same module need be connected to the same pad. This is not a restriction, because if more than one pin of a module needs to be connected to the same pad, then these pins must appear consecutively in the cyclic order on the module boundary, otherwise the connection graph is not planar. This is easy to prove, and a proof is given in Syed and Gamal [10]. Therefore we can bunch these pins logically into one pin. With this assumption, it is easy to see that if there are only two pads, then the connection graph is always planar. Therefore we will assume that the n u m b e r of pads p is at least three. A module M~ is said to be consistent with the chain of pads P if its cyclic ordering of edges C~ is a sub-ordering of P. A pair of modules Mi and Mj is said to interleave, if their respective cyclic orderings of edges C~ and Cj, and the chain of pads P satisfy one of the following conditions: 1. C i . . . . P a ' " P c ' " ; Cj . . . . P b ' ' ' P a ' ' ' ; and p .... pa...pb...pc...pa...,or 2. Ci . . . . Pa ' ' ' P b ' ' ' P a ' ' ' ; Cj . . . . Pa . . . P b . . . P~ . . . ; and P .... Pa'''Pb''" Pc'"Pa'"; here Pc may be the same as Pa. These two configurations are illustrated in Fig. 3. Theorem. There exists a planar embedding of a connection graph G, which respects the cyclic orderings C~ of the edges at the module vertices and in which the pad vertices appear on the external face, if and only if, 1. M~ is consistent with P, for i = 1, 2 . . . . . m, and 2. M~ and Mj do not interleave for 1 ~< i ~< m, 1 ~
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Jan-Ming Ho, G. Vijayan, C.K. Wong / Planar topological routing of pad nets Mi

Po

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Fig. 3. Interleaving of modules.

orderings can be found simultaneously in linear time by using a distribution sorting technique. We then get a simple algorithm for testing whether these orderings satisfy the second condition of the theorem by avoiding the two interleaving situations shown in Fig. 3. Consider a module M,. For each edge e = ( M i, Pj) emanating from this module, we define next(e) as the successor edge of e the cyclic ordering C i. We define next2(e) as the edge succeeding next(e) in Ci. N o t e that if Ci has only two edges, then next2(e) = e. If Ci has only the edge e then next2(e) = next(e) = e. Define p (e) as pad vertex Pj on edge e, and re(e) as the module vertex M~ on edge e. For the sake of convenience, we will break the cyclic chain of pads to get a linear chain P~, P2,..., Pp. Instead of requiring the module vertices to be inside the cycle of pads, we require that the module vertices be on the same side of the linear string of pads. It is easy to see that these two versions are equivalent. We will write Pi < Pj if i < j. Consider any two edges el and e 2 incident on the same pad vertex u. That is, u = p (e 1) = p (e 2). The following case analysis on the values u, p (next( e 1)), and p(next(ez) ) gives necessary conditions for planarity on the relative ordering of these two edges at u.

Case 1 Suppose u, p(next(el)), and p(next(e2) ) are all distinct. Then the relative order among these three pad vertices induces a relative order on el and e2 in the linear order at the pad vertex u. If p ( n e x t ( e l ) ) < u < p ( n e x t ( e 2 ) ) , or p(next(e2) ) < p ( n e x t ( e l ) ) < u, or u < p ( n e x t ( e 2 ) ) < p ( n e x t ( e l ) ) , then ea must appear before e 2 in the linear order at the pad vertex. If we place the edges in reverse order, then the other edges of either m(e~) or m(ez) are blocked from reaching their pad vertices without crossings. See Fig. 4 for an illustration of these three situations. Otherwise e2 must appear before e a. ~

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Fig. 4. Illustration of Case 1.

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FNEXT(el) /-NEXT(el} .~//-NEXT(e2)//~/-NEXT(e2)

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Case 2 Suppose u4:p(next(el))=p(next(e2)). Since the two modules m ( e l ) and m(e2) must not interleave it must be the case that one or both of these modules has only two edges incident on it. Otherwise we have an interleaving situation shown in condition 2 of Fig. 3. Hence we have p(next2(el)) = u or p(next2(e2) ) = u. If p(next2(el) ) 4: u, then e I must appear before e 2. This is shown in Fig. 5. If p(next2(e2) ) ¢ u, then e 2 must appear before e 1. Otherwise, if both modules m(el) and m(e2) have only two edges emanating from them, then e 1 and e2 can be placed in any order at u provided the two edges next(e~) and next(ee) are placed in the opposite order at the pad vertex p(next(ea) ) = p ( n e x t ( e 2 ) ). In this particular case, these two modules and the two edges can be merged into a single module as far as planarity testing is considered.

Case 3 Suppose u = p ( n e x t ( e l ) ) or u = p ( n e x t ( e 2 ) ). That is, one of the two modules re(el) or re(e2) has only one edge emanating from it. In this case e I and e 2 can be placed in any order at u. This situation is shown in Fig. 6. The module with only one edge can be removed as far as planarity testing is considered. It is easy to verify that these three cases are exhaustive. Consider the function 2(p × sgn(p(next(e))-p(e))

-p(next(e)));

}

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2(p×sgn(p(next(e))-p(e))

p(next(e)))+l;

p (next2( e )) = p ( e ) where p is the total number of pad vertices, and sgn(x) is defined as the sign of the integer x.

tl

Fig. 6. Illustration of Case 3.

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Let e 1 and e 2 be two edges incident on the same pad vertex u. We leave it to the reader to verify that: 1. If e I must appear before e 2 as described in cases 1 or 2, then f(el)
Planarity testing algorithm (1) For each module M i, check whether it is consistent with the chain of pads P. If not, the connection graph is not planar. (2) Remove all modules with only one edge incident on them. (3) Simultaneously sort all the remaining edges that connect the modules and pads, using a distribution sort on the ordered pairs ( p ( e ) , f(e)). F r o m this sorted list, extract the linear orderings of the edges for each pad vertex P,. As discussed earlier these are the only possible linear orderings at the pad vertices. (4) Testing condition 2 of Fig. 3: Scan the sorted list and verify that if two edges e 1 and e 2 have the same p( el) = p( e2) and f(el) = f ( e 2 ) values, then f(el) is odd. This is the case when the two modules re(el) and m(e2) and the two edges e~ and e 2 can be merged as described earlier. Remove all but one copy of these pair of values. This is equivalent to merging these edges together. Suppose f ( e l ) = f ( e 2 ) is even, and p( el) = p( e2). From the definition of f we can deduce that p ( n e x t ( e l ) ) = p ( n e x t ( e 2 ) ), n e x t 2 ( e l ) ~ e l, and next2(e2) 4: e 2. The two modules re(el) and m(e2) interleave as shown in condition 2 of Fig. 3, and the connection graph is not planar. Since the converse is also true, any interleaving among the modules as shown in condition 2 of Fig. 3, will be discovered in this step. (5) Testing condition 1 of Fig. 3: We can transform this problem to one of checking whether a string S of labeled parentheses is properly nested. For each pad vertex Pj in the order j = 1, 2 . . . . . p, consider the linear order of the edges obtained from the distribution sort. If an edge e is the first edge of the module re(e) to be seen so far, then concatenate the labeled opening parenthesis (,,~e) to the string S. If e is the last edge of re(e) then concatenate the labeled closing parenthesis )re(e) to S. Otherwise concatenate the string ),,(e)(m(e) to S. In other words, each module is represented by k pairs of opening and closing parentheses, where the number of edges emanating from the module is k + 1. These parentheses are ordered according to the linear order of the edges obtained from the distribution sort. It is easy to prove that there is no interleaving as shown in condition I of Fig. 3, if and only if this string S is a properly nested string of labeled parentheses. Test this property using a stack.

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(6) The last step is to split the merged edges of modules with only two incident edges, in reverse order at the two pad vertices, so that these modules are properly nested within one another. Also, insert the edges of modules with only one edge in any arbitrary place in the linear order at the pad vertex. The final result is a set of linear orderings of all edges incident on the pad vertices.

Time complexity The time complexity of the distribution sort in step (3) is O(p + n), which is O(n). The parentheses checking in step (5) can be implemented using a stack to run in O(n) time. The remaining steps also have time complexity O(n).

4. Topological routing We now describe the topological routing algorithm. We describe the main ideas in this Section, and follow with details in Sections 5 and 6. Conceptually, the topological routing algorithm performs the routing in two phases. In the first phase, called the module chaining phase, we create permutation of the modules by chaining them using links. In the second phase, called the permutation routing phase, this chain is used as a pipe to carry the wires emanating from the pads and route them around the modules as dictated by the embedding, thus creating a permutation routing between the permutation of pads and the permutation of modules. A chain of modules is a sequence of objects in which an object may be a module or a simple rectilinear link. The modules and the rectilinear links connecting adjacent modules appear in the chain alternatively. The simple rectilinear links should not cross each other. A naive method of chaining the modules, such as simply choosing a random ordering of modules and trying to create rectilinear links between the adjacent modules, might create an exponential number of turns. This is because, each new link inserted might weave in and out of the regions created by the other links and modules, so that the number of turns is doubled with each insertion. This might happen even in the case where each pad is to be connected to a distinct module, and the chosen ordering of the modules is the natural one imposed by the ordering of pads on the boundary. An example similar to the one in Fig. I can be constructed to illustrate this problem. We use the pre-order traversal of a spanning tree of an x-visibility graph to chain the modules. By doing so, we can guarantee that the total number turns on the chain is O(m ). In the permutation routing phase, we bring the wires originating from the pads together in a bunch (like a ribbon cable). The linear ordering of the wires in the bunch must be the same as the linear ordering given by the embedding. The whole bunch is then routed parallel to the "chain of modules". Conceptually the chain is being used as a pipe to carry these wires. At each module, a "distinguished wire" is connected to a "distinguished pin" on the module. The bunch

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splits into two groups at the position of the distinguished wire, and goes around either side of the module. For each of the nondistinguished pins of the module, a new wire is started at the pin. These wires are inserted between the two groups to get a new bunch of wires, and routed parallel to the next link to the next module. After passing the last module, we have to make connections between the newly created wires and the corresponding wires which originated at the pads. Now all the connection points are in an open region close to the last module, and are not obstructed by any of the modules. Thus, the permutation routing helps us bring all the wires (from pads as well as pins) to an unobstructed region, where the connections can be made easily by just creating a simple rectilinear drawing of the embedding. Since we followed the requirements of the embedding when merging the new wires with old ones, it is guaranteed that a simple drawing can be created. When the bunch of wires follow a link in the chain, the number of turns created for each wire in the bunch is approximately the same as the number of turns in the link. Thus it is important that the total number of turns in the chain is kept within a certain bound. In our algorithm, the chaining of the modules is determined by a natural sequence given by a visibility relation among the modules. The number of turns in the chain is only O ( m ) and thus the total number of turns in all the n wires is O(m x n).

5. Module chaining In this section, the problem of chaining m disjoint rectangular modules by r n - 1 non-crossing simple paths (links) is discussed. Formally, the problem is stated as follows: We are given rn non-intersecting rectangles, { M 1, M 2 . . . . . M m }, with sides parallel to the two axes, where each rectangle is specified by its lower left corner (Ix;, ly;) and upper right corner (ux;, uy;). These rectangles are enclosed within a larger rectangle M 0. The problem is to find an appropriate ordering M~, Mf . . . . , M~ of these rectangle,s and a collection of rn non-crossing simple links L ( i , i + 1), 0 ~< i ~< m such that its starting point a i is on 3//i, and its end point b; is on module Me+ 1. The total number of turns on the chain must be O(m). We will show how to obtain such a chain by constructing and traversing an x-visibility graph. The directed x-visibility graph VG x is defined as follows: Each rectangle (including the enclosing rectangle) is a vertex in this directed graph. For each pair of internal rectangles ( M i, Mj), M; to the left of Mj, such that the two rectangles are visible from each other in the x-direction, we introduce a directed edge. For the enclosing rectangle, we introduce directed edges from its corresponding vertex to vertices representing internal rectangles that are visible in the x-direction from the left edge of the enclosing rectangle. We now describe an algorithm to construct VG x in O(m log m) time. This algorithm is similar to a visibility graph algorithm given by Schlag et al. [9].

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A sweep-line will scan the rectangles along the y-direction in increasing order, so we first sort the set of y-coordinates {lye, uyi [0 ~< i ~< m ). A height-balanced binary tree is maintained to keep track of the modules intersecting the sweep-line. If a point scanned by the sweep-line is the y-coordinate of the lower side of a rectangle M,, then M~ is inserted into its appropriate place in the tree. Let 3//,.~ and M i r be the two rectangles to the left and right of M~ respectively on the scan line. These two rectangles can be extracted from the binary tree. Introduce the directed edges (M, 1, Mi) and (M~, M, r) into VG x. If the point scanned is the y-coordinate of the upper side of a rectangle M~, then 34,. is deleted from the binary tree. Introduce the directed edge (34,.1, M~r), if it has not been introduced earlier. In addition, for each directed edge, we will keep track of the position of the scan line along which they are visible. In other words, with each directed edge ( M i, Mj), we store the horizontal line segment segment(M~, Mj) between the corresponding rectangles, which does not intersect any other rectangle. Since these line segments are all horizontal they do not cross each other. At each vertex (rectangle) the outgoing directed edges (line segments) are ordered according to their y-coordinates. In the following, we use the terms edges and line segments interchangeably. The above algorithm runs in O(m log m) time because each insertion, deletion, or extraction of an adjacent module using a height-balanced binary tree structure, can be done in O(log m) time, and we have a total of O ( m ) insertions, deletions, or extractions. We perform a depth-first search of VG x, and obtain a directed rooted spanning tree T, whose root is the vertex representing the enclosing rectangle. Note that at each vertex the edges of the tree are ordered according to the y-coordinates of their corresponding line segments. For each rectangle Mi, let parent(M~) be the parent of M, in the tree. F r o m the directed spanning tree, we have one line segment incident on a rectangle and zero or more line segments emanating from the rectangle. The end points of these line segments partition the rectangle boundary. Each part is a portion of the boundary from an end point to the next. We associate with an outgoing line segment (tree edge) e = (M,, Mj) that part part(e) of the b o u n d a r y of M, from the end point of this line segment to the end point of the next line segment in counter-clockwise direction (see Fig. 7). The outgoing edges at a vertex of the directed spanning tree are ordered as mentioned previously according to the y-coordinates of their corresponding line segments. The ordering of the rectangles on the chain is given by the depth first numbering (or the pre-order traversal of the directed spanning tree). Let this ordering be M~, M~ . . . . , M~. Note that M~ = M 0. For two adjacent rectangles M,c and M~+I, if M c = parent(M~+l), then use the corresponding line segment of this edge as the link between the two rectangles. Otherwise, let el, e2,... , e k be the sequence of edges on the path from M~ to M e~+l in the underlying undirected version of the spanning tree. All edges but the last one are going from child to parent in the spanning tree. The link L(i, i + 1) from M 7 to M~C+l is given as the sequence segment( e 1), part( el ), segment( e 2), part( e 2) . . . . . segment( e k_ a), part( e k _ 1), seg-

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= ~ b

04

00

Fig. 7. C h a i n i n g t h e m o d u l e s .

ment(ek). In reality, we have to construct the link parallel to this sequence, but for the purpose of simplicity we define a link by giving its sequence of segments and parts. Intuitively, the link from one module to the next on the chain is simply a path parallel to the one in the spanning tree between the two modules (see Fig. 7). Thus, we have the following module chaining algorithm. An example of module chaining is shown in Fig. 7.

Module chaining algorithm (1) Construct the x-visibility graph VG x (2) Use depth-first traversal to obtain a directed spanning tree T of VG~. (3) Perform a pre-order traversal of the tree T to get the ordering of the modules M~, M~ . . . . . M c, on the chain. (4) L(0, 1) = segment(M~, M~); (5) f o r i = l t o m - 1 do begin L ( i , i + 1) = ~b; R=MC; while R # parent( M[+ 1) do begin Let e = (parent(R), R); L ( i , i + 1) = L ( i , i + 1), segment(e), part(e); R = parent(R); end L ( i , i + 1) = L ( i , i + 1), segment(R, M/+I); end Time complexity

Step (1) runs in O(m log m) time. Steps (2) and (3) run in O ( m ) time, because the visibility graph is a planar graph on m + 1 vertices, and therefore has O ( m )

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edges. Step (5) is basically a pre-order traversal of the tree T and also runs in O ( m ) time. Each edge is traversed at most twice in the pre-order traversal. Thus the overall time complexity of the module chaining algorithm is O(m). Number of turns In a pre-order traversal of a tree, the number of edges on a path between successive vertices is either one (when going from parent to first child), or more than one (otherwise). However each edge in the tree appears at most twice in all these successive paths. Thus each line segment appears at most twice in the chain. Also, each part of a module appears at most once in the chain. Thus, the total number of turns in the chain is O(m).

6. Permutation routing In this section, we present an algorithm for generating a planar topological routing, given a chaining of the modules. A pin for each module is selected arbitrarily, which is identified as distinguished. We create a wire for each pin at the appropriate pad in the linear order given by the embedding. These wires are routed parallel to the b o u n d a r y of the chip to the point a0, the intersection point of the chip b o u n d a r y and the first link in the chain of modules. This whole bunch of wires is routed parallel to the chain. The bunch is routed parallel to a link in the chain, and as a module M i is met, the appropriate wire is drawn to connect the distinguished pin on the module. One wire for each of the other pins is created at these pins. These new wires are merged into the bunch. The new bunch is then split into two groups at the old position of the distinguished wire. These two groups go on either side of the module and join again into a single bunch at the starting point of the next link on the chain. The next module on the chain is processed and so on. After the last module is processed, we make the connections between the wires which originated at the pads, and their corresponding new wires which originated at the pins. These connections are made in a region without obstacles, and since we followed the linear ordering of wires at each pad and the ordering of wires at each module, it is guaranteed that these final connections can be made in a simple manner. We now describe the algorithm in more detail. An example of permutation routing is shown in Fig. 8.

Permutation routing algorithm (1) Place a new point a m at an arbitrary place on the b o u n d a r y of the last module M~ on the chain. Consider a m to be the starting point of an imaginary link L ( m , m + 1). (2) Start wires W 1, I,V2. . . . . Wn, one for each of the pins T~, T2. . . . . Tn, from the appropriate pads in the linear order prescribed in the embedding.

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Fig. 8. Permutation routing.

(3) Route these wires parallel to the boundary of the enclosing rectangle M~, to the starting point a 0 of the first link L(0, 1) in the chain. Let S0 = W1, W2,..., W, be the ordered bunch of wires at the point a 0. (4) for j:---1 to m do begin a. Route the bunch Sj_ 1 parallel to link L ( j - 1, j ) from its starting point a / - i to its end point bj_l on the next module My on the chain. b. Let Tsl, Tj2 Tit' be the pins of module My in counter-clockwise order. Choose Tjl as the distinguished pin. Connect the corresponding wire Wsl from bunch Sj_ 1 to this distinguished pin Tjl of module Mr. c. Start new wires Xj2, Xs3 . . . . . Xj,, from the remaining pins ~2, ~3 ,Tit,, respectively, of module My. Let this new sub-bunch be called Zj. Each wire Xs, has to be connected in future to the corresponding wire Wj; which originated at a pad. We refer to these wires at X-wires. d. Route the wires in the sub-bunch Zj, around module My to the starting point aj of the next link in the chain. e. Let Sj_ 1= S~_ 1WjlS~_1. That is, S~_1 is the bunch of wires to the left of the distinguished wire Wj1 and S~_ 1 comprise the wires to the right of this wire. Route wires in S~_ 1 around the side of module Mf to the left of the chain, and bring them to the starting point aj of the next link. f. Route wires in S~_1 around the side of module M; to the right of the chain, and bring them to the starting point aj of the next link. g. Merge the three sub-bunches S~, Zj and S~ together to form a new bunch Sj = S~_1ZjS~_ 1, near the starting point aj of the link L ( j , j + 1). That is, to get S s from Sj_I, we have inserted the sub-bunch Zj in the place of the already connected wire Wj1. end {of for loop} . . . . .

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Wl W2 X4 W4 X2 X9 W~ X6 X~

w~ w~ X4 Wll

Xll wt~, Xl~ w14

Fig. 9. T h e final b u n c h S m.

(5) We have a bunch of wires S,, in the neighborhood of module M~, near the point am. S m is of the following form: am= YI, Y 2 , ' " , Y2(n-m)

where each Y, is either a W-wire or an X-wire (see Fig. 9). There is a one-to-one correspondence between the X-wires and the W-wires in this bunch. X-wires originated at the pins of the modules, and W-wires originated at the pads. We have to show how to connect the corresponding X-wires and W-wires. a. Construct a rectilinear planar drawing of the abstract embedding of the connection graph as follows: Split each pad vertex into as many copies as there are edges incident on the vertex and place these new vertices on a horizontal straight line in the same order as the linear order given in the embedding. Pick any module vertex, and place it in the form of a small rectangle at a suitable position above the horizontal line between its leftmost pad vertex and its rightmost pad vertex. Draw L-shaped lines to connect the module vertex to the copies of the pad vertices it is to be connected with (see Fig. 10). Repeat this procedure sequentially for the remaining module vertices. Note that since we have preserved the linear ordering of the pad vertices, for each module vertex inserted, the copies of the pad vertices that it has to be connected with will all be within a face of the current drawing. Place the module vertex inside this face at an x-position between its leftmost pad vertex and its rightmost pad vertex. Make the L-shaped connections to the appropriate copies of the pad vertices. b. Deform this drawing as follows: Move each module vertex to a point below the horizontal line to the left of the copy of the pad vertex which connects to its distinguished pin, by simply contracting the distinguished

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M'--r ,1 [~M2

Wl~ W2-

-J-M5

~'~'IJI~ ~W7 Wl?"~

W=

I I'1-w'

w.11r

,o

,-WI4

II

P6 Pz P5 P4 P5 Fig. 10. Rectilinear drawing of an embedding. edge and deforming the other edges suitably (see Fig. 11). This is another rectilinear drawing of the same embedding. The arrangement of the edges at the horizontal line is exactly the same as the arrangement of the wires in the final bunch Sm (see Figs. 9 and 11). This is because the algorithm inserts each new sub-bunch Zj originating at the module Mf in the place of the distinguished wire Wj~ of the same module. c. Copy the portion of this drawing above the horizontal line into the routing, to establish connections between the X-wires and the W-wires. Since we assume that the wires can be placed arbitrarily close to each other, there will always be enough empty space in the neighborhood of module M~ for this rectilinear drawing.

Time complexity Step (5) of the algorithm, in which a deformation of a rectilinear drawing of the embedding is used to connect the X-wires and the W-wires can be imple-

X4 -W2--~ Wl--=,.

t~VX9 I ~ -X8

'11

W4

3 Fig. 11. Deformed rectilinear drawing.

'q--Wl4 ~-W13

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mented to run in O(n) time. Note that n is the total number of pins. The time complexity of the first four steps of the algorithm is essentially given by the total n u m b e r of turns created in the routing. There are n W-wires and (n - m) X-wires in the routing. Each wire runs parallel to the links in the chain of modules. The total number of turns in the chain is O(m), where m is the n u m b e r of modules. Thus the total number of turns created in the routing is O ( m ( 2 n - m)), which is O(m x n). This is also the time complexity of the algorithm. Thus, the overall time complexity of the topological routing algorithm is dominated by permutation routing and is O(m x n). Correctn ess To prove correctness we simply have to show that wires are not crossed in permutation routing algorithm. In the first part the algorithm runs wires parallel to each other, and thus no crossings can occur. In step (5), we are simply creating in rectilinear drawing, again without any crossings. The case of two pads In the case when p = 2, that is, there are only two pads (nets), we can simplify the permutation routing part of the algorithm as follows: Start only one W-wire from each pad (independent of number of pins it connects to) and route these two wires parallel to the boundary of the enclosing rectangle to the starting point a 0 of the chain. Route the first wire to the left of the chain and parallel to it. Route the other wire to the right of the chain and also parallel to the chain. Whenever a module is passed, create the necessary connecting wires from these two wires and route them parallel to the sides of the module to the two pins on the module. Continue the routing of the two wires to the next module. Since the two wires are running on opposite sides of the chain, these connecting wires can be created without any crossings. Thus, the total n u m b e r of turns created is only O(m), and the time complexity is dominated by the module chaining part of the algorithm, which is O(m log m). Unfortunately, this technique of using only one wire for each pad does not generalize to the case of three pads. For three or more pads, we have to use one wire for each pin.

7. Extensions and open questions Equivalent pins A subset of the pins of a module are said to be equivalent if they all belong to the same pad net, and we have the flexibility of connecting any of these pins to the corresponding pad. We want to consider such an extension to the basic model, where each module may have sets of equivalent pins. We consider the

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problem of selecting one pin from each set of equivalent pins from each module, so that the resulting connection graph is planar. The selection of different pins from these sets, will result in different connection graphs, only some of which may be planar. It may even be the case that none of these different connection graphs is planar. The main theorem on planarity stated in Section 3 has to be modified to include the case of equivalent pins. It is very easy to observe that, it is enough to modify condition 1 of the theorem as follows: For every module M,, there exists a selection of one pin from each equivalent set, such that M i is consistent with the chain of pads P. Thus step (1) of the planarity testing algorithm of Section 3 has to be suitably extended to check whether there exists a cyclic subsequence of the list of pins Ci of each module M~, such that this subsequence includes exactly one pin from each equivalent set, and in addition the subsequence is consistent with the chain of pads P. A simple linear time algorithm for this subsequence problem can be designed as follows: Consider a module M,. Let Q1, Q2 . . . . . Qr be the sequence of pads, in the order they appear in the chain of pads P, that are to be connected to this module. For each of these pads there is a set of equivalent pins on the module M~. Let C~ be the cyclic list of pins of Mi. To simplify the notation, we label these pins with the name of the pad that they are to be connected with. The subsequence problem reduces to that of testing whether the sequence Q1, Q2 . . . . . Qr can be found as a subsequence in C,, when we make scans through the list C~, starting at each copy of Q1 in C/. In order to implement this in linear time, we will show how this can be done b y going around C~ at most twice. Start the scan at any copy of Q1 in the list C,. For each Qi, 2 ~< i ~< r, we store a pointer to the latest copy of Q1 seen so far in the scan, that expects Q, as the next item in its search for the sequence Q~, Q2 . . . . . Qr. During the scan, when a copy of Q~ is visited, we examine if any pointer is stored under Q~. If yes, then the copy of Q~ that this point points to has now seen Q~, Q2 . . . . . Q~, and it wants to see a Q,+a next. Therefore, we move the point to that particular copy of Q1 from under Q~ to under Q~+1. N o t e that this new point under Q~+1 may now be replacing any old pointer that is already stored under Q,+~. Thus we always keep track of only the latest copy of Q1 that wants to see a copy of Q/+I in its search for the entire sequence. We stop the scan when Qr is seen by some copy of Q~, or when we come back to the last copy of Qa. In the former case, condition 1 of the theorem is satisfied, and in the latter case, it is not. We leave the correctness proof as an exercise to the interested reader. Clearly, we scan the list C~ at most twice, and the time complexity is linear in the number of pins of M~. If all the modules pass this new consistency test, then we have selected one pin from each equivalent set, such that the modules are consistent with the chain P. We take the resulting connection graph and apply the steps (2)-(6) of the planarity testing algorithm of Section 3. The topological routing algorithm is exactly the same as before. We have assumed that the power and ground nets are not allowed to be routed over the modules. This will indeed be the case when we have a hierarchical structure for power and ground routing. In such a situation, the interior of the modules are to be used for routing power and ground nets from the pins of the modules to the b o u n d a r y of the next lower

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level cells in the hierarchical structure. The algorithms described in this paper can be hierarchically applied at each level.

Over-the-module routing Suppose we want to allow the routing of power and ground nets over the modules without any restrictions. That is, the nets are allowed to cross the module boundaries between adjacent pins. In the connection graph, the pins will be represented as separate vertices, which have no edges between them. Thus the underlying connecting graph will be a ring of pads connected to an independent set of pins. Such a graph is always planar. If we have equivalent pins, any one of these pins may be selected, and the connection will still be planar. It is as if each pin is taking the part of a module in the original problem, and the topological routing algorithm can be applied as before.

Detailed routing We now list some open questions regarding the detailed routing that must follow the topological routing algorithm presented in this paper. 1. When the set of pad nets includes multiple power and ground nets, the detailed routing of power and ground nets needs the ability to handle variable widths and be able to control the total lengths of these nets. A detailed routing algorithm similar to [5] can handle variable width wires, but it is an open question as to whether it can be modified to perform detailed routing, with upper bounds on the lengths of some of the wires given. 2. Another interesting problem arises when no feasible detailed routing exists for a given topological routing and placment of modules and pads. This m a y be due to congestion of wires in certain regions between the modules. However there may be a different planar embedding and topological routing that may lead to a feasible detailed routing. The question is how to bring the detailed routing constraints into the planarity testing and topological routing algorithms. 3. The detailed routing algorithm of [5] is designed for general planar routing of nets between modules. It is an interesting question as to whether the results and algorithms of [5] can be simplified for the case of routing only pad nets.

Acknowledgements We wish to thank Howard Chen, Martin Kolinek, David LaPotin, and Don Tang for several discussions on this research.

References [1] B.S. Baker and R.Y. Pinter, An Algorithm for the Optimal Placement and Routing of a Circuit within a Ring of Pads, Proc. 24th Syrup. Foundations of Computer Science, pp. 360-370, November 1983.

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[2] M. Cutler and Y. Shiloach, Permutation layout, Networks 8 (1978) 253-278. [3] J.E. Hopcroft and R.E. Tarjan, Efficient planarity testing, J. ACM 21 (4) (October 1974) 549-568. [4] E. Kuh and X-M. Xiong, The scan line approach to power and ground routing, Digest of Technical Papers ICCAD-86 (November 1986) 6-9. [5] F.M. Maley and C.E. Leiserson, Algorithms for routing and testing routability of planar VLSI layouts, Proc. 17th ACM Syrup. Theory of Computing, pp. 69-78, May 1985. [6] M. Marek-Sadowska and T.T.K. Tarng, Single-layer routing for VLSI: Analysis and algorithms, IEEE Trans. Computer-Aided Designs of Integrated Circuits and Systems CAD-2 (4) (October 1983) 246-259. [7] A.S. Moulton, Laying the power and ground wires on a VLSI chip, Proc. 20th Des. Aurora. Conf., pp. 754-755, June 1983. [8] R.Y. Pinter, The impact of layer assignment methods on layout algorithms for integrated circuits, Ph.D. dissertation, Department of EECS, M.I.T., Cambridge, August 1982. [9] M. Schlag, F. Luccio, P. Maestrini, D.T. Lee and C.K. Wong, A visibility problem in VLSI layout compaction, F.P. Preparata, ed., Aduances in Computing Research (VLSI Theory) 2 (1984) 259-282. [10] Z.A. Syed and A.E. Gamal, Single layer routing of power and ground networks in integrated circuits, J. Digit. Syst. VI (1) (1982) 53-63.