Porous Silicon Based MEMS

Chapter 23

Porous Silicon Based MEMS Gerhard Mu¨ller1, Alois Friedberger1 and Kathrin Knese2 1

EADS Innovation Works, Mu¨nchen, Germany, 2Robert Bosch GmbH, Automotive Electronics, Reutlingen, Germany

23.1 POROUS SILICON BACKGROUND Porous silicon (PS) was first discovered by accident in 1956 by Uhlir Jr. and Ingeborg at the Bell laboratories when developing surface-polishing procedures for silicon and germanium wafers [1]. This early work was considered a failure as it was found that the silicon was not removed in a layer-by-layer fashion. Rather, a sponge-like structure formed at the silicon surface. Depending on preparation conditions, pore diameters ranged from a few nanometers up to about one micrometer. A first application of PS was in the field of silicononinsulator (SOI) technology [2,3]. There, Si wafers were made porous at the top surface and epitaxial silicon was grown on top of the PS layers. Subsequent oxidation of the PS formed thick SiO2 layers that insulated the epitaxial layers from the substrates. Renewed interest in PS was raised in the late 1980s when it was argued that PS might display quantum confinement effects. Soon thereafter, Leigh Canham [4] and, independently, Lehmann and Go¨sele [5] showed that nanoporous silicon (NPS) exhibits an efficient orange photoluminescence when illuminated with UV light. This discovery generated an explosion of interest in NPS, as NPS technology seemed to offer a road toward silicon light-emitting devices. Several books and review articles have since been devoted to this subject [6,7]. Whereas quantum confinement effects arise out of the constrained geometry of the lamellae that separate neighboring pores in the NPS, NPS has also attracted attention because of the pores themselves. This internal pore structure in NPS leads to an enormous internal surface area which may range up to 800 m2/cm3 [8]. Together with the constrained geometry of the pore-separating lamellae, this makes NPS an extremely surface-dominated material. This surface sensitivity has relevance for applications in the realm of catalysis [9,10], fuel cells [11], as well as in the field of physical [12], chemical [13], and gas sensors [14,15]. Very likely, the discovery of “explosive porous

silicon” [16] is the most striking demonstration of the surface reactivity in NPS. Last but not least, the dense network of interpenetrating pores makes NPS a heterogeneous twophase material with interesting optical properties. Optical interference filters [17,18] and antireflection coatings for solar cells [19] are applications that build on this heterogeneous two-phase structure.

23.2 PS SACRIFICIAL LAYER TECHNOLOGIES Whereas the above lines of research all build on fundamental and applied interests in the material properties of the PS itself, NPS has also attracted attention due to its potential as a sacrificial layer material. This latter line of research was motivated by the fact that PS formation is sensitive to the doping profiles that can be created inside silicon wafers. Secondly, once formed, it was found that PS layers can be easily removed from the remaining bulk silicon by using dilute chemical etches which easily attack the PS but leave the remaining bulk silicon intact. These properties opened up a range of possibilities for generating three-dimensional (3D) microstructures in bulk silicon [12,18]. Several types of microsensors and microactuators have since been realized with the help of PS technologies. More recently, macroporous silicon (MPS) has attracted major interest as a microstructuring technology as well [20,21]. MPS can be formed in n-type silicon under illumination, yielding long, straight pores with pore diameters and wall thicknesses in the micrometer range. A trigger for this interest was the observation that large regular arrays of macropores can be formed by lithographic pore initiation. This possibility seems to be most promising for the formation of two-dimensional and 3D photonic crystals [22] and for the fabrication of microfluidic devices [23
25].

Handbook of Silicon Based MEMS Materials and Technologies. DOI: http://dx.doi.org/10.1016/B978-0-323-29965-7.00023-3 © 2010 Elsevier Inc. All rights reserved.

503

504 PART | IV Micromachining Technologies in MEMS

FIGURE 23.1 Thermal flow sensor with heatable silicon carbide (SiC) bridges before (left) and after (right) removal of the NPS sacrificial layer [24].

4.2 μm

With regard to other bulk and surface micromachining technologies which can be applied to silicon, the distinguishing features of PS sacrificial layer technologies are as follows: G

G

G

G

G

G

microstructure geometries can be defined by the lithographical design of masking layers; the lateral PS profile is determined by the shape of electrical field lines during PS processing rather than by crystallography; the etching of the silicon substrates can be confined to the front side of the silicon wafers; that is, protection wafers for the rear side of the micromachined wafers are not required; the vertical extent of the micromachined structures can be varied over a large range extending from nearsurface up to bulk silicon microstructures; the micromachined structures consist entirely of lowstress bulk crystalline silicon; the use of hydrofluoric acid (HF) as an etching agent guarantees enhanced CMOS compatibility.

FIGURE 23.2 Regular array of macropores formed in n-type silicon under illumination. The modulation of the pore width was achieved by varying the illumination intensity during pore etching [25]. r Wiley-VCH Verlag GmbH & Co. KGaA. Reproduced with permission.

Figures 23.1 and 23.2 show some representative silicon microstructures that have been formed using NPS and MPS technologies.

23.3 PS FABRICATION TECHNOLOGY PS forms when silicon is immersed in HF under conditions of current flow. A first arrangement that can be used to form PS is shown in Figure 23.3 [26]. There, the Si wafer to be treated separates a volume of HF, forming a double-cell arrangement. The electrolyte in each cell is contacted by a platinum (Pt) grid. Both grids are connected to a potentiostat, and a current is forced through the double-cell arrangement. For proper operation it is important that the two half-cells are contacted exclusively through the Si wafer and that any leakage currents around the wafer are avoided. Such conditions can be attained by O-ring seals along the periphery on both sides of the wafer.

Porous Silicon Based MEMS Chapter | 23

FIGURE 23.3 Electrochemical double-cell arrangement for PS formation: (left) Cell architecture; (right) Equipment photograph. Sapphire windows allow for an optional front- or rear-side illumination.

Electrolyte level

Electrical contact

HF

505

HF Sealing

Pt Electrode

Sapphire window

Silicon wafer

Etching

FIGURE 23.4 I
V characteristics produced by the double-cell arrangement shown in Figure 23.3. As the rate of PS formation depends on the current density through the wafer, biasing at a voltage V0 B 0.5 V, p, p1, and n1 wafers can be anodized, while moderately doped n-Si remains largely intact.

Passivation

100

– – – – – – – HF PS formation

+ – + – + – + – + – + – + Si – HF

J (mA/cm2)

80

+ + + + + + +

n+

n n

p+ p

60 40 20

Electr. contact through implantation or illumination

p-Si

0 –0.5

0.0

0.5

Electrolyte

+

2.0

n-Si

– + +

1.0 1.5 V (Volt)

2.5

3.0

Electrolyte

– –

+

–

+

p+-Si

n+-Si

Electrolyte +

+

Electrolyte – – –

–

– + + +

FIGURE 23.5 Band-bending profiles developing at the anode side of p, p1, n, and n1 wafers.

When Si wafers are immersed in HF/H2O electrolytes, quasi-Schottky barriers form at both interfaces [27,28] and nonlinear current-voltage characteristics emerge. Typical I
V characteristics are shown in Figure 23.4. These demonstrate that the form of the I
V characteristics sensitively depends on the kind and concentration of dopant impurities in the Si wafers.

The form of these I
V characteristics can be qualitatively explained in terms of the band-bending profiles that develop at the anode side of the wafers (Figure 23.5). The characteristics above can be understood by way of example. Considering the case of a p-type wafer, the current inside the wafer is supported by electronic holes (h1). On the anode side of the wafer, that is, the side

506 PART | IV Micromachining Technologies in MEMS

Pt grid electrode

Temp. sensor Front-side contact Rear-side contact

Air

HF

Si wafer

Au contact

Sapphire window

FIGURE 23.6 Single-cell arrangement for PS formation.

facing the negatively biased Pt grid, the electronic holes emerge at the free surface and discharge F2 ions which abound in the liquid electrolyte: F2 1 h1 -F

(23.1)

The neutral F atoms, in turn, corrode the silicon surface by breaking Si
Si bonds and by forming Si molecular ions which can dissolve in the liquid electrolyte: 2F 1 Si 1 4HF-H2 SiF6 1 H2

(23.2)

The opposite side of the wafer, which faces the positively biased Pt grid, stays intact. There, H3O1 ions are discharged upon interaction with the Si surface by trapping valence electrons, thereby forming H2O and H2: H3 O1 1 e
-H2 O 1 1/2 H2

(23.3)

As this rear contact ultimately has to supply the holes that are needed to sustain the PS formation process at the anodic side, it is important to a make good Ohmic contact to the cathodic wafer side. This can be accomplished by performing a p1 contact implantation prior to the PS formation. Alternatively, blue-light illumination can be used to reduce the contact resistance. In order to allow illumination during processing, the electrochemical cell in Figure 23.3 is equipped with two transparent and HFresistant sapphire windows. Similar considerations obviously apply for p1 wafers. In n-type wafers PS formation cannot proceed in the dark, as such wafers hardly contain any electronic holes

that could neutralize F2 ions and thus initiate a PS formation process. In n-type wafers PS can only be formed when holes are photo-generated. In this case the photo-generated holes are attracted to the solid/liquid interface on the anodic side by the upward band bending that exists there. n1 Silicon is exceptional insofar as PS formation can proceed there also in the dark. The reason is that the band-bending profile at the anodic surface of the n1 Si is so steep that it becomes transparent to electron tunneling. Adsorbed F2 ions therefore can discharge and thus become chemically active by injecting their excess electron into the Si conduction band. Further considering the fact that in all cases considered above, it is only H3O1 ions that are discharged at the cathodic side with no chemical reaction taking place on the Si side, less complex single-cell electrochemical arrangements can also be used. As shown in Figure 23.6, such arrangements only expose the anodic side of the wafer to the HF, whereas electrical contact to the cathodic side of the wafers is made via standard metallic contacts. Attaining Ohmic backside contacts again requires a p1 contact implantation and a metallization step prior to the PS formation.

23.4 MICROSCOPIC PROCESSES UNDERLYING PS FORMATION In order to arrive at a deeper understanding of the electrochemical processes that lead to the formation of PS, it is

Porous Silicon Based MEMS Chapter | 23

Energetics of silicon/Electrolyte contact (HF / H2O)

Simplified band diagram Contact with p-type Si

Vacuum level 0eV Conduction Conduction band band

+ H3O+ / H2O

4.05eV 5.17eV

+

+

Silicon

4.5eV

1.12eV

Eredox

EF

Electrolyte

507

FIGURE 23.7 (left) Positions of the conduction and valence band edges in silicon and of the electrochemical potential in a strongly acid HF/H2O electrolyte relative to the vacuum level Evac; (right) form of the surface band bending in p- and n-type Si after immersing the silicon wafers and after establishing thermal equilibrium between silicon and liquid electrolyte.

Contact with n-type Si Valence band

F2 / 2F– 7.35eV

Silicon

Electrolyte

Eredox EF

Silicon

important to consider the energetic conditions that prevail at the solid
liquid interface. On the solid side, the relevant electron energies are the conduction and valence band edges, Ec and Ev, and their positions relative to the vacuum energy, Evac. The relevant energetic parameters on the liquid side are the electro-chemical potentials of the H3O1/ H2O and the F2/2F2 redox couples. In a strongly acid electrolyte like HF/H2O, the electrochemical potential is roughly at a position 4.5 eV below Evac (Figure 23.7). With Eredox at this level, all the fluorine atoms in the liquid are completely converted to F2 ions, and a significant fraction (B1 mol/L) of the H2O molecules abounds in its positively ionized form H3O1. Turning to the solid side of the junction, we note that Eredox is roughly halfway in between the conduction and valence bands; that is, it coincides with the intrinsic position of the Fermi level in silicon. This means that forming an actual contact between a silicon wafer and an HF/H2O electrolyte, the direction of the charge exchange across the solid/liquid interface and therefore the direction of the band bending, depends on whether the wafers are n- or p-type. Establishing thermal equilibrium between solid and electrolyte, the Si band edges therefore will bend downwards at the surface of p-type wafers and upwards in n-type wafers. In order to understand PS formation, the chemical bonding at the silicon surface needs to be considered. Creating a crystallographic surface by cleaving involves cutting covalent bonds and thus creating a layer of dangling, that is, unsaturated bonds at the cleavage surface. On a free surface most of these dangling bonds will reunite, forming weak bonds as indicated in Figure 23.8. Given the strong directionality of the silicon sp3 bonds, it is clear that the reconstructed Si
Si bonds will be relatively weak and therefore likely to break. Once broken,

Electrolyte

these form pairs of dangling bonds. Dangling bonds in turn form localized electronic states in the bandgap which can easily communicate with the extended electron states in the conduction and valence bands. In the course of such charge exchange interactions, the surface dangling bonds may acquire either of three charge states: positive, neutral, or negative. Which of these states predominates depends on the electron availability, that is, on the position of the Fermi energy at the Si surface. The charge on the dangling bonds in turn determines in which way the unsaturated surface bonds can interact with the charged or neutral molecular constituents in the liquid electrolyte. These possibilities are displayed in Figure 23.9 considering the cases of an n- and a p-type Si surface. The actual dissolution process that breaks out silicon atoms from the surface is sketched in Figure 23.10. This latter picture shows that a silicon ionic species that may become dissolved in the liquid electrolyte is formed once the two dangling bonds on a single surface Si atom become terminated by two fluorine atoms. The two strong Si
F bonds destroy the sp3 hybridization of the surface atom, and an Si
F2 molecule is released into the liquid electrolyte. Due to its strongly positive redox potential, the SiF2 acquires two electrons from its chemical environment, becoming ultimately dissolved in the liquid electrolyte. Recognizing the fact that F-termination of Si dangling bonds precedes Si dissolution into the liquid electrolyte, we note from Figure 23.9 that there is a very clear asymmetry in the number of Si
F bonds at the solid
liquid interface when we consider p- and n-type surfaces. Because of the predominant positive surface charge at p-type surfaces, such surfaces are much more attractive to Si
F bonding than n-type ones. p-Type surfaces, therefore, become rapidly attacked in HF/H2O electrolytes,

508 PART | IV Micromachining Technologies in MEMS

z

z

z

a

a

a

a

a y

a

a y

a

[1,0,0]

[1,1,0]

x

[1,1,1]

x

Si Si

Si Si

y

a x

Si Si

Si Si

[100] Si

Si Si

[111]

Si Si

Si Si

[110]

Si

Si

Si Si Si Si Si Si Si FIGURE 23.8 Bond reconstruction at the three major crystallographic planes of silicon.

– EC

EC Si+ + F–

→ Si–F

D+

Si+ + F– → Si–F

D+ Si0 + HF → Si–F+½H2 Si0 + HF → Si–H+½ F2

D0

Si0 +HF → Si–F +½ H2 Si0 +HF → Si–H+½F2

D0 D–

D– Si– + H3O+ → Si–H+H2O

EV

Si– + H3O+ → Si–H +H2O

EV +

FIGURE 23.9 Schematic densities of band and dangling bond states at the surface of n-type (left) and p-type Si (right). The energetic positions of the differently charged dangling bond states have been displaced from each other for ease of graphical presentation. The relative numbers of positive, neutral, and negative dangling bond states depend on the surface Fermi energy. The electronic charge of the dangling bonds in turn determines how these states may interact with the positive, neutral, and negative molecular constituents of the liquid electrolyte.

H evolution

SiF2 2– + 4HF

H2SiF62– + H2

Dissolved ions

F Si Si

+

F Si

Si

Si Si

Si

+

Hole induced bond breaking

FIGURE 23.10 Molecular mechanism of Si dissolution in HF/H2O liquid electrolytes.

whereas n-type surfaces tend to stay intact. The other point apparent from Figure 23.10 is that positive surface dangling bonds are consumed in the dissolution process. Maintaining a thermal equilibrium between positively charged, neutral, and negatively charged dangling bonds therefore requires a resupply of two holes to the newly emerging surface dangling bond sites, that is, a hole current to flow through the Si wafer to keep the etching process going. Considering Figure 23.10, it is a striking fact that—on an atomic scale—the PS formation process and the process of anisotropic silicon etching in alkaline solutions look fairly similar. The common aspect is that individual Si atoms are liberated from the solid surface by terminating the emerging surface dangling bonds either by F2 or

Porous Silicon Based MEMS Chapter | 23

400 J (mA/cm2)

Low current density: Etching limited by availability of holes → pore growth

300

High current density: Etching limited by availability of F– ions → electro-polishing

Jep

200 Electro-polishing

100

509

0.5 1.0 1.5 2.0 V [Volt] +

F– F– F–

F– – F F– + – F + F– – F + F– F– F– F–

+ F

+

–

+ + +

+

+ +

+

F– + F–

FIGURE 23.11 Focusing of electrical field lines at randomly forming irregularities at the silicon surface. Depending on the relative abundance of F2 ions (low bias voltage) or electronic holes (high bias voltage) either pore formation or electro-polishing is observed [29,30].

by OH2 ions, respectively. Whereas PS formation is an isotropic process, KOH etching is very sensitive to the surface orientation and thus anisotropic. The isotropic nature of the PS formation process can be traced back to three important differences: 1. Si
F bonds are stronger than Si
OH ones. Si
F surface bonds therefore influence the sp3 electron configuration of the surface Si atoms much more heavily than Si
OH ones. As a consequence, the Si
Si back bonds, which keep the surface Si atoms connected to the Si bulk, are destabilized to a much larger extent in HF/H2O electrolytes as compared to alkaline ones. 2. In an alkaline electrolyte the electrochemical potential is at Evac 5 23.7 eV. As a consequence the surface Fermi energy is pinned at a position close to the conduction band edge. Most of the surface dangling bonds will therefore attain a negative charge and thus will be unlikely to form Si
OH bonds. In acid HF/H2O electrolytes, on the other hand, the surface energy is pinned at around midgap. The much larger number of positive surface dangling bonds largely enhances the probability of forming two destabilizing Si
F bonds at the same surface Si site. 3. In contrast to alkaline KOH etching, PS formation is a current-driven process. Randomly forming perturbations of the originally planar etch front tend to focus electrical field lines, thus supplying more charge carriers to these irregularities. Depending on the electrical bias, this can either result in pore formation or in electro-polishing. The process of current focusing is essential for an understanding of pore formation in PS and thus sketched in more detail in Figure 23.11 [29,30].

The remaining question is what determines the pore size and the thickness of those lamellae that separate neighboring pores. In the early days of PS research two limiting cases were discussed. These relate to (i) quantum confinement and (ii) to space charge limitation. These elementary models explain certain limiting cases as, for instance, NPS formation in p-type Si [5,31,32] or MPS formation in illuminated n-type Si [33,34], but need to be complemented by further details to explain more complex features as, for instance, macropore formation in unilluminated p-type Si [35]. Turning to NPS formation in p-type Si first, the process limiting the lamella width is believed to be an inherently quantum mechanical one (Figure 23.12). Whereas current focusing at the pore tips drives pore formation into the direction of the electrical field lines, the isotropic nature of the dissolution process tends to widen the emerging pores laterally. This lateral growth stops when the thickness of the remaining lamellae has been reduced to the nanometer range. At this dimension, quantum confinement effects set in that widen the band gap in the lamellae regions, resulting in a reduced supply of electronic holes to the lateral pore walls. A different situation arises during the photoelectrochemical etching of n-type wafers. Forming macropores in n-type Si, the wafers are illuminated from the backside and photo-generated holes are attracted to randomly forming or intentionally initiated etch pits at the front side. There, current focusing again favors etching at the pore tips. Etching of the pore walls is less efficient due to the current focusing at the pore tips and the highresistivity space charge zones that develop inside the pore walls. Wall etching is considered to seize when the lamella thickness has shrunk to twice the depletion layer

510 PART | IV Micromachining Technologies in MEMS

Passivation layer

Etch hole

Noble metal, a-SiC:H, ß-SiC Poly-Si / Si3N4 Poly-Si, n-Si

NPS

p-Si p+-Si FIGURE 23.14 Formation of spatially confined NPS sacrificial layers in a p-type Si substrate.

Ec

PS

Bulk Si +

+

+

Ev

lattice constants in the range between 0.5 and 8 μm can be realized with the aspect ratio of the macropores reaching values in the order of 100
500. Furthermore, as the diameter of the emerging pores depends on the supply of photo-generated holes to the pore tips, variations in the backside illumination may be used to modulate the pore diameter as the pores grow.

FIGURE 23.12 Limitation of lateral pore growth in p-type Si due to quantum confinement effects in the lamellae regions [31].

Electrolyte Depleted silicon +

+

+

+

Bulk n-type silicon –

–

–

–

Backside illumination

FIGURE 23.13 Photo-electrochemical pore etching in backsideilluminated n-type wafers [28].

width. As the extent of space charge zones in moderately doped n-type regions is in the order of micrometers, much larger pores and thicker lamellae develop in n-type material (Figure 23.13). An interesting aspect of the MPS process is that lithographical prestructuring can be used to define those spots on the surface where macropores will ultimately start to grow. In this way regular arrays of pores with a defined lattice constant can be formed (see Figure 23.2). Due to the space-charge-limited passivation of the pore walls,

23.5 FORMATION OF SILICON MICROSTRUCTURES 23.5.1 Structure Delineation 3D structures in bulk silicon can be formed when the process of PS formation is confined to specified areas of the Si wafers. The most straightforward way of forming spatially confined PS sacrificial layers is to use p-type Si substrates and to confine the process of PS formation laterally by employing photo-lithographically structured masks on the wafer surface. This process is illustrated in Figure 23.14. There, it is also indicated that a wide choice of materials can be used to limit the PS formation process to the desired regions. In principle, any kind of material can be used that can be deposited onto silicon and that can withstand the aggressive chemical environment of a HF/H2O electrolyte. Materials of choice are noble metals [36], dielectric materials (hydrogenated amorphous silicon carbide, a-SiC:H) [37], silicon-compatible multi-layer films (e.g., poly-Si/Si3N4) [38,39], semiconductor thin films (β-SiC [24], n-type poly-Si (P. Kreisl, private communication), n-type epitaxial Si [40,41]) and, last but not least, p-type [42] and n-type bulk Si [26,43]. In the past all these possibilities have been used to realize silicon devices. Very often, combinations of such materials had to be used to arrive at a reliable passivation of those areas which needed to be protected against an electrochemical attack. We will come back to a discussion of such passivation aspects after having reviewed the basics of the structure delineation in bulk Si wafers.

Porous Silicon Based MEMS Chapter | 23

p-Si wafer

1. Mech. structure delineation; n-implantation into p-Si

2. Deposition passivation layers; protection n-implantation during PS formation

Standard front-end process module

511

FIGURE 23.15 Modularization of a sensor or an actuator fabrication process into a CMOS-compatible front-end and a device-specific back-end process.

Sensorspecific back-end process module 3. PS sacrificial layer formation

4. Functional layer deposition

5. Sacrificial layer removal

The attraction of such PS sacrificial layer technologies relates to the fact that PS layers can be formed after a CMOS-compatible preprocessing of the silicon wafers. This kind of preprocessing can be carried out in all kinds of silicon foundries. Secondly, the PS sacrificial layer technology holds the potential that—after the PS formation—there is still a flat wafer surface that allows a number of application-specific, thin-film, and lithography steps to be carried out. As shown in Figure 23.15, the removal of the PS sacrificial layer belongs to this application-specific back-end of the process sequence. A subdivision of the entire process sequence into a CMOS front-end and an application-specific back-end is an important prerequisite in enabling technically and economically feasible cooperations of silicon foundries and high-tech SMEs active in specialized fields of sensor and actuator technology. Returning to the problem of confining PS formation to mask-defined regions, we note that bulk silicon has excellent mechanical properties and that PS formation is sensitive to the doping level in bulk silicon. Building on this fact, Bischoff et al. [26,44] have devised a number of processes that allow forming 3D silicon microstructures consisting entirely of bulk Si by forming doping profiles in the surface and subsurface regions of Si wafers, using ion implantation and drive-in procedures. These processes are sketched schematically in Figure 23.16. The general idea behind these processes is that silicon will dissolve electrochemically, once electronic holes are constantly supplied to certain parts of the Si/liquid electrolyte interface. The first process (a) is one of the possible realizations of the basic micro-structuring process displayed in Figure 23.14. With this process PS etch depths up to 20 μm were reached under constant-current conditions. At this point the n-type surface layers started

to corrode as well due to changes in the bias conditions that developed inside the wafer as the PS formation was driven toward larger depths. Using a process variant that keeps the surface potential of the n-type surfaces constant, much larger etch depths of the order of 160 μm were obtained. The other three processes (b, c, and d) are photovoltaic processes. In these processes the preprocessed silicon wafers simply need to be immersed into the liquid electrolyte and illuminated with above-bandgap light. The built-in junction fields then separate the photo-generated electron-hole pairs, causing a fraction of them to diffuse to the differently doped surface regions. With p- and ntype surface regions collecting charge carriers of different signs, electrical fields automatically develop at the wafer surface that keep the electrochemical corrosion process going. With the p1/p process shown in Figure 23.16(b), recesses in the silicon wafer up to 6 μm in depth could be formed. With the npn process in Figure 23.16(c) arrays of 300-nm thick Si cantilevers over 4-μm-deep recesses were formed. The photo-electrochemical np process, finally, allowed arrays of 300-nm Si cantilevers over 90-μm-deep grooves to be formed (Figure 23.16(d)). On the whole, these experiments revealed that suitably shaped doping profiles in Si wafers may be used to produce 3D microstructures. The obtainable vertical dimensions of these structures could be varied over a range extending from those typical of surface up to bulk micromachining. As the process of PS formation is a largely isotropic one, vertical and lateral etch processes proceed at a similar rate. A perforation of the surface masking layers therefore needs to be considered when structures with large lateral extent need to be undercut. This problem is visualized in Figure 23.17. Another approach toward undercutting large lateral structures was undertaken by Zeitschel et al. [37]. These

512 PART | IV Micromachining Technologies in MEMS

(a)

Illumination

(b)

Passivation layer

Etch hole

n-Si p+-Si

NPS

+ +

–

+ +

–

–

–

p-Si

p-Si

p+-Si Illumination

(c)

–

n+-Si – + + – + p-Si + –

n-Si

Illumination

(d)

p-Si –

–

–

+ +

–

– + n-Si

–

+

–

–

+ +

n+-Si FIGURE 23.16 Processes for forming 3D Si microstructures using ion implantation and drive-in processes to delineate areas of electrochemical or photo-electrochemical attack [26,44].

FIGURE 23.17 (Left) Platform consisting of n-type silicon as formed by the process displayed in Figure 23.16(a); (right) perforation as a tool for undercutting large laterally extended structures.

latter authors exploited the fact that the PS formation process tends to follow the direction of the electrical field lines inside an Si wafer. In order to produce electrical field lines inside an Si wafer that drive the etch fronts into lateral directions the back surface of a p-type wafer was isolated by means of an n1 implantation. Ohmic p1 backside contacts were only formed in those positions directly underneath an extended platform structure that had been delineated at the front surface using an n-type implantation. The electrical field line distribution in such wafers and the resulting effects of field focusing on the etch progress are shown in Figure 23.18. From the crosssection through an incompletely processed device the etch fronts can clearly be seen progressing from the peripheral

p-type access holes at the front surface toward the p1 back-surface contact holes. Further evidence for an electrical field line guided process can be obtained from the optical micrograph that has been taken on the back surface of a fully processed platform that had been broken free from its Si suspensions. An important extension of the base process sketched in Figure 23.16(a) is that active electronic functions can be integrated into free-standing silicon structures such as hotplates, cantilevers, etc. This possibility emerges from the fact that p-type regions embedded into an n-type well are electrically insulated from the bulk p-Si wafer by a reverse-biased pn junction field. An etch process at the surface of the embedded p-type regions therefore cannot be sustained. A result obtained on a bidirectional thermal mass flow sensor with a central heater meander and upstream and downstream pn-junction temperature sensors is shown in Figure 23.19. The embedded pn junctions exhibited diode ideality factors of n 5 2, indicating the dominance of recombination limited diode currents.

23.5.2 Passivation Layers The results above demonstrate how doping profiles in the subsurface regions of preprocessed Si wafers can be used to guide the PS formation process inside Si wafers to form 3D microstructures with embedded electronic devices. The example in Figure 23.18, in particular, has shown that in

Porous Silicon Based MEMS Chapter | 23

Current

513

Current n - Si

p - Si

Current FIGURE 23.18 Electrical field line focusing in a p-type wafer (left); lateral etching under conditions of field line focusing (middle); backside of a fully processed n-type Si platform revealing four converging etch fronts (right).

106 p-Si

n-Si

104 J/Js

n-Si

102

NPS p-Si

1 102

p+-Si

0

0.2 0.4 0.6 0.8 1 VB (Volt)

1.2 1.4 1.6

FIGURE 23.19 pn Junction embedded into an n-type passivation layer: (left) doping profile; (middle) realized device structure; (right) IV characteristics of embedded diode.

principle very large undercuttings are possible without employing dense patterns of perforation holes. Aiming at a high process yield, the above pn junction techniques need to be supplemented by more elaborate surface passivation techniques. The need for such supplementary passivation technologies arises out of the following problems and necessities: G

G

G

Using unprotected n-type regions, large vertical and lateral etch depths cannot be reached. The reason is that etch rates in the order of a few micrometers per minute require cell voltages that significantly exceed the turn-on voltages of Si pn junctions (B0.6 eV). Under such conditions n-type layers tend to become corroded as well. In case active electronic functions such as pn junctions are to be integrated into free-standing Si bridges, highly doped p1 and n1 regions are required which extend up to the free surface. When directly exposed to HF/H2O electrolytes, such regions tend to etch with a high rate. An extra protection therefore is required. In case MOS capacitors and field effect transistors are to be integrated, gate and field oxides need to be protected against the aggressive liquid electrolyte.

As PS formation occurs under conditions of current flow, an obvious choice for improved passivation layers would be using electrically insulating dielectric layers.

Standard oxide and nitride dielectric layers, in common use in the CMOS technology, however, are readily dissolved in HF/H2O electrolytes. A promising way out, however, was the discovery that hydrogenated amorphous silicon carbide (a-SiC:H) is highly resistant to HF [37]. Such layers can be deposited in plasma-enhanced chemical vapor deposition (PECVD) reactors at moderate deposition temperatures at around 300
350 C [45], containing high concentrations of bonded hydrogen [46]. With regard to bulk Si, such passivation layers possess a high level of built-in compressive stress, which can be lowered by thermal annealing and Heffusion. Soon after this discovery such layers were employed as masking materials in the PS sacrificial layer technology [30,47]. Lang and co-workers successfully demonstrated the fabrication of bolometers and thermal mass flow sensors, using the PS technology. The benefit obtained using a-SiC:H passivation layers instead of pn junction passivation techniques is shown in Figure 23.20. Whereas pn junctions readily fail as the wafer-internal bias voltage becomes more anodic than 0.6 V, the a-SiC:H layers can easily withstand higher voltages because of their much larger bandgap (B2.5 eV). Significantly higher voltages and larger etch rates in p-type materials can therefore be employed without a residual attack on the n-type regions. Although being successful for small undercuttings and short PS formation times, a-SiC:H passivations showed a

514 PART | IV Micromachining Technologies in MEMS

p-Si

p-Si n-Si

n-Si

HF/H2O

HF/H2O

+

p-Si

+

HF/H2O –

–

F–

a-SiC:H

p-Si n-Si

FIGURE 23.20 (left) pn junction passivation under zero-bias (top) and anodic bias (bottom) conditions; (right) a-SiC:H passivation layer on top of a conventional pn junction passivation structure under anodic bias (top); a-SiC:H passivation as deposited on top of an n1 Si contact region.

a-SiC:H

n-Si

HF/H2O F–

+

–

n+-Si

FIGURE 23.21 (left) Mask design for an a-SiC:H passivation layer for enabling a large lateral underetching underneath an n-type platform structure. Two surface n1 regions for enabling contacting and heating of the hotplates can be seen in the periphery and extending into the four Si suspensions; (right) fully released Si platform showing flaws in the a-SiC:H passivation layer after very long processing in HF/H2O.

tendency to fail once very long PS processing times in the order of several hours under high bias conditions were used. As shown in Figure 23.21, such flaws, in general, were initiated in those areas which covered n1 regions on the Si wafer surface. Friedberger et al. [48] suggested that this problem is due to electron tunneling through the many localized bandtail states that abound in the amorphous aSiC:H films. This process, which is indicated in the bottom right-hand side of Figure 23.20, makes a-SiC:H accessible to a residual electrochemical attack. Once pinholes have been formed in the a-SiC:H, the underlying n1 Si layers are rapidly degraded, causing the a-SiC:H to lift off. A fully satisfactory solution with regard to passivation was found by Friedberger et al. [48]. These latter authors developed a double-layer passivation technique that consistently uses thin films belonging to the standard repertoire of CMOS lines. These double layers consist of Si3N4, which is highly insulating but only moderately stable in HF, and polySi, which is stable in HF but unstable in case of an additional current flow. In their passivation technique both layers cooperate in that the poly Si protects the underlying Si3N4 against the HF and in that the insulating Si3N4 prevents a current flow through the topside poly-Si layer. The electronic

p-Si

n-Si / n+Si

Si3N4/Poly-Si Electrolyte –

+

– –

– + + +

+

FIGURE 23.22 Band bending profile through a poly-Si/Si3N4 passivation layer deposited on top of an implanted n/n1 region at the surface of a p-type wafer. A current flow through the nitride layer is safely inhibited under anodic bias.

performance of such passivation layers is demonstrated in Figure 23.22. With regard to a-SiC:H, the better performance of this double-layer passivation is explained by the still wider bandgap of Si3N4 and its largely reduced density of localized bandtail states that arise from the high-temperature deposition and the concomitantly increased structural order. Other attractive features of this double-layer technique are that the individual layer thicknesses can be adjusted to yield a low overall tensile stress and that both layers can be removed after the PS sacrificial layer process, selectively, with regard

Porous Silicon Based MEMS Chapter | 23

to gate and field oxide layers that might be used for the realization of active electronic devices inside the freestanding Si structures. Using this technique, large platforms with dimensions of approximately 500 μm 3 300 μm were successfully thermally insulated, as will be described further in Figure 23.30. The electronically active components in the Si platforms withstand the PS sacrificial layer process. Using the above kinds of passivation layers, special care needs to be taken when n1 surface areas need to be protected. As during activation and drive-in anneals, n1 layers have a tendency to spread vertically and laterally, a sufficient overlap of the passivation layers beyond the design size of the n1 regions needs to be taken into account. Very long PS formation processes could be sustained, allowing for 10-μm overlaps (Figure 23.23). An overview on passivation layer techniques and PS depths obtained with these techniques is presented in Table 23.1.

23.5.3 PS Stability Once the PS had been formed in predefined areas of the wafer, the question arises of how to remove the PS with Overlap

Passivation n+ Implantation Outdiffused n

PS

p-type substrate FIGURE 23.23 Protection of n1 surface areas by overlapping passivation layers.

515

regard to the undisturbed bulk Si. The ease with which this can be done depends on the morphology of the PS: Highly porous NPS layers with extremely thin lamellae are easier to remove than lower-porosity materials with concomitantly thicker lamellae. Forming high-porosity NPS is clearly the method of choice in all those cases in which the PS removal is the final processing step. In many sensor and actuator processes, however, this is not the case. In these latter cases additional lithography and thin-film deposition steps need to be carried out on a sufficiently flat PS surface. NPS material cannot be used under such circumstances, as these high-porosity layers tend to shrink and eventually to collapse as the NPS is removed from the etchant solution and dried to enable follow-on processing steps. Reasonably flat surfaces can be obtained using lower-porosity material, albeit at the expense that such layers are harder to remove with good selectivity to the bulk Si. Turning to the problem of PS removal first, we note that—depending on the porosity—the thickness of the lamellae in p-type PS can range from a few up to about 100 nm, depending on the initial doping and the PS processing conditions. Further considering that the entire PS network is accessible to a liquid etchant, removing a thickness of silicon corresponding to the average lamellae thickness means that an entire sacrificial layer with vertical and lateral dimensions of 100 μm or more will be removed. As there is no chemical selectivity against the remaining bulk Si structures, bulk Si layers with a thickness comparable to the average lamellae thickness will be removed from the bottom of the n-type drive-in regions. Such small amounts of Si can easily be removed by room-temperature KOH etching. As NPS exposes a huge surface to the KOH, care needs to be taken that the process of PS dissolution is carried out in a reasonably slow and controlled way. In order to avoid excessive formation

TABLE 23.1 Comparison of Passivation Layer Techniques Mask Material

Etch Rate

PECVD SiN

Undercut

Max. PS Depth

Remarks

Reference

.250 nm/min

Mask may delaminate in high-stress and over n1 regions

[49]

PECVD SiC

None

Mask may delaminate in high-stress and over n1 regions

[30,47]

n-Implantation

None

1:1

Wafer thickness

Rough surfaces due to junction leakage at high cell voltages

[48]

SiO2/poly-Si

None

1:1

Wafer thickness

Underetching of SiO2; approximately 50% of mask undercut

[49]

LPCVD SiN

B25 nm/min

1:1

10
30 μm

Etch rate thickness dependent

[49]

LPCVD SiN/poly-Si

None

1:1

Wafer thickness

Negligible lateral etching of LPCVD SiN

[48]

516 PART | IV Micromachining Technologies in MEMS

PS removed (μm)

40 30 20 10

O

a

Af te r

2

Pl a

ba rd ha

Af te r

sm

ke

h 48

h Af te r

24 Af te r

e ca

sc

ad

et ch KO H

PS

di

de

re

pt h

ct

0

FIGURE 23.24 Ease of PS sacrificial layer removal following unintentional surface oxidation treatments.

TABLE 23.2 PS Dissolution Techniques Etchant

Etch Rate (μm/min)

Remarks

Reference

Diluted TMAH

1
5 μm/min

Fails after partial oxidation of PS

[49]

Diluted KOH

5
10 μm/min

Can be used on partially oxidized PS

[48,49]

10% HF

22
25 μm/min

To be used after dry oxidation of PS at 950

[30,47]

of H2 bubbles, the porosified Si wafers need to be processed through a cascade of increasingly more concentrated KOH (1%, 5%, 10%) solutions [30,47,48]. Another consequence of the high specific surface area of NPS is that, once formed, NPS layers may easily oxidize as the wafers are stored in the lab as they wait for further processing steps (Figure 23.24). A short HF dip, therefore, might be necessary before processing through a KOH cascade. Concerning NPS dissolution, some authors also advocate for an intentional dry oxidation of the NPS at 950 C and subsequent removal of the porous SiO2 in dilute HF [30,47] (Table 23.2). An advantage of this latter method is that excessive H2 bubbling is avoided. However, care needs to be taken with regard to mechanical stresses that may be generated upon oxidation of the NPS. Moreover, the use of dilute HF for the NPS removal requires that thin-film structures on top of the wafer surface are either able to sustain such a treatment or that these are properly passivated. Another approach to removing PS sacrificial layers is high-temperature annealing in a reducing H2 atmosphere. In this way potential problems with unintentional PS oxidation are avoided and the nanometer-sized silicon particles in the NPS are caused to sinter and to evaporate onto

the more massive bulk silicon structures in the immediate neighborhood. In this latter case cavities with smooth surfaces and well-defined geometries can be obtained (cf. Section 23.6.3). The second issue relates to the problem of PS stability. PS stability is required whenever the sensor or actuator process requires lithography and thin-film steps to follow the PS formation process. PS stability is related to the level of porosity and to the mechanical stability of the pore-separating Si walls. Ensuring PS stability, maintaining at the same time a sufficiently high porosity to allow easy PS removal, requires insight into those processes that determine the porosity of the PS layers. As detailed in Section 23.4, the elementary process of silicon removal is bond breaking, rebonding of the released Si atoms to the molecular and atomic constituents of the HF electrolyte, and finally forming dissolvable negative Si molecular ions. This elementary process of bond breaking and ion formation is operative in all kinds of silicon (p, p1, n, n1) and also under all conditions of current flow, illumination, and electrolyte composition. This universality of the key elementary process is reflected in Figure 23.25(a) which plots the mass removed from 1 cm2 of silicon wafer as a function of the charge that had been circulated through this same wafer area. The results of Figure 23.25(a) can be summarized as follows: d ðΔmÞ 5 αPS dQPS

(23.4)

In this equation, Δm (g/cm2) is the mass removed from 1 cm2 of wafer surface and QPS (As/cm2) is the charge circulated through this same surface element. αPS (g/As) is a universal constant that characterizes the elementary etch process. From Figure 23.25(a) it follows that, in agreement with the explanations in Section 23.4, roughly two electronic charges need to be circulated through the wafer to remove a single Si atom from the surface: αPS B0:5 Si atoms=elementary charge

(23.5)

With QPS 5 JPS 3 t, it further follows that globally the mass removal rate is proportional to the current density JPS that had been applied in the PS formation process: d ðΔmÞ 5 αPS 3 JPS dt

(23.6)

This once again applies to all kinds of silicon (p, p1, n, n1) and all conditions of PS formation. This kind of universality is lost when one considers the progression of the etch front into silicon wafers with time, that is, the etch rate. Figure 23.25(b) shows that in spite of the universal behavior with regard to mass removal, etch fronts move at different speeds as wafers with different background doping are porosified. Figure 23.25(b)

Porous Silicon Based MEMS Chapter | 23

0.016

(b) 180

0.014

160

0.012

140 Etch depth (μm)

Mass removed (g/cm2)

(a)

0.01 0.008 0.006 0.004

517

p-Si; 30 – 50 Ωcm

120 100 80 p-Si; 3–10 Ωcm

60 40

0.002

20

0

0 0

20

40

60

80

100

120

140

p-Si; 14 – 26 Ωcm 0

0.0025 0.005 0.0075

Charge accumulated (As/cm2)

0.01

0.0125 0.015

Mass removed (g/cm2)

FIGURE 23.25 (a) Mass removed per square centimeter of wafer surface as a function of charge circulated through this same wafer area; (b) penetration of the PS etch front into the same wafers as in (a) as a function of the mass removed [50].

Here L is the depth of the PS/bulk Si interface below the surface, ρSi and ρPS the bulk Si and the PS mass densities, and π the relative pore volume of the PS: ρ 2 ρPS π 5 Si (23.8) ρSi The decisive factor in Eq. (23.7) is the porosity or pore fraction π, which characterizes the PS morphology. There have been many investigations into the phenomenon of pore formation. These reveal that π is largely a function of the following materials and processing parameters:   K Si π 5 π doping; JPS ; illumination; (23.9) K el Here, KSi and Kel stand for the specific resistivities of the Si wafer and the electrolyte, respectively. Concentrating on the processing of p-type Si wafers under dark conditions, the results of Figure 23.26 show that π varies with the current density JPS and the background acceptor doping NA. These latter data, in particular, reveal that mechanically stable PS material is largely produced using moderate current densities and relatively heavily doped p-type material. Following this strategy, most authors studying NPS sacrificial layer technologies advocate using p-type material with specific resistivities in the range from 0.1 to 20 Ωcm. Under these latter conditions reasonably flat and

100 Mechanically unstable 80 Porosity (%)

moreover shows that the silicon removal rate may vary as the etch front penetrates deeper into the wafers. These differences in etch front propagation can be related to changes in the PS morphology. Writing Δm 5 πρSiL, an equation for the propagation of the etch front is obtained:     d 1 αPS ðLÞ 5 (23.7) 3 3 JPS dt π ρSi

60 5 Ωcm

40

0.1 Ωcm 20 0.01 Ωcm 0 0

50

100 Current density

150

200

250

(mA/cm2)

FIGURE 23.26 Porosity π of PS as a function of the current density JPS and the p-type background doping [32].

stable PS surfaces can be obtained that allow photolithographic processing of thin-film structures on top of the PS sacrificial layers. Optimally flat surfaces, which additionally allow high-quality epitaxial films to be deposited, require p1 surfaces which produce dense low-porosity materials at the wafer surface. An interesting possibility is forming a heavily doped p-type surface on a moderately doped p-type substrate. In such a case a stable surface PS layer can be formed on an NPS layer with a much higher porosity in the subsurface regions. The possibilities arising out of this latter technique are further demonstrated in Section 23.6.3.

23.6 APPLICATION EXAMPLES Following the description of the individual technological building blocks, we present in this final section a number of device demonstrators using PS as a sacrificial material.

518 PART | IV Micromachining Technologies in MEMS

(a)

(b)

n+ -implantation

FIGURE 23.27 Airbag bridge igniter: (a) schematic device layout; (b) n-type silicon bridge thermally insulated from the p-type substrate by PS formation.

n-well p-substrate p+ - implantation

23.6.1 Airbag Igniters An actuator application that promises a large market potential are airbag igniters. In a car accident, airbag igniters trigger an explosive charge that fills an airbag within milliseconds to reduce the effects of the impact on the passengers inside the car. Depending on the direction of the impact, several airbags need to be fired in a precisely defined time sequence to achieve optimum protection. Building such complex safety systems requires electronic airbag igniters to exhibit highly reproducible properties to allow successful integration into safety bus systems. Semiconductor technologies are best suited toward solving this problem: firstly because the silicon technology offers the required precision, and secondly because batch processing promises low cost. On a functional level, airbag igniters are one-shot thermal devices that become irreversibly destroyed when used. During use such igniter devices have to generate within a very short time temperatures much larger than the Si melting temperature, and they also need to generate an intense mechanical shock wave during the ignition event. Such requirements can be satisfied using silicon microstructures that exhibit the phenomenon of “explosive evaporation.” Semiconductor devices that exhibit this phenomenon can be made using PS sacrificial layer technologies. Figure 23.27(a) shows that such a device consists of a heavily doped n-type silicon bridge formed at the surface of a moderately doped p-type silicon wafer. Such bridges can be formed by ion implantation and a subsequent drive-in diffusion. In a second step the doped silicon bridge is thermally insulated by forming PS in all those surface areas that were not converted to ntype conductivity. Figure 23.27(b) shows that in this way the doped silicon bridge becomes successively underetched and thermally insulated by PS as the etching proceeds from the unmasked surface areas. The thermal insulation provided by the PS layer causes Joule heat to pile up inside the silicon bridge when current is passed through it. Figure 23.28 shows that the PS layer provides enough thermal insulation to allow heating the silicon bridge well beyond its melting point (TmB1412 C). Melting and recondensation of evaporated silicon is evidenced by the small silicon spheres deposited on the damaged substrate (Figure 23.28(a)).

The phenomenon of explosive evaporation is further demonstrated by the data of Figure 23.28(b)
(d). Figure 23.28(b) and (c) shows the current and light transients that occur during bridge heating. Figure 23.28(c), in particular, shows in greater detail that a sharp current increase is observed after a short constant-current period (B200 μs). This time delay corresponds to the time required for heating the bridge to its intrinsic temperature. After this temperature has been reached, the exponentially increasing conductivity of the silicon bridges causes large amounts of current (..1 A) to be passed through the tiny bridge and huge amounts of heat to be generated there. As due to the thermal insulation this heat cannot be conducted away, a rapid thermal runaway occurs, leading to the phenomenon of explosive evaporation. This latter interpretation is corroborated by Figure 23.28(d) which displays the resistance variation as derived from the current and voltage transients that can be observed during the ignition process. From the electrical and geometrical data of the device it can further be figured out that peak power densities in the order of PmaxB108 W/cm3 are generated. In this way peak temperatures up to 3000 C may be attained and a mechanical shock wave is initiated as the evaporated silicon suddenly requires roughly 1000 times more space than the initial silicon bridge. Such conditions are favorable for triggering explosive charges as in airbag safety devices.

23.6.2 Field Effect Gas Sensors Building on the experience gained in the successful realization of airbag igniters, we have realized a second set of thermal devices, namely, micro gas sensors. Both metal oxide and catalytic gate field effect devices have been realized. In this chapter we focus on this latter kind of device, as this can demonstrate the successful protection of delicate MOS devices that had been preprocessed into the ultimately freestanding silicon bridges. The entire process chain leading to such devices is shown in Figure 23.29, and final results are displayed in Figure 23.30. Except for the formation of field and gate oxides, the process chain of Figure 23.29 is largely the same as in the case of the airbag igniters. In summary,

Porous Silicon Based MEMS Chapter | 23

(b) Current (A); Light (a.u.)

(a)

519

20 Light 15 10 5 Current 0 0

1

2

3

4

Time (ms) (d) 100

8

Resistance (Ohm)

Current (A); Light (a.u.)

(c) 10

Current 6 4 Light 2 0 –0.1

10

1

0.1 0

0.1

0.2

0.3

Time (ms)

0

0.2

0.4

0.6

Time (ms)

FIGURE 23.28 (a) Airbag igniter after explosive evaporation; (b) current and light transients through the Si bridge during the process of explosive evaporation; (c) current and light transients in the pre-explosion phase; (d) variation of the bridge resistance as evaluated from the measured current and voltage transients.

(1) Implantation

(4) Passivation Passivation

n well

operated at high temperature, the air cushion formed after PS removal ensures thermal insulation and, hence, low power consumption [51].

p-substrate (2) Oxidation

(5) PS Formation

Field & gate Nitride oxide p-substrate

Porous silicon

(3) Implantation Oxide p-substr.

Passivation

(6) Metallization KOH

n+-impl. n well

Pt heater gate electrode Air cushion

p+-impl. FIGURE 23.29 Process sequence leading to thermally insulated catalytic gate field effect gas sensors.

the PS sacrificial layer process with the improved passivation layer technology allows for the fabrication of thermally insulated hotplates which serve as a platform for the described gas sensors. While the sensors can be

23.6.3 Pressure Sensors MEMS pressure sensors are widely employed in the automotive industry and other industrial sectors as well as in various kinds of medical instruments. Typical automotive applications include manifold absolute pressure (MAP) and barometric air pressure measurement in engine control units. Other applications are tire pressure, fuel tank, or airbag monitoring systems [52,53]. Micromechanical pressure sensors are also increasingly used in consumer electronics, as, for instance, in altimeters inside mobile phones or in climate-control and navigation systems. All applications demand small-size, low-cost, and highaccuracy pressure sensors. In MEMS pressure sensors, the key element is a diaphragm containing piezoresistors which can be formed by ion implantation or in-diffusion. Applied pressure deflects the diaphragm and thereby changes the resistance of the piezoresistors. By arranging the piezoresistors in a Wheatstone bridge, an output signal voltage can be generated [53].

520 PART | IV Micromachining Technologies in MEMS

FIGURE 23.30 Top row: Results of sacrificial layer etching (a) crosssection through the air cushion forming after the PS release; (b) catalytic gate MOS capacitor after removal of the Si3N4/poly-Si passivation layer. The ntype Si hotplate serving as a platform for the MOS capacitor has dimensions of approximately 500 μm 3 300 μm and a thickness of a few micrometers. Bottom row: (c) high-frequency CV characteristics of the MOS capacitor after PS formation, PS release, and passivation layer removal; (d) gas response toward a train of H2 pulses (bridge temperature 150 C).

(b) 190 μm

(a)

(c) C (pF)

(d) 47

40

C (pF)

46 35 30

44

25 –15

–10

–5

45

43 0

5

10

0

U (V)

Since single-crystal silicon exhibits much higher piezoresistive coefficients than poly-crystalline silicon, most piezoresistive pressure sensors employ single-crystal silicon membranes with integrated piezoresistors. Such sensors are conventionally fabricated by anisotropic etching with KOH [54], requiring expensive backside and wafer bonding processes. Advanced methods rest upon isotropic undercutting of single-crystal silicon layers epitaxially grown on expensive SOI substrates [55]. In the following, the surface micromachining Advanced Porous Silicon Membrane (APSM) technology is presented, which was first introduced at Bosch in 2002 [56]. This method enables the fabrication of self-sealing single-crystal silicon membranes covering a vacuum cavity by using PS as a smart sacrificial material. The APSM process offers a high degree of freedom in designing different membrane geometries, a fully CMOS-compatible process flow, and a high level of integration. The membrane formation is embedded in a standard mixed-signal process to fabricate an integrated piezoresistive pressure sensor. Most of the necessary membrane fabrication steps are simultaneously used for the ASIC integration, with the anodic etching of the PS representing the only additional process step. Furthermore, this technology requires only frontside processing. Thus, very cost-efficient integrated pressure sensors can be obtained. The main process steps of the APSM technology are (a) anodization, during which the silicon substrate is locally porosified by electrochemical etching in concentrated HF, (b) thermal rearrangement of the PS, and (c) epitaxial growth on top of the rearranged PS double layers.

23.6.3.1 PS as Seed Layer for Epitaxial Growth During the process of anodization, silicon atoms are dissolved from the crystal lattice. Since the remaining atoms

50 t (min)

100

stay on their atomic positions, the porous matrix retains its lattice arrangement. This allows for epitaxial growth of single crystal silicon layers on top of a PS seed layer. At elevated temperatures above 400 C in nonoxidizing atmospheres, PS starts to rearrange and coarsen its morphology [57]. The driving force is the minimization of the surface energy. In isolated pores the surface energy reduction is achieved by arranging surface atoms along crystal planes with the lowest specific surface energy {(100) and (111)}. This leads to faceted pore shapes. Further, pores can reduce their total surface area, which results in pore shrinkage. Considering PS double layers, it has been shown that the rearrangement leads to solidification of the low porosity layer and dissolution of the high porosity one [58]. At the interface of PS and vacuum (equivalent to 100% porosity) the same effect leads to the sealing of surface pores. However, the change of the PS morphology during thermal treatment is highly constricted by contamination of the internal surface with adatoms. A thin layer of native oxide, for example, stabilizes the morphology up to temperatures of 900 C in a nonreducing atmosphere [59]. Hence, to use thermal rearrangement of PS as a reproducible process step, any kind of surface contamination has to be avoided.

23.6.3.2 Fabrication A schematic overview of the membrane fabrication is shown in Figure 23.31. Starting material is a moderately p-doped silicon substrate with (100)-orientation. First, a deep n1 and a shallow p1-implantation are performed in the substrate. Since the n1-regions are not porosified during the anodization [60], they serve as lateral confinements for the membrane regions inside the bulk substrate. The n1-wells are designed as quadratic frames enclosing shallow p1-areas. The p1-areas

Porous Silicon Based MEMS Chapter | 23

(a)

n+-Si

p+-Si

Si3N4

p-Si

(c)

p-Si

n+-Si

(b)

p-Si n+-Si

sealed mesoporous Si

521

mesoporous Si

nanoporous Si

(d) Single-crystal Si epitaxy

rearranged nanoporous Si

p-Si

vacuum cavity

FIGURE 23.31 Process flow of the APSM process: Si-substrate (a) before anodization, (b) after anodization, (c) after hydrogen prebake, (d) after single-crystal epitaxy.

Mesoporous seed layer

Nanoporous cavity layer

FIGURE 23.32 Cross-sectional SEM micrograph after anodization of a mesoporous seed layer and a buried nanoporous cavity layer.

subsequently serve as single crystal seed layers for the epitaxial growth of silicon. Additionally, a silicon nitride layer is deposited onto the wafer to avoid porous etching of the substrate surface except for the membrane regions themselves. The subsequent anodic etching in concentrated HF is performed in a double-cell arrangement as shown in Figure 23.31. The anodization is carried out in a two-step process. First, the p1-Si layer is etched, using a low current density resulting in a mesoporous silicon layer with a porosity of about 45%. Second, the subjacent p-Si is anodized with an increased current density leading to an NPS layer with a porosity of about 70% buried underneath the mesoporous layer (Figure 23.31(a)). Afterwards, the silicon nitride layer is removed in the same HF cell (Figure 23.31(b)). In a CVD reactor the substrate is then exposed to a H2 atmosphere at ambient pressure. At temperatures between 900 C and 1100 C the hydrogen desorbs any residual native oxide from the PS surface. As soon as the oxide has been removed, both PS layers start to rearrange: The surface pores in the mesoporous layer are thereby sealed, while the buried NPS starts to merge into one single cavity (Figure 23.31(c)).

In the same CVD reactor, an epitaxial Si-layer is grown, using the sealed mesoporous silicon as a seed layer. Upon completion of the epitaxial layer, all PS has completely rearranged leaving one single cavity (Figure 23.31(d)). The thickness of the epitaxial layer (B10 μm) defines the membrane thickness. The hydrogen enclosed inside the cavity diffuses through the silicon during subsequent high-temperature processes, leaving a vacuum. Figure 23.32 shows the cavity region after anodization. In the whole membrane region a double porous stack with an upper mesoporous layer and a buried nanoporous layer was generated. Figure 23.33 displays the cavity region after hydrogen prebake. Driven by the minimization of the free surface energy, both PS layers start to rearrange. The buried NPS layer shows a coarsened morphology (Figure 23.33(a)). The surface of the enlarged pores is strongly faceted, which is due to the low surface energy of specific crystal faces. The upper mesoporous layer is sealed, providing the seed layer for the epitaxial growth (Figure 23.33(b)). Since the rearrangement of PS is a thermally activated process, it continues with each high-temperature process, even in the sealed cavity, until finally a single cavity is formed. Figure 23.34(a) and (b) shows the membrane and cavity regions after the deposition of an approximately 10 μm thick silicon membrane. The PS has now completely rearranged, creating a single vacuum cavity. The Si epitaxial layer is grown onto the sealed mesoporous silicon. Since the mesoporous silicon layer, and thereby the Si growth, is perfectly single crystalline, a high-quality single-crystal silicon layer is formed. The mesoporous layer is part of the membrane and has been completely smoothed by the thermal rearrangement (Figure 23.34(a)). Due to the vacuum inside the hermetically sealed cavity, the membrane is slightly bent under atmospheric pressure (Figure 23.34(b)).

522 PART | IV Micromachining Technologies in MEMS

(a)

(b) 1 μm Sealed mesoporous Si

Rearranged nanoporous Si

1 μm

(a)

FIGURE 23.33 Cross-sectional SEM micrograph after hydrogen prebake, (a) rearranged NPS with strongly facetted pore surface and (b) sealed mesoporous seed layer.

FIGURE 23.34 (a) Cross-sectional SEM micrograph of single-crystal Si-membrane after epitaxial growth; (b) optical micrograph of Si-membrane. The enclosed vacuum leads to a deflection toward the substrate.

(b)

Si-epitaxy

Vacuum cavity

p-Si

5 μm

200 μm

FIGURE 23.35 Picture of a fully processed MAP sensor: (a) sensor element after dicing, (b) sensor element bonded to premold housing, and (c) complete sensor module.

23.6.3.3 Piezoresistive Pressure Sensor The APSM technology was successfully embedded into a standard mixed-signal process to fabricate an integrated piezoresistive pressure sensor for automotive applications [56]. By utilizing the high synergy between MEMS and ASIC fabrication, a cost-effective fabrication can be achieved. Figure 23.35(a) shows a fully processed MAP

sensor chip. Four piezoresistors are implanted at the membrane edges and connected into a Wheatstone bridge. The monolithically integrated ASIC provides a constant supply voltage and is also used for signal processing as well as for temperature and offset compensation. Figure 23.35(b) shows the sensor element bonded to its premold housing, and Figure 23.35(c) presents a view onto the complete sensor module.

Porous Silicon Based MEMS Chapter | 23

23.7 SUMMARY AND CONCLUSIONS PS micromachining (PSM) technologies form a group of technologies that build on the use of PS as sacrificial layers. Release of the PS sacrificial layers can result either in freestanding thin film structures or in low-stress bulk silicon structures containing electronic elements such as piezoresistors, pn-junctions or MOS capacitors. PSSM technologies allow 3D silicon microstructures to be formed at the surface of silicon wafers without affecting the back surface of the wafers. The vertical dimensions of the released microstructures can range from a fraction of a micrometer up to several micrometers. The dimensions of air or vacuum gaps underneath released microstructures can range from a few micrometers up to the full wafer thickness. PSSM technologies therefore combine the advantages of relatively massive bulk silicon microstructures with the advantages of topsurface silicon processing. PSSM technologies employ electrochemical etching in HF/H2O/ethanol electrolytes for the PS formation. As the PS formation is sensitive to the background doping and illumination of the silicon wafers, microstructures can be vertically delineated by forming suitably shaped surface and subsurface doping profiles in silicon wafers. Such profiles can be formed by ion implantation and drive-in diffusions. Lateral confinement of the microstructures can be achieved by employing CMOS-compatible passivation layers such as low-pressure chemical vapor deposition (LPCVD) nitride and poly-silicon. Such layers can also be used to protect electronic elements embedded in bulk silicon microstructures from the aggressive HF/H2O/ethanol electrolytes. Removal of the PS sacrificial layers can be performed at the end of sensor and actuator process sequences, either using diluted silicon etches or by employing sintering and evaporation techniques. Full process compatibility with CMOS and mixedsignal electronic technologies has been demonstrated, and the first industrial products based on PSSM techniques have been launched in the automotive markets.

REFERENCES [1] A. Uhlir, Electrolytic shaping of germanium and silicon, Bell Syst. Tech. J 35 (1956) 333
347. [2] K. Imai, A new dielectric isolation method using porous silicon, Solid-State Electron 24 (1981) 159. [3] D. Flandre, A.N. Nazarov, P.L.F. Hemment (Eds.), Porous silicon based SOI: history and prospects, in: Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment, NATO Science Series, vol. 185, Springer Netherlands, ISSN 1568
2609, 2004, pp. 53
64. [4] L.T. Canham, Appl. Phys. Lett. 57 (1990) 1046
1048. [5] V. Lehmann, U. Go¨sele, Porous silicon formation: a quantum wire effect, Appl. Phys. Lett. 58(8) (1991) 856
858.

523

[6] L. Canham (Ed.), Properties of porous silicon, in: EMIS Datareviews Series, No. 18, INSPEC The Institution of Electrical Engineers, ISBN 0852969325. [7] Z.C. Feng, R. Tsu (Ed.), Porous silicon, in: World Scientific, 1994, ISBN 9810216343. [8] R. He´rino, Pore size distribution in porous silicon, in: L. Canham (Ed.), Properties of Porous Silicon, EMIS Datareviews Series, No. 18, INSPEC The Institution of Electrical Engineers, ISBN 0852969325, pp. 89
96. [9] J. Drott, K. Lindstro¨m, L. Rosengren, T. Laurell, Porous silicon as the carrier matrix in microstructured enzyme reactors yielding high enzyme activities, J. Micromech. Microeng. 7 (1997) 14
23. [10] M. Hayase, D. Saito, T. Hatsuzawa, Catalyst metal deposition into porous silicon layer, IEE J. Trans. Sens. Micromach. 125(10) (2005) 407
412. [11] C.-Y. Lee, S.-J. Lee, C.-L. Dai, C.-W. Chuang, Application of porous silicon on the gas diffusion layer of micro fuel cells, Key Eng. Mater. 364
366 (2008) 849
854. [12] P.T.J. Gennissen, P.J. French, D.P.A. De Munter, T.E. Bell, H. Kaneko, P.M. Sarro, Porous silicon micromachining techniques for accelerometer fabrication, in: Proceedings of ESSDERC ‘95, Den Haag, The Netherlands, 1995, pp. 593
596. [13] M. Archer, M. Christophersen, P.M. Fauchet, Electrical porous silicon chemical sensor for detection of organic solvents, Sens. Actuators, B 106(1) (2005) 347
357. [14] R. Angeluccia, A. Poggia, L. Doria, G.C. Cardinalia, A. Parisinia, A. Tagliania, et al., Permeated porous silicon for hydrocarbon sensor fabrication, Sens. Actuators, A 74(1
3) (1999) 95
99. [15] G.M. O’Halloran, P.M. Sarro, J. Groeneweg, P.J. Trimp, P.J. French, A bulk micromachined humidity sensor based on porous silicon, in: Proceedings of Transducers ‘97, 1997 International Conference on Solid
State Sensors and Actuators, Chicago, IL, 1997, pp. 563
566. [16] D. Kovalev, V. Yu Timoshenko, N. Ku¨nzner, E. Gross, F. Koch, Strong explosive interaction of hydrogenated porous silicon with oxygen at cryogenic temperatures, Phys. Rev. Lett. 87(6) (2001) Article ID 068301, 4 pages. [17] M. Tho¨nissen, M. Kru¨ger, G. Lerondel, R. Romestain, Optical applications of porous silicon, in: L. Canham (Ed.), Properties of Porous Silicon, EMIS Datareviews Series, No. 18, INSPEC The Institution of Electrical Engineers, ISBN 0852969325, pp. 349
355. [18] G. Lammel, P. Renaud, 3D flip-up structure of porous silicon with actuator and optical filter for microspectrometer applications, in: Proceedings of MEMS 2000, The Thirteenth Annual International Conference on Micro Electro Mechanical Systems, 2000, pp. 132
137. [19] R.R. Bilyalov, L. Stalmans, L. Schirone, C. Levy-Clement, Use of porous silicon antireflection coating in multicrystalline silicon solar cell processing, IEEE Trans. Elect. Dev. 46(10) (1999) 2035
2040. [20] S. Ottow, V. Lehmann, H. Fo¨ll, Processing of three-dimensional microstructures using macroporous η-type silicon, J. Electrochem. Soc. 143(1) (1996) 385
390. [21] J. Schilling, A. Birner, F. Mu¨ller, R.B. Wehrspohn, R. Hillebrand, U. Go¨sele, et al., Optical characterisation of 2D macroporous silicon photonic crystals with bandgaps around 3.5 and 1.3 μm, Opt. Mater. 17 (2001) 7
10. [22] R.B. Wehrspohn, S.L. Schweizer, V. Sandoghdar, Linear and nonlinear optical experiments based on macroporous silicon photonic crystals, Phys. Stat. Sol. A 204 (2007) 3708
3726.

524 PART | IV Micromachining Technologies in MEMS

[23] G. Kaltsas, D.N. Pagonis, A.G. Nassiopoulou, Planar CMOS compatible process for the fabrication of buried microchannels in silicon, using porous-silicon technology, J. Microelectromech. Syst. 12(6) (2003) 863
872. [24] C. Lyons, A. Friedberger, W. Welser, G. Mu¨ller, G. Kro¨tz, R. Kassing, A high-speed mass flow sensor with heated silicon carbide bridges, in: IEEE Proceedings, The 11th Annual International Workshop on Micro Electro Mechanical Systems, Heidelberg, Germany, 1998, pp. 356
360. [25] F. Mu¨ller, A. Birner, J. Schilling, U. Go¨sele, Ch. Kettner, P. Ha¨nggi, Membranes for micropumps from macroporous silicon, Phys. Status Solidi A 182 (2000) 585
590. [26] T. Bischoff, G. Mu¨ller, W. Welser, F. Koch, Frontside micromachining using porous-silicon sacrificial-layer technologies, Sens. Actuators, A 60(1
3) (1997) 228
234. [27] F. Gaspard, A. Bsiesy, M. Ligeon, F. Muller, R. Herino, Charge exchange mechanism responsible for p-type silicon dissolution during porous silicon formation, J. Electrochem. Soc. 136(10) (1989) 3043
3046. [28] H. Fo¨ll, Properties of silicon-electrolyte junctions and their applications to silicon characterization, Appl. Phys. A 53 (1991) 8
19. [29] W. Lang, P. Steiner, H. Sandmaier, Porous silicon: a novel material for microsystems, Sens. Actuators, A 51 (1995) 31
36. [30] W. Lang, Silicon microstructuring technology, Materials Science and Engineering, R 17, No. 1, Elsevier Science, (1996) 1
55. [31] U. Go¨sele, V. Lehmann, Porous silicon quantum sponge structures: formation mechanism, preparation methods and some properties, in: Z.C. Feng, R. Tsu (Eds.), Porous Silicon, World Scientific, 1994, pp. 17
39. ISBN 9810216343. [32] S. Frohnhoff, M. Marso, M.G. Berger, M. Tho¨nissen, H. Lu¨th, H. Mu¨nder, An extended quantum model for porous silicon formation, J. Electrochem. Soc. 142(2) (1995) 615
620. [33] V. Lehmann, H. Fo¨ll, Formation mechanism and properties of electrochemically etched trenches in η-type silicon, J. Electrochem. Soc. 137(2) (1990) 653
659. [34] V. Lehmann, The physics of macropore formation in low doped n-type silicon, J. Electrochem. Soc. 140(10) (1993) 2836
2843. [35] C. Le´vy-Cle´ment, S. Lust, M. Mamor, J. Rappich, Th. Dittrich, Investigation of p-type macroporous silicon formation, Phys. Status Solidi A 202 (2004) 1390
1395. [36] W. Lang, P. Steiner, A. Richter, K. Marusczyk, G. Weimann, H. Sandmaier, Application of porous silicon as a sacrificial layer, Sens. Actuators, A 43 (1994) 239
242. [37] A. Zeitschel, A. Friedberger, W. Welser, G. Mu¨ller, Breaking the isotropy of porous silicon formation by means of current focusing, Sens. Actuators, A 74 (1999) 113
117. [38] P. Steiner, W. Lang, Micromachining applications of porous silicon, Thin Solid Films 255 (1995) 52
58. [39] S.P. Duttagupta, C. Peng, P.M. Fauchet, S.K. Kurinec, T.N. Blanton, Enhancement and suppression of the formation of porous silicon, J. Vac. Sci. Technol. B 13(3) (1995) 1230
1235. [40] S.S. Tsao, T.R. Guilinger, M.J. Kelly, V.S. Kaushik, A.K. Datye, Porous silicon formation in N2/N1/N2doped structures, J. Electrochem. Soc. 138(6) (1991) 1739
1743. [41] G.-A. Racine, G. Genolet, P.-A. Clerc, M. Despont, P. Vettiger, N.F. de Rooij, Porous silicon sacrificial layer technique for the fabrication of free standing membrane resonators and cantilever arrays, in: Proceedings of Eurosensors XI, Warsaw, vol. 1, 1997, pp. 285
288.

[42] R. Mlcak, H.L. Tuller, P. Greiff, J. Sohn, L. Niles, Photoassisted electrochemical micromachining of silicon in HF electrolytes, Sens. Actuators, A 40 (1994) 49
55. [43] T.E. Bell, P.T.J. Gennissen, D. DeMunter, M. Kuhl, Porous silicon as a sacrificial layer, J. Micromech. Microeng. 6 (1996) 361
369. [44] T. Bischoff, G. Mu¨ller, F. Koch, Bulk and surface micromachining using porous silicon sacrificial layer technologies, in: Proceedings of Eurosensors X, Leuven, Belgium, 1996, P1.1-73, pp. 211
214. [45] G.F. Eriksen, K. Dyrbye, Protective coatings in harsh environments, J. Micromech. Microeng. 6 (1996) 55
57. [46] J.-H. Park, J.-B. Choi, H.-Y. Kim, K.-Y. Lee, J.-Y. Lee, A study on the structural characterization of a-SiC: H films by the gas evolution method, Thin Solid Films 266 (1995) 129
132. [47] W. Lang, S. Billat, F. Hedrich, SEPOS II—Einsatz von poro¨sem Silizium in der Sensorik Final Report Hahn-SchickardGesellschaft fu¨r angewandte Forschung e.V.—Institut fu¨r Mikround Informationstechnik—IMIT (HSG-IMIT), D-78052 VillingenSchwenningen, June 2000. [48] A. Friedberger, P. Kreisl, G. Mu¨ller, R. Kassing, A versatile and modularizable micromachining process for the fabrication of thermal microsensors and microactuators, J. Micromech. Microeng. 11 (2001). [49] Z.M. Rittersma, Microsensor applications of porous silicon, Ph.D. thesis, Department of Physics and Electrical Engineering, University of Bremen, 1999. [50] A. Zeitschel, Diploma thesis, Physics Department TUM, 1997. [51] P. Kreisl, A. Helwig, A. Friedberger, G. Mu¨ller, E. Obermeier, S. Sotier, Detection of hydrocarbon species using silicon MOS capacitors operated in a non-stationary temperature pulse mode, Sens. Actuators, B 106 (2005) 489
497. [52] M.J. Madou, Fundamentals of Microfabrication: The Science of Miniaturization, second ed., CRC Press, Boca Raton, FL, 2002. [53] M.-H. Bao, Micro Mechanical Transducers, second ed., Elsevier, 2004. [54] H.-J. Kress, F. Bantien, J. Marek, M. Willmann, Silicon pressure sensor with integrated CMOS signal-conditioning circuit and compensation of temperature coefficient, Sens. Actuators, A 25 (1991) 21. [55] Y. Suzuki, T. Kudo, K. Ikeda, Accurate, cost effective absolute pressure sensor, in: Digest of Technical Papers Transducers ‘97, 1997, p. 258. [56] S. Armbruster, F. Scha¨fer, G. Lammel, H. Artmann, C. Schelling, H. Benzel, et al., Monocrystalline silicon membranes grown on sintered porous silicon for an integrated pressure sensor, in: Proceedings of SENSOR 2003, 2003, pp. 185
190. [57] R. Herino, A. Perio, K. Barla, G. Bomchil, Microstructure of porous silicon and its evolution with temperature, Mater. Lett. 2 (1984) 519. [58] N. Ott, M. Nerding, G. Mu¨ller, R. Brendel, H.P. Strunk, Structural changes in porous silicon during annealing, in: Proceedings of PSST, 2002, p. 36. [59] A. Halimaoui, Porous Silicon—Science and Technology, Lecture 3, Springer, 1994. [60] M.I.J. Beale, J.D. Benjamin, M.J. Uren, N.G. Jew, A.J. Cullis, An experimental and theoretical study of the formation and microstructure of porous silicon, J. Cryst. Growth 73 (1985) 622
636. [61] J. Spannhake, A. Helwig, A. Friedberger, G. Mu¨ller, W. Hellmich, Resistance heating, in: J. Webster (Ed.), Wiley Encyclopedia of Electrical and Electronics Engineering—3223, John Wiley & Sons, Inc., 2007.