Nuclear Instruments and Methods in Physics Research B 161±163 (2000) 381±386
www.elsevier.nl/locate/nimb
Post-irradiation eects in MOS structures Elena Iliescu a
a,*
, Cecilia Codreanu b, M. Badila b, V. Banu c, Aritina Badoiu
d
Electron Accelerators Laboratory, Nat. Inst. for Laser, Plasma & Radiation Physics, P.O. Box MG-36, 76900 Bucharest-Magurele, Romania b Nat. Inst. for Microtechnologies, P.O. Box 38-160, Bucharest, Romania c Baneasa S.A., Str. Erou Iancu Nicolae 32, Bucharest, Romania d Romes S.A., Str. Erou Iancu Nicolae 32B, Bucharest, Romania
Abstract The paper presents results of a study of post-electron irradiation eects in MOS structures (MOS capacitors, VDMOS transistors). The behavior of oxide trap charge and interface traps have been monitored with standard C±V method. By evaluating electrical parameters depending on volume and surface eects, we could compare the signi®cance of interface states versus volume eects in irradiated samples. Ó 2000 Elsevier Science B.V. All rights reserved. PACS: 85.30.T; 73.25; 72.20.J Keywords: Electron-irradiation; MOS structures; Interface traps; Oxide-trap charge; Electrical parameters
1. Introduction The post-irradiation eects in power MOS devices have received a considerable attention during the last several decades [1]. Despite many years of research, the mechanism of radiation induced interface states formation in MOS devices remains controversial. The ionizing radiation produces in SiO2 a transient, followed by a permanent or a semipermanent eect that can be in¯uenced by post-irradiation annealing treatments. This aspect was intensively investigated in the last years [2,3] and new models of oxide and interface traps in-
*
Corresponding author. E-mail address: eiliescu@i®n.nipne.ro (E. Iliescu).
duced by irradiation [4] and new characterization methods were proposed [5,6].
2. Experimental MOS capacitors test samples were fabricated on N type (phosphorus doped) silicon substrates of á1 1 1ñ orientation, and 5±10 X cm resistivity, that corresponds to a doping concentration of approximately 5 1014 cmÿ3 . Two types of thermally grown oxides were used to fabricate the test thickness, structures: one is a wet oxide of 3500 A The and the other is a dry oxide of 1000±1200 A. metal of the gate contact was aluminum. To avoid the errors arising from geometrical factors, in the analysis of the experimental data, we have used the
0168-583X/00/$ - see front matter Ó 2000 Elsevier Science B.V. All rights reserved. PII: S 0 1 6 8 - 5 8 3 X ( 9 9 ) 0 0 9 6 3 - 5
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normalized values of measured capacitance. Further, the notation ``C1'' will be used for capacitor test samples proceeding from the wafer having the and, respectively, the oxide thickness of 3500 A notation ``C2'', for capacitor test samples pro oxide ceeding from the wafer with a 1000±1200 A thickness. Many applications involving semiconductor devices operating in a radiation environment imply high temperature conditions too, and we considered being useful to study how the irradiation temperature in¯uences these eects. Irradiation was performed using the linear electron accelerator ALIN-7, at dierent doses and temperatures. ALIN-7 has the following parameters: energy 7 MeV, average beam current 8 lA, pulse width 2.5 ls, pulse repetition rate 150 Hz, electron radiation dose 4 103 Gy/min at 1 m. Samples were irradiated either at room temperature (300 K) or at high temperature (500 K), as follows: · three steps, each of 5 kGy (15 kGy total dose) at T 300 K, for samples C1; · three steps, each of 5 kGy (15 kGy total dose) at T 500 K, for samples C1; · two steps, each of 5 kGy (10 kGy total dose) at T 300 K, for samples C2; · two steps, each of 5 kGy (10 kGy total dose) at T 500 K, for samples C2. Measurements were made on a standard 1 MHz C±V-meter before and after irradiation. Post-irradiation C±V curves were obtained in two circumstances: immediately after irradiation, and after a post-irradiation annealing treatment consisting of an initial heating of the samples up to 500 K for 10 min, then slowly cooling them up to the room temperature. The behavior of the oxide and interface trapped charge in the Si/SiO2 system, before and after irradiation, was investigated by means of the standard high-frequency C±V method in a biastemperature aging experiment consisting of: · initial determination of the C±V curves, at T 300 K, before irradiation; · after irradiation determination of the C±V curves for samples heated at T 500 K and stressed with a positive high voltage applied to the gate electrode for 5 min (+16.5 V for samples C1 and +10 V for samples C2);
· a slow cooling of the structures up to 300 K; · after irradiation determination of the C±V curves for samples heated at 500 K and stressed with a negative high voltage stress applied to the gate electrode for 5 min ()16.5 V for samples C1 and )10 V for samples C2). The magnitude of the gate voltage stress was chosen so that the ®eld created in the oxide is smaller than the breakdown ®eld. We have also studied the post-irradiation eects on VDMOS transistors. The samples are fabricated on N type silicon substrate of á1 1 1ñ orientation. The epitaxial layer is a relatively thick Nÿ region that provides voltage breakdown capability but with inherent introduction of a high series resistance. The interface ®xed charges are responsible for a 510 V breakdown voltage. The devices were encapsulated in TO-3 cases. The electron irradiation was performed at high temperature (500 K) in order to increase the irradiation eciency and to minimize the post-irradiation annealing requirement. The studied samples were enough for a statistical evaluation. Devices were measured: before electron irradiation, after electron irradiation, and after an annealing at 450 K for 24 h in N2 ambient. 3. Results and discussions 3.1. In¯uence of irradiation dose, irradiation temperature, and post-irradiation annealing on MOS capacitors Samples C1 support the irradiation at 300 and 500 K up to 10 kGy without great C±V curves deformation. The result of the ®rst 5 kGy irradiation step is a rather stretch than a shift in C±V characteristics (DV ÿ0:5 V), i.e. a modi®cation of the interface level density and only a small quantity of irradiation oxide induced charge. After the second 5 kGy irradiation step, the curve shift becomes predominant (DV ÿ2:5 V) over the curve stretch, indicating the induction of a positive oxide charge density DNox 1:5 1011 cmÿ2 . After a new room temperature irradiation step of 5 kGy the C±V curve is drastically distorted.
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If the irradiation is made at 500 K, there is a slight increase in C±V curve stretch either at 5 kGy or at 10 kGy than at 300 K. This means that the irradiation at a higher temperature inducts a slight higher density of interface traps than in the case of room temperature irradiation (Fig. 1). Fig. 2 presents the in¯uence of the annealing treatment on irradiation-induced charges and traps in samples C1. After annealing, the distorted curve in the case of 15 kGy room temperature irradiation has only a small stretch and only a voltage shift DV ÿ2 V. That indicates the induction of a positive charge density DNox 1:21 1011 cmÿ2 . The annealing of samples C1 irradiated at 5 and 10 kGy at 500 K almost
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eliminates the previous irradiation induced oxide charge, but remains the interface induced traps. Fig. 3 presents the results of experiments on samples C2. After irradiation even with 5 kGy at 500 K, C±V curves were drastically distorted, i.e. a high level of interface trap density was observed. The positive voltage shifts of C±V characteristics indicate an accumulation of negative charges in oxide. This oxide charge accumulation is DNox 1:4 1011 cmÿ2 for the irradiation at 300 K and 5 kGy, increases at DNox 1:74 1011 cmÿ2 at 10 kGy, and is greater, DNox 2:27 1011 cmÿ2 , in samples irradiated at 500 K and 5 kGy. After the annealing process, the C±V characteristics distortion drastically decreases, but the accumulation of negative charges in the oxide persists. 3.2. Results of the bias-temperature aging experiment on MOS capacitors The main numerical results obtained from the bias-temperature aging experiment described in Section 2 are presented in Table 1. DV represents the voltage shift of C±V curves obtained after the positive and negative voltage stresses applied on the gate, and Nox is the total charge in the oxide corresponding to the DV voltage shift and is calculated with the known relation
Fig. 1. In¯uence of irradiation temperature and dose (without post-irradiation annealing) on samples C1.
Fig. 2. In¯uence of the post-irradiation annealing on C1 samples.
Nox
e0 Kox DV ; qdox
Fig. 3. In¯uence of the irradiation temperature and dose, and post-irradiation annealing on C2 samples.
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Table 1 Irradiation conditions
Samples C1, dox 3500 A
Before irradiation 5 kGy at 300 K 5 kGy at 500 K 10 kGy at 300 K 15 kGy at 300 K 10 kGy at 500 K
DV DV DV DV DV DV
Samples C2, dox 1000±1200 A
5:12 V; Nox 3:1 1011 cmÿ2 ÿ5:51 V; Nox 3:3 1011 cmÿ2 ÿ8:86 V; Nox 5:3 1011 cmÿ2 ÿ5:30 V; Nox 3:8 1011 cmÿ2 ÿ6:80 V; Nox 4:8 1011 cmÿ2 ÿ4:70 V; Nox 3:0 1011 cmÿ2
DV DV DV DV
ÿ0:63 ÿ1:73 ÿ2:52 ÿ3:23
V; V; V; V;
Nox Nox Nox Nox
1:1 1011 cmÿ2 3:6 1011 cmÿ2 5:3 1011 cmÿ2 6:17 1011 cmÿ2
where e0 and q are the permittivity constant in vacuum and the electron charge, respectively, and Kox and dox are the dielectric constant and the thickness of the oxide, respectively. In the non-irradiated samples the voltage shift is dominated by the metal ionic charge movement from the gate electrode to the Si±SiO2 interface under the positive stress, and back to the gate under the negative stress. Irradiated samples subjected to this experiment exhibit, however, a quite dierent behavior. A systematic shift of C±V curves towards higher negative voltages, after positive and equally after negative stress, was registered for samples C1, while a shift towards more positive voltage values after a negative stress was observed for samples C2. Figs. 4 and 5 present the typical results of the bias-temperature experiments on C1 and C2 samples after irradiation in dierent conditions. The negative voltage shift of the C±V curve for C1 samples after the positive
stress reveals the existence of a positive charge in the oxide (Fig. 4). This shift increases when the irradiation temperature is higher. DV ÿ3:75 V when the irradiation was made at 300 K, and DV ÿ4:8 V when the irradiation was made at 500 K. This means that the accumulation of defects generating positive charges in oxide increases with the temperature. After the recent studies [4± 6], the origin of this oxide trap generation in irradiated oxides is attributed to the transport of hydrogen species to the Si±SiO2 interface, where subsequent reaction with Si±H bonds results in creation of trivalent Si defects. Otherwise, the irradiated C2 samples subjected to a positive stress exhibit a positive shift of the C±V curve (Fig. 5). As it was recently demonstrated [7], this is mainly due to electrons captured from the silicon substrate into the oxide, by the positive and neutral charge centers accumulated by irradiation. After a number of electrons are
Fig. 4. C1/Cox ±VG characteristics for samples C1 irradiated at 10 kGy after the bias-temperature aging experiment.
Fig. 5. C2/Cox ±VG characteristics for samples C2 irradiated at 5 kGy after the bias-temperature aging experiment.
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injected, the net negative charges appear due to neutralization of the positive charge centers and the electrons capture by the neutral trap centers. This negative charge is smaller in samples irradiated at 250°C, probably due to predominant eect of positive charge induction by irradiation. After the negative stress, the shifting of C±V curve for samples C2 is in the negative voltage direction, which is due to the positive charge accumulation in the oxide (Fig. 5). The negative stress applied on samples C1 determines a negative shifting of C±V curve (Fig. 4), indicating a further accumulation of positive charge. This charge is greater in the case of samples irradiated at 500 K, i.e. a greater amount of positive charge centers were accumulated in oxide than in the case of 300 K irradiation. 3.3. In¯uence of irradiation dose on VDMOS transistors Fig. 6 presents the switching time variation of high current body-drain junction with the electron irradiation dose, and the threshold voltage variation with the electron irradiation dose. It is important to note that a supplementary annealing (24 h ± 450 K) does not aected the switching time characteristics. The threshold voltage reduction can be attributed to the variation of interface ®xed charge quantity with the irradiation exposure. Fig. 7 presents the blocking characteristics before and
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Fig. 7. VDMOS o-state characteristics evolution for 5 kGy electron irradiation.
after 5 kGy irradiation. The leakage current reduction and the breakdown value improvement are also attributed to the ®xed interface states variation. 4. Conclusions Electron irradiation experiments made at different temperatures on MOS capacitor samples with wet and dry oxides revealed an enhancement of the charge and defects induced in oxides if the irradiation is made at an elevated temperature. Samples with thinner dry oxide were more aected by irradiation exposure than samples with thicker wet oxide. Post-irradiation annealing treatments produced a recovery in C±V characteristics. The bias-temperature aging experiments revealed that the temperature of irradiation enhances the oxide charges induced by irradiation. Electron irradiation experiments made on VDMOS transistors revealed a clear improvement in breakdown voltage, a proportional switching time decreasing with the irradiation dose, and a proportional reduction of the threshold voltage. References
Fig. 6. Switching time variation of the high current body-drain junction, and threshold voltage variation with electron irradiation dose, for VDMOS transistors.
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