Power-constrained testing for bridging and stuck short faults in CMOS combinational circuits

~

Microelectron. Reliab., Vol. 37, No. 5, pp. 753 761, t997 Copyright © 1997 Elsevier Science Ltd Printed in Great Britain. All rights reserved 0026 2714/97 $17.00+.00

1Pergamon

PIh S0026-2714(96) 00060-1

POWER-CONSTRAINED TESTING FOR BRIDGING AND STUCK SHORT FAULTS IN CMOS COMBINATIONAL CIRCUITS ASAD A. ISMAEEL and RAKESH BHATNAGAR Department of Electrical and Computer Engineering, Kuwait University, P.O. Box 5969, Safat 13060 Kuwait

(Received]br publication 15 March 1996) Abstract--An increasing demand for the portable applications has elevated power consumption to be the most critical parameter. A transistor level model and a testing methodology are presented for detected bridging and stuck short faults in CMOS combinatorial circuits, with the power consumption as a major constraint during testing. The circuits are modeled by the CTF (Current Transfer Function) model. The quiescent current (IDDQ) measurement technique is utilized as the testing methodology. Transistor stuck open faults, that can change the test vector for IDDQ, are incorporated in the model. Simulation using hspice is carried out to support the results. Copyright ~ 1997 Elsevier Science Ltd.

1. INTRODUCTION Higher integration and speed in VLSI designs have resulted in increased power consumption and heat dissipation. The increased heat dissipation leads to larger size, higher weight and packaging cost. Designs that minimize the power consumption, without compromising speed, have therefore gained more importance in VLSI designs in the recent past [1-4]. Power dissipation of the circuits has a direct impact on the amount of batteries, a major factor in the size and weight of portable devices [3, 4]. CMOS circuits are known to consume low power. However, even this consumption is too high for the portable applications, and the power consumption needs to be further reduced. Power dissipation during switching has been identified as the main cause of this high consumption. The new design trend is to minimize the power consumption during switching. The energy associated with a switching event is proportional to CLVZoD,where Cg is the capacitance switched (load capacitance) and VDo is the voltage swing associated with the event (assumed equal to the supply voltage) [1]. The designers have addressed the problem of power consumption, if the circuit is fault free. However, the problem of power consumption during testing has not been addressed. Effectively, the portability of testing equipments has not been given much attention. In this paper, we generate the test vectors to detect stuck short and bridging faults in CMOS circuits, with power consumption as a major constraint. The objective is to minimize the power dissipation of the testing equipment/setup. The fault detection based on the IDDQ measurement technique in CMOS circuits has been proved to be quite successful. McEuen has presented the benefits of I D D Q and implementation of I D D Q in terms of

test hardware, test stimulus, test conditions and test locations [5]. Maxwell et al. have presented the effectiveness of IDDQ, functional and scan tests [6]. The importance and implementation of I D D Q testing in CMOS digital ASIC's and CMOS Sea-of-Gate IC's have been presented by Perry, and Sawada and Kayano, respectively [7, 8]. Midkiff and Bollinger have presented the fault classification according to the type of fault, fault location and affected transistor structure. They have also presented the effectiveness of I D D Q for specific physical faults [9]. Lee and Breuer have presented various constraints for using I D D Q testing to detect CMOS bridging faults [10]. A transistor level model based on the I D D Q measurement technique, Current Transfer Function (CTF), was developed earlier for detecting the bridging faults [11]. The CTF for a circuit having a bridging fault represents a general expression that models the I D D Q current flow path between VDDand G N D in terms of the transistor topology and input variables of the circuit. It specifies a vector that sensitizes the path between VDDand GND, which can be considered as the test vector for I D D Q testing. A fault free circuit has a CTF as null (
754

A.A. Ismaeel and R. Bhatnagar

incorporate the power constraint. Bridging and stuck short faults are considered in the CMOS circuits. The CTF modeling is performed by dividing a circuit into a number of sub-circuits called partitions. Only the faulty partitions are required to be modeled by the CTF modeling at the transistor level. The test vectors are derived for the faulty partitions, and their necessary justifications are obtained by applying D-algorithms or its variants. Section 2 presents the various sources of power dissipation. The CTF modeling and test generation are presented in Section 3. The circuits are simulated on hspice and the results are verified. Finally, Section 4 concludes the paper. 2. S O U R C E S OF P O W E R DISSIPATION

There are three sources of power dissipation in CMOS circuits [3, 4]. These are switching, shortcircuit and leakage currents. Thus, the average power dissipation is given by: Pavg = Pswitching q- Pshort-circuit -~- Pleakage" The switching component of power consumption arises due to the capacitive load at the output of the circuit. This component is given by the following equation: Pswitching :

Pt'Energy per transition..(

= P~.c~ v ~ D ' f

where f is the clock frequency and Pt is the probability of a power consuming transition (0 ~ I). Thus, the switching power consumption can be minimized by reducing the supply voltage or the term P~CL. Some designs are now based on low voltage standards (3.3 V instead of 5 V). The term PtCL can be minimized through the choice of logic function, logic style, circuit topology, data statistics, and the sequence of operations. The short-circuit power dissipation component arises due to the direct-path short-circuit current, Isc. This current arises when both pMOS and nMOS transistors of a CMOS gate are simultaneously active, providing a direct current path from VDD to GND. The short circuit power dissipation in a circuit is given as:

CMOS circuit produce high short-circuit current for some specific input vectors. Thus, the short-circuit power dissipation imposes a restriction on testing. The high power dissipation during testing can be minimizd by applying the test vectors that do not lead to high supply currents. This is achieved in the test generation of Section 3. 3. CTF MODELING AND TEST GENERATION To enhance CTF modeling, we divide the circuit into a number of sub-circuits called partitions [5]. The partitions having a fault are called faulty partitions. All the faulty partitions are modeled by the CTF. If a bridge exists between two partitions, they can be combined to form a single partition. The CTF model is utilized to generate the test vectors for detecting bridging faults in CMOS circuits. The CTF generates input vectors in terms of input variables and transistor topology of the faulty partition, which when applied to a faulty circuit, sensitize the path between VDD and GND. For a fault free CMOS circuit, the path between VDD and G N D is never sensitized, thus, the CTF is null (~b). For a faulty circuit, the CTF is utilized to generate a test vector for I D D Q testing. Each pMOS and nMOS transistor has four terminals source, drain, gate and well (or substrate). Normally, the well of a pMOS (nMOS) transistor is connected to VDD(GND) [7]. Hence, a bridge having an end at the well of a pMOS (nMOS) transistor can be considered as a bridge having that end at the VDO (GND). This eliminates the need of considering the terminal "'well" in the model. Each pMOS and nMOS transistor in the faulty partition is modeled by its equivalent model shown in Figs l(a) and (b), respectively, I~ and I~ represent the normal and inverted logical input at the gate of a transistor 7. G~, S~ and Di represent the gate, source and drain junctions of Tf, respectively. The model shown in Figs l(a) and (b) for a MOS transistor is obtained by the following three steps:

Gi

Di .T

(a)

Pshort-circuit = VDD'I~" Finally, the third component of power dissipation arises due to the leakage currents. The leakage currents arise from substrate injection and subthreshold effects, and is primarily determined by fabrication technology considerations. It is obvious that the switching and the leakage components of the power dissipation cannot be utilized to reduce the power dissipation in a circuit at the testing stage. These components impose restrictions on the design and fabrication technology considerations. Bridging and stuck short faults in a

I'i

vDo o...2 i

? oi

"~Gi

--

1

Ii

(b)

Fig. 1. Model for a (a) pMOS transistor, (b) nMOS transistor.

Detecting bridging and stuck short faults (1) A logical variable that appears in a pMOS (nMOS) transistor between its drain and source terminals is a primed (unprimed) input variable. (2) A subscript for each logical variable represents the transistor associated with that logical variable. (3) A logical variable that appears between Vtm (GND) to gate of a transistor is an unprimed (primed) input variable. This is represented by the inputs I~ and I; between VDt,to gate and gate to GND, respectively. The graphical representation of a circuit is obtained by replacing each MOS transistor by its model shown in Figs l(a) or (b) between its gate, source and drain terminals. The proposed bridging faults are inserted into the graphical representation and are represented by a logic value 1. The CTF is obtained from the graphical representation by mapping the elementary path set between VoDand GND. The elementary path set is obtained by using the path algebra technique [12]. The stuck open and stuck short faults, if any in the partition under consideration, can be inserted into the CTF. The Boolean expression obtained is utilized to generate the test vector. Algorithm 1 shows the steps to generate test vectors for a faulty partition. Six variables, "Depth", "Remaining", "Selected", "TV", "Test vector" and DR have been used in the algorithm. "Depth" of an individual term in an expression represented in Sum-of-Product (SOP) form is defined as the number of transistors associated with that term. A path sensitized between VDoand GND, by a term having higher depth, involves larger number of transistors. Hence, the d.c. resistance of this path will be high, and it will result in a lower power consumption, provided all parallel paths are inactive. "Depth" of an expression is defined as the maxima of the depths of its individual terms. The variable "Remaining" contains a set of input vectors (other than "Selected") that sensitize the paths between VDO and GND. Initially, "Selected" is ~b. Hence, "Remaining" contains all the possible input vectors that sensitize the path between VDDand GND. "Selected" selects an input vector from the "Remaining" that has the maximum depth. It is found that this vector cannot be a test vector, it is removed from the "Remaining". Then the next input vector with highest depth is selected. It must be noticed that "Remaining" represents all the parallel paths to the "Selected". "TV" refers to an individual term in the "Test vector". "Test vector" represents the final constrained test vector. DR represents depth of "Remaining". Algorithm 1 (1) Obtain a graphical representation by replacing each pMOS and nMOS transistor of the faulty partition(s) by its equivalent model shown in Figs l(a) and (b), respectively. (2) Insert the proposed bridging faults between the nodes into the graphical representation obtained

755

in step 1. Assume a logic value 1 for these bridges in the graphical representation. (3) The expression that consists of the logic variables and the transistor subscripts is transferred to the adjacency matrix, and the necessary matrix powers are evaluated. (4) The CTF for the faulty partition(s) is (are) obtained by mapping the elementary path set between VDOand GND. If we do not have any bridging fault, this step gives us a general expression for a fault free partition in which the stuck faults can be inserted. This general expression will be utilized to detect the stuck short faults. (5) Transform the CTF in sum-of-product (SOP) form.

(6) Insert the stuck open and short faults, if any in the partition(s) under consideration, into the CTF. This is accomplished by replacing every input variable that has a stuck open (short) transistor as a subscript by 0 (1). (7) At this stage CTF represents a set of input vectors that sensitize the path between Voo and GND. Thus, initialize Remaining = CTF. (8) Initialize, Test vector = ~b TV = qS. (9) Perform the following operation iteratively: While (DR ¢: q~) and (Text vector = gb) (While there is a term of depth DR in the "Remaining" that has never been selected) (i) Select a term of depth DRfrom "Remaining" that has never been selected earlier and assign it to "Selected". (ii) Remove "Selected" term from "Remaining". (iii) Save the "Selected" term in a variable "Temp". (iv) Extract subscripts from "Selected" and simplify. (v) If Selected = ~b, perform next iteration of the inner while loop. (vi) Evaluate TV = Selected. (Remaining). (vii) Extract subscripts from TV and simplify. (viii) Test vector = Test vector + TV. (ix) Remaining = Remaining + Temp. If Test vector = ~b, remove all the terms of depth DR from "Remaining". (10) The test vectors for IDDQ with minimum power consumption is given by the "Test vector". Example 1 Figure 2 shows a single partition for a CMOS circuit implementing the function Y = A'(B'C' + F'E')

756

A.A. Ismaeel and R. Bhatnagar

~/DD 1 G1

S1 T1 D1

2

8

o--4FT2

--O:-41--T

G 3 ,~_.~S 3

G5

yD3

'i

I G8 A

.6

5

D6

]

|

'? 05

Y = A'(B'C'+ F'E')

V D

,t,

t~) S 7

6

t~Sa

1

×

1

o,.J,

[" T 6

|1~$5

.

0

o .io,

o,o O,o I[~T9 E .~[~TIo ;s, TlO

F~

GND T 12 Fig. 2. A CMOS circuit implementing Y = A'(B'C' + F'E'). Generate the test vectors for detecting the bridging fault VOD to node 5. Applying algorithm 1 and replacing each transistor by its equivalent model shown in Fig. l, we obtain a graphical representation as shown in Fig. 3. The bridging fault is inserted between VDDand node 5, and is represented by a thick line. It is assigned a logic value I. The C T F is given by the elementary path set between VDDand G N D . Thus we obtain, C T F = A1A'1 + B2B'2 + C3Cr3 "Jr"F4F'4 + EsE'~ + A6A'6 + B7B'7 + C8C'8 + F9E'9 + EloE'~o + A 6 + (B7 + C8)(F9 + El0 ) = A6 + (B7 + C8)(F9 + EIo). Transforming the C T F into SOP form, we obtain C T F = A 6 + BTF9 + CsF9 + BTE1o + C8E1o. Thus, initializing the following variables to Remaining = A 6 + BTF9 + CsF9 + BTElo + CsElo Test vector = T V = ,~.

The depth of "Remaining" is given by DR=2.

This is due to the fact that the maximum number of transistors associated with an individual term in "Remaining" is 2. Selecting the first term in "Remaining" of depth 2, we get Selected = BTF9. Deleting the "Selected" term from "Remaining", we get Remaining = A 6 + CsF9 + BTEIo + C8Elo Temp = BTF9. Extracting the subscript and simplifying the "Selected" term, we get Selected = BF. Thus, TV = BF(A 6 + C8F9 + BTElo + CaEto )' Extracting subscripts and simplifying we get TV = BF(A + CF + BE + CE)' = BF(A'(C'+ F')(B' + E')(C' + E')) = A'BC'FE'.

757

Detecting bridging and stuck short faults

VDD VDD T

1

F

A'

VDD

VDD T2

B2

IW4 B'2

T

4

VDD

VDD T3

C3 9

EI

E5

C'3

VDD

VDD T

T7

6

5

1

T8

B7

98

VDD

8 -It

A6 A6

VDD T9

VDO

F9

T

F9

10 10

F

GND

E'10

12

Fig. 3. Graphical representation with bridging fault inserted. Thus,

Thus, Test vector = A'BC'FE'.

Adding " T e m p " to "Remaining", we get Remaining = A 6 + BTF9 + C8F9 + BTEzo + CsElo.

Test vector = A'BC'FE' + A'B'CFE'. Adding " T e m p " to "Remaining", we get Remaining

=

A 6

+ B.TF9 + CsF9 + B'~Elo + CsElo.

Selecting the next term of depth DR in "Remaining", we get Selected = CsF9.

Similarly, selecting the other terms BTElo and CsE~o, of depth DR in "Remaining" will give us TV as A'BC'F'E and A'B'CF'E, respectively. Thus, we will obtain

Following the same steps as shown above, we will get

Test vector --- A'BC'FE' + A'B'CFE' + A'BC'F'E

TV = A'B'CFE'.

+ A'B'CF'E.

758

A. A. Ismaeel and R. Bhatnagar

Table 1. The simulated results of example 1 in hspice Input vector A

Fault free

B

C

F

E

Output voltage (V)

1 1 0 1 1 t 0 1 0 0 1 0 1 0 0 0 l 1 0 1 1 0 0 1 1

l 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 1 1 0 0

1 l 1 1 0 1 1 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 1 0 1

1 1 l 0 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 1 0 1 0

65.2143 105.2165 80.3635 105.2165 80.3635 144.3909 117.6919 117.6919 90.5786 287.1156 287.1074 287.0828 266.1985 287.1074 287.0829 266.1986 132.1065 274.5493 212.1537 274.5490 212.1537 301.5301 384.7242 384.7242 467.9177

n n n n n n n n n n n n n n n n n n n n n n n n n

Since there is n o m o r e t e r m of d e p t h 2 in " R e m a i n ing", the i n n e r while l o o p of step 9 of a l g o r i t h m 1 terminates. Also the o u t e r while l o o p t e r m i n a t e s because the Test vector # q~. Hence, the c o n s t r a i n e d test vectors for detecting the fault u n d e r c o n s i d e r a t i o n is given by

Faulty

Power consumption (W)

Output voltage (V)

Power consumption (W)

86.9437 p 116.8955 p 89.2838 p 116.8955 p 89.2838 p 144.3765 p 117.6802 p 117.6802 p 90.5695 p 191.3913 p 191.3858 p 191.3694 p 177.4480 p 191.3858 p 191.3694 p 177.4480 p 88.0622 p 122.0097 p 94.2811 p 122.0096 p 94.2811 p 100.5000p 128.2286 p 128.2286 p 155.9570 p

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

2.5666m 2.1688m 2.1688m 2.1496m 2.1496m 1.9499m 1.9499m 1.9499m 1.9499m 1.3332m 1.3332m 1.3332m 1.3332m 1.3332 m 1.3332m 1.3332m 1.2334m 835.5743 835.5743 p 816.3661 p 816.3661 # 616.6867 # 616.6867 I~ 616.6867 p 616.6867

G N D , we o b t a i n the C T F as: C T F = A t A ' ~ + B2B'2 + C3C'3 + F,F'4 + EsE'5

+ & A ; + B,B'~ + GC'~ + F9F; + E,oEio + A I ( B I C ' 3 + F',,E;)

Test vector = A ' B C ' F E ' + A ' B ' C F E '

+ A ' B C ' F ' E + A'B'CF'E. T h e circuit w h e n s i m u l a t e d using hspice p r o d u c e s the results s h o w n in T a b l e 1. All t h e i n p u t vectors t h a t sensitize a p a t h b e t w e e n VDD a n d G N D are listed. It c a n be o b s e r v e d t h a t the test vectors g e n e r a t e d a b o v e c o n s u m e the m i n i m u m power. It is less t h a n 25~o of the p o w e r c o n s u m e d w h e n the vector A B C F E is applied. T h e fault free values are s h o w n to indicate t h a t the applied i n p u t vectors are the test vectors for I D D Q testing, b u t they m a y n o t be c o n s t r a i n e d . T h e supply voltage is a s s u m e d to be 5 V. Hence, the supply c u r r e n t ( I D D Q ) c a n be c o m p u t e d by dividing the p o w e r c o n s u m p t i o n by 5 V. T h e bridge resistance is t a k e n as 100 f~.

Example 2 F o r the circuit s h o w n in Fig. 2, g e n e r a t e the test vectors for d e t e c t i n g the fault t r a n s i s t o r T 3 stuck short. A s s u m e there is n o b r i d g i n g fault. W e a p p l y a l g o r i t h m 1 a n d insert the p r o p o s e d stuck s h o r t fault in step 6. By replacing e a c h t r a n s i s t o r by its e q u i v a l e n t m o d e l s h o w n in Fig. 1, we o b t a i n a g r a p h i c a l r e p r e s e n t a t i o n as s h o w n in Fig. 4. By m a p p i n g the e l e m e n t a r y p a t h set b e t w e e n Vm~ a n d

'(A~, + (B 7 + C8)(F 9 + ElO))

= A't(B'2C;+F',E'5)(A6+(BT+Cs)(Fg+Eto)). T h i s is the general e x p r e s s i o n for a fault free circuit in w h i c h a n y stuck fault c a n be inserted. T r a n s f o r m i n g C T F i n t o S O P form, we obtain: C T F = A'IB'2CBA~, + A'IB'2C'3BTF 9 + A'IB;C'3BvEio

+ A',B'~C'3C8F9 + A;BIC'3CsE,o + A IF',,E'sA 6 + A', F',,E'sB,G + A', F'eE'sBvEi 0 + A'IF~E'~CsF9 + A;F'4E'sCsElo. T h e v a r i a b l e a s s o c i a t e d with the t r a n s i s t o r 7"3 is C;. R e p l a c i n g it by 1, we get: C T F = A'IB'2A 6 + A'IB'2BTF9 + A'~B'EBTE,o

+ A'IB;CsF9 + A'IB'2CsElo + A', F'gE'sA6 + A',F',,E'sBvF9 + A', F'gE'sBTE,o + A'~F'4E'sCsF9 + A'~FkE'sCsEIo .

Detecting bridging and stuck short faults

759

VII) VDD T1

)

V[X)

VDD T2

P4

B2

B'2

0

T4

)3

VCO

V[~

T3

E5

C3

E~

5

11

9

T5

5

VDD T

B7

T7

6

VDD G7 .?'8

VDD '=8"

6

A6 ~6

VDD

VDD

T9

g9

F9

TIO

Elo~

G10 "1o

GND

112

Fig. 4. Graphical representation without any bridging fault. Initialize the following as: Remaining = A'tB'2A 6 + A'IB'2BTF9 + A'IB'2BTElo + A'qB'2CsF9 + A',B'2CsE,o + A'IF',tE'sA 6 + A'IF',E'sBTF9

Depth of "Remaining" is

D.=5. The terms of depth 5 in "Remaining" are A',F'4E'sB7F9, A',F',,E'sBTE,o , A'xF~E'sCsF9

+ A'IF'aE'sBvExo + A'~F'4E'sCsF9 + A'xF',E'sCsElo Test vector = ~b TV = ~b. HR 37/5-C

and A'IF'4E'sCsElo. However, when we assign these terms to "Selected", extract the subscript and simplify, all these terms are reduced to q~. Hence, no term of depth 5 is left. Since

760

A. A. Ismaeel and R. Bhatnagar

Table 2. The simulated results of example 2 on hspice Input vectors

Fault free

A

B

C

F

E

Output voltage (v)

0 0 0

0 0 0

1 1 1

1 0 1

1 1 0

212.1537 n 301.5301 n 384.7242 n

the "Test vector" is 4~, then we execute next iteration of the outer while loop. The "Remaining" will be reduced to: Remaining = A'IB'2A 6 + A'IB'2BTF9 + A'IB'zBTElo + A',B'2CsF9 + A'1B'zCsElo + A'IF'4E'sA 6 . Now, the depth of "Remaining" will be DR=4. The terms having depth 4 in " R e m a i n i n g " are as follows:

Faulty

Power consumption (w)

Output voltage (v)

Power consumption (w)

94.2811 p 100.5000 p 128.2286 p

1.7953 2.5 2.5

602.8136 # 548.0244 ,u 548.0244 ,u

4. CONCLUSION The importance of minimizing the power consumption during testing is considered in this paper. The methodology presented in this paper is used for detecting the bridging and stuck short faults in C M O S circuits. The test generation utilizes the C T F model. The generation of C T F model is quite simple and systematic. It utilizes path algebra technique. Once the test vectors are generated, the faults can be detected by applying those test vectors and measuring the quiescent supply current. The test vectors generated consume the minimum power out of all possible tests that can be used for I D D Q testing.

A'IB'zBvV9, A',B'zBTElo, A',B'2CsF9, A'~B'2CsEIo and A]FgE'sA 6. The terms A'IB'2BvF9 and A'IB'zBvElo, when selected, will also reduce to q~ upon simplification. Thus, the "Remaining" will be reduced to:

Acknowledgements--The authors would like to acknowledge the research unit at Kuwait University for the support of this work under grant ECE 042.

REFERENCES

Remaining = A] B'2A6 + A'IB2CsF9 + A'IB'2CsE~o + A'~F'4E'~A 6. Selecting the next term of depth 4, we obtain Selected = A'IB'zCsFo Remaining = A'IB'2A 6 + A'~B'2CsEIo + A'IF'4E'sA6 Temp = A'I B'2CsF9. Hence, TV = A'B'CFE'. Similarly, when the term A'IB'2CsEto is selected, we obtain TV = A'B'CF'E. Thus, Test vector = A ' B ' C F E ' + A'B'CF'E. The last term A'tF'4E'sA o of depth 4 will reduce to ~b upon simplification. Hence, we remove this term from "Remaining". Since there is no more term of depth 4 and the "Test vector" is not ~b, we acquire the final constrained test vector as: Test vector = A ' B ' C F E ' + A'B'CF'E. Table 2 shows simulated results of the circuit on hspice. Note that the test vectors A ' B ' C F E ' and A ' B ' C F ' E consume the minimum power.

1. Najm, F. N., A survey of power estimation techniques in VLSI circuits, IEEE Trans. VLSI systems, 1994, 2 (4), 446-455 (1994). 2. Shen, A., Ghosh, A., Devadas, S., and Keutzer, K., On average power dissipation and random pattern testability on CMOS combinational logic networks, IEEE/ACM Int. Conf. on CAD, Santa Clara, CA, USA, 1992, pp. 402-407. 3. Chandrakasan, A. P. and Brodersen, R. W., Minimizing power consumption in digital CMOS circuits, Proc. IEEE, 1994, 83(4), 498-523. 4. Chandrakasan, A. P., Potkonjak, M., Mehra, R., Rabaey, J. and Brodersen, R. W., Optimizing power using transformations, IEEE Trans. CAD Integrated Circuits and Systems, 1995, 14(1), 12-31. 5. McEuen, S. D., DDQ benefits, IEEE VLSI Test Symposium on Chip-to-System Test Concerns for the 1990s, 1991, pp. 285- 290. 6. P. C. Maxwell, R. C. Aitken, V. Johnson and I. Chiang, The effectiveness of IDOQ,functional and scan tests: how many fault coverages do we need?, International Test Conf., pp. 168-177 (1992). 7. Perry, R., IDoo testing in CMOS digital ASIC's--Putting it all together, International Test Conf., 1992, pp. 151-157. 8. Sawada, K. and Kayano, S., An evaluation of lot~ versus conventional testing for CMOS sea-of-gate IC's, International Test Conf., 1992, pp. 158-167. 9. Midkiff, S. F. and Bollinger, S. W., Circuit-level classification and testability analysis for CMOS faults, VLSI Test Symposium on Chip-to-System Test Concerns for the 1990s, 1991, pp. 193-198. 10. Lee, K. J. and Breuer, M. A., Constraints for using IDDQ

Detecting bridging and stuck short faults testing to detect CMOS bridging faults, IEEE VLSI Test Symposium on Chip-to-System Test Concerns for the 1990s, 1991, pp. 303-308. 11. Ismaeel, A. A. and Bhatnagar, R., Modeling and testing for bridging faults in CMOS and BiCMOS combinational circuits, Microelectron. Reliab. In press.

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12. Damper, R. I. and Burgess, N., MOS test pattern generation using path algebra, IEEE Trans., 1987, C-36, 1123-1128. 13. Ismaeel, A. A., Testing for stuck faults in CMOS combinational circuits, IEE Proceedings-G,, 1991, 138 (2), 191-197.