Power dissipation sources and possible control techniques in ultra deep submicron CMOS technologies

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Microelectronics Journal 37 (2006) 851–860 www.elsevier.com/locate/mejo

Power dissipation sources and possible control techniques in ultra deep submicron CMOS technologies Ndubuisi Ekekwe, Ralph Etienne-Cummings Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD 21218, USA Received 29 January 2006; accepted 13 March 2006 Available online 4 May 2006

Abstract As technology scales down into the ultra deep-submicron (UDSM) region, the static power dissipations grow exponentially and become an increasingly dominant component of the total power dissipation in CMOS circuits. With increase in gate leakage current resulting from thinner gate oxides in UDSM and the problems associated with short channel effects, leakage power dissipation is becoming a huge factor challenging a continuous success of CMOS technology in the semiconductor industry. With strict limitations of maximum allowable power (the power being limited more by system level cooling and test constraints than packaging) of 2.8 W (in 2005) to 3 W (in 2020) for battery (low cost/handheld) operated devices as projected by the International Technology Roadmap for Semiconductors (ITRS) 2005, innovations in leakage control and management are urgently needed. This paper presents an overview of the sources of the power dissipation mechanisms in the UDSM technologies, and the device and circuit techniques to control them. r 2006 Elsevier Ltd. All rights reserved. Keywords: Power dissipation; Control techniques; Submicron CMOS; Leakage current; Semiconductor roadmap

1. Introduction The evolution of CMOS integrated circuit is a major milestone in the history of modern industry. It has driven a revolution in computing capability due to a long trend in increased performance, higher device density, and lower cost with scaling [1]. As the technology scales down to the ultra deep-submicron (UDSM), there are number of challenges to the continuing success of CMOS in the semiconductor industry. These challenges fall into the broad categories of reliability, variability, signal integrity, speed, and power problems [2]. Over the years, enhancing chip performance has come through increased circuit complexity and number of transistors. But despite down scaling of circuit propagation delay, supply and threshold voltages for every technology generation, the power dissipation in circuits has continued to increase. This increase is costly in terms of shorter battery life, complex cooling and packaging methods, and degradation of system performance. Corresponding author. Tel.: +1 410 235 2940; fax: +1 410 516 2939.

E-mail address: [email protected] (N. Ekekwe). 0026-2692/$ - see front matter r 2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2006.03.008

Power dissipation in CMOS circuits involves both static and dynamic power dissipations [3]. In the submicron technologies, the static power dissipation, caused by leakage currents and subthreshold currents contribute a small percentage to the total power consumption, while the dynamic power dissipation, resulting from charging and discharging of parasitic capacitive loads of interconnects and devices dominates the overall power consumption. But as technologies scale down to the UDSM (see Fig. 1[4,5]), the static power dissipation becomes more dominant than the dynamic power consumption [1]. And despite the aggressive downscaling of device dimensions and reductions of supply voltages, which reduce the power consumption of the individual transistors, the exponential increase of operating frequencies results in a steady increase of the total power consumption. Eq. (1) gives the relationship between dynamic power consumption (P), capacitance (C), frequency (f), technology factor (k) and Vdd [1,5]. P ¼ k:C:f :V 2dd

(1)

Based on data from the ITRS 2005 [6], this trend would continue as feature sizes of transistors continue to scale

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down. Consequently, if power dissipation, especially the static power dissipation, is not controlled and optimised carefully, it promises to become a major limiting factor for system integration and performance improvement [7–14]. Transistors consume static power when they are not switched ON having a small, so called leakage current flowing through them [8]. Over the years, this leakage current has continued to increase as technology scales down (Fig. 2) even though the OFF resistance of the devices decreases. Potential problems and challenges associated with leakage currents are many and vary with applications. Some of them are the requirements for sophisticated cooling methods, large battery sources and management of dynamic noise immunity. These factors adversely affect applications especially in portable and wireless electronic devices. Eq. (2) [1] gives the standby power of a CMOS chip due to source-to-drain subthreshold leakage.
 qV th Poff ¼ W tot V dd I off ¼ W tot V dd I O exp
, (2) mkT Micron

Ultra deep submicron

Deep submicron

Submicron

80286 16MHz

2.0

80386

Lithography (µm)

1.0

33MHz

486 66MHz

0.3

Pentium 120MHz

0.1 0.05

86

89

92

95 Year

98

01

Fig. 1. Evolution of lithography [4,5].

04

Table 1 shows the 2005–2020 Roadmap for power supply and power dissipation for CMOS circuits obtained from the ITRS 2005 [6]. As technology scales, strict limitation of the allowable maximum power for battery (low cost/handheld) operated systems is projected; from 2.8W in 2005 to only 3W in 2020. Within this period, the Vdd for high performance systems is expected to scale down by 36% while the allowable maximum power for high performance (with heatsink) devices will increase by only 19%. Short channel effects and gate leakage current would become very prominent in the UDSM due to shorter

Chip characteristics/Production year

Research

83

2. Brief Summary of 2005–2020 power supply and power dissipation roadmap

Table 1 Roadmap trends 2005–2020 for power supply and power dissipation [6]

Industry Pentium III 0.7GHz Pentium IV 3GHz

Pentium II 300MHz

0.2

where Wtot is the total turned-off device width with Vdd across the source and drain, Ioff is the average off-current per device width, I0 is the extrapolated current per width at threshold voltage, m is a dimensional factor, and Vth is the threshold voltage. This paper is organized as follows: brief summary of 2005–2020 power supply and power dissipation roadmap is discussed in Section 2; Section 3 discusses the sources of leakage current in CMOS circuits. Section 4 discusses the leakage control techniques and Section 5 gives the final conclusions.

07

Power supply voltage (V) Vdd (high performance) Vdd (low operating power, high vdd transistors) Allowable maximum power (W) High performance with heatsink Cost-performance Battery—(low cost/handheld)

2005 2006 2008 2013 2016 2020

1.1 0.9

1.1 0.9

1.0 0.8

0.9 0.6

0.8 0.5

0.7 0.5

167 91 2.8

180 98 3.0

198 111 3.0

198 137 3.0

198 151 3.0

198 157 3.0

Fig. 2. Scaling of static current and OFF resistance of CMOS transistor [4].

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features sizes and thinner gate oxide thickness respectively. Early availability of high-k dielectrics would be necessary to meet the stringent gate leakage especially in low power devices. There would be problems associated with controlling the threshold voltage as a result of non-uniform doping as technology scales. With time, the performance of copper/low-k interconnects will become inadequate to meet the speed and power dissipation goals of highly scaled ICs [6]. 3. Sources of leakage currents in CMOS circuits There are five major sources of leakage currents (see Fig. 3) in CMOS transistors and their understandings are important prerequisite to developing techniques to effectively control them. They are: (A) (B) (C) (D) (E)

Gate oxide tunnelling leakage (IG). Subthreshold leakage (ISUB). Reverse-bias source/drain junction leakages (IREV). Gate Induced Drain Leakage (IGIDL). Gate current due to hot-carrier injection (IH).

Fig. 4 shows the variation of some leakage components with oxide thickness and channel length [11]. It is evident that decrease in both the gate oxide thickness and channel length result to increase in leakage current. For very thin oxides, the gate direct leakage current is dominant while for thicker ones, the junction and subthreshold leakage currents are most prevalent. 3.1. Gate oxide tunnelling leakage The downscaling of the gate oxide thickness increases the field oxide across the gate resulting to electron tunnelling from gate to substrate or from substrate to gate [11,15,16]. The resulting current is called gate oxide tunnelling current. Two mechanisms are responsible for this phenomenon. The first is called Fowler-Nordheim (FN) tunnelling mechanism, which is electron tunnelling into the conduction band of the oxide layer. Ignoring the effect of finite temperature Source

Gate

Drain

IH IG

N+

N+

ISUB IP P substrate

IGIDL

IREV

Fig. 3. Leakage current components in NMOS transistor.

Fig. 4. Variation of different leakage components with oxide thickness and channel lengths.

and image-force-induced barrier lowering, the current density on the FN tunnelling is given by Eq. (3) [16]
pffiffiffiffiffiffiffiffiffi 1:5  q3 E 2ox
4 2m fox J FN ¼ exp , (3) 16p2 _fox 3_qE ox where Eox is the field across the oxide, fox is the barrier height for electrons in the conduction band; m* is the effective mass of an electron in the conduction band of silicon, q is the electronic charge; _ is 1/2p times Planck’s constant. Because this equation is valid for V ox 4fox , where Vox is the voltage drop across the oxide, current due to FN is negligible since short channel devices operate at V ox 4fox [17]. The other mechanism, direct tunnelling, is more dominant than the FN. In this case, electron tunnel directly to the gate through the forbidden energy gap of the silicon dioxide layer [16]. The resulting current is called the gate direct-tunnelling leakage and it flows from the gate through the oxide insulation to the substrate. In attempts to keep adverse 2D electrostatic effects on threshold voltage under control, gate-oxide thickness is reduced nearly in proportion to channel length in every CMOS generation [8–10,18]. This reduction has made this leakage current to be very significant. The direct tunnelling current density is given in Eq. (4) [17,19]. " " #  3=2 # V ox J DT ¼ AE 2ox exp
B 1
1
E
1 ox , fox pffiffiffiffiffiffiffiffiffi q3 4 2m f3=2 ox A¼ , ð4Þ ;B ¼ 16p2 _fox 3_q where V ox 4fox ; Eox is the field across the oxide, fox is the barrier height for electrons in the conduction band; m* is the effective mass of an electron in the conduction band of silicon, q is the electronic charge; _ is 1/2p times Planck’s constant.

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It is the major leakage current in the UDSM [11] unlike in the submicron technologies, where other leakage currents dominate. A possible effective approach to overcome the gate leakage currents while maintaining excellent gate control is to replace the highly used silicon dioxide gate insulator with high-k dielectric material like TiO2. Use of the high-k dielectric will allow a less aggressive gate dielectric thickness reduction while maintaining the required gate overdrive at low supply voltages [9]. Another possible means to reduce this leakage is multiple oxide thickness technique where higher oxide thickness transistors are used in non-critical paths while the thinner oxide transistors are used in critical paths [11]. However, increasing the oxide thickness would require longer channel lengths to avoid short channel effects. 3.2. Subthreshold leakage The subthreshold leakage is the drain-source current of a transistor during operation in weak inversion [12]. Unlike the strong inversion region in which the drift current dominates, the subthreshold conduction is due to the diffusion current of the minority carriers in the channel for a MOS device. The magnitude of the subthreshold current is a function of the temperature, supply voltage, device size, and the process parameters [9]. This relationship is presented in Eq. (5) [3]:
h i W I sub ¼ I x (5) 1
e
ðV ds =V T Þ e
ðV gs
V th Þ=S , L where S, the subthreshold slope, is given by Eq. (6).  
1
 d 2:3kT C dm 1þ S¼ lnðI D Þ ¼ , dV gs q C ox

bulk voltage of 0 to
0.5 V. The figure shows that the current increases as the Vth decreases. A better illustration is shown in a semilog plot shown in Fig. 6 where the leakage currents are observed at Vgs ¼ 0.4 V. Also, at a temperature of 1271C (see Fig. 7), the leakage current increases by nearly a factor of 100 indicating a strong relationship between leakage current and temperature. Two factors increase the subthreshold current as the temperature is increased; decrease in threshold voltage, and the linear increase of subthreshold slope with temperature. Eq. (7) [3,5] shows the various factors that affect the threshold voltage based on the Berkeley Short Channel IGFET-4 (BSIM4) model, which models the MOS transistor operation in the deep submicron technologies. pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi V th ¼ V tho þ K1: fs
V bs
fs
K2:V bs þ D, (7) where D ¼ DVtSCE þ DVtNULD þ DVtDIBL . Vtho is the long channel threshold voltage at V bs ¼ 0; K1 is the first order body bias coefficient; Vbs is the body-source voltage; fs is

103 104 105 Ids(A)

854

(6)

Vds is the drain–source voltage; VT is the thermal voltage; Vgs is the gate–source voltage; W is the transistor width; L the transistor length; Cox is the gate oxide capacitance; Cdm is the capacitance of the depletion layer. Fig. 5 shows the simulated drain current (Ids)) versus Vgs of an NMOS transistor in a 50 nm process (27 1C) at the

vb=0.00 vb=-0.10

106 107 108

vb=-0.20 vb=-0.30

109

vb=-0.40

1010

vb=-0.50

10

11

0.10

0.20

0.30

0.40

0.50

0.60

0.70

0.80

VGS

Fig. 6. Simulated log (Ids) vs. Vgs of an NMOS transistor in a 50 nm process (27 1C) at the bulk voltage of 0 (topmost) to
0.5 V. W ¼ 0.65 mm, L ¼ 0.05 mm.

103 104

Ids(A)

105 106 10

vb=0.00 vb=-0.10

7

vb=-0.20

108 109

vb=-0.30 vb=-0.40

1010

vb=-0.50

1011 0.10

Fig. 5. Simulated Ids vs. Vgs of an NMOS transistor in a 50 nm process (271C) at the bulk voltage of 0 V (topmost) to
0.5 V. W ¼ 0.65 mm, L ¼ 0.05 mm.

0.20

0.30

0.40 VGS

0.50

0.60

0.70

0.80

Fig. 7. Simulated Ids vs. Vgs of an NMOS transistor in a 50 nm process (127 1C) at the bulk voltage of 0 (topmost) to 0.5 V. W ¼ 0.65 mm, L ¼ 0.05 mm.

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(i) Short channel effect (SCE). In MOS devices, the threshold voltage relationship between the long and short channel is not the same [5,18]. There exits a complex dependence, which for smaller channels, the threshold voltage tends to decrease thereby increasing the subthreshold current. The physical origin of this effect is due to the extension of the depletion region of the channel to the isolating field oxide. For conduction in the channel, the gate voltage must support this extra depletion charge. For a large channel, this effect is ignorable; however, for a short one as in the UDSM devices, it is significant resulting to an increase in the Vth. This complex dependence between the threshold voltage and the channel length is expressed in Eq. (8) [5] and illustrated in Fig. 9. DVtSCE ¼


0:5Dvto ðVbi
fs Þ , coshðDvt1 ðLeff =ltÞ
1Þ

(8)

where Dvto is the first coefficient of the short channel on the threshold voltage, Dvt1 is the second coefficient of the short channel on the threshold voltage, Leff is the effective length, lt is the characteristic length, Vbi is the built in potential and fs, is the surface potential. (ii) Drain induced barrier lowering (DIBL ). The threshold voltage of long channel device is largely independent of the source-to-drain voltage (Vds) whereas in ultradeep submicron devices, which have short channels, there is a decrease in the threshold voltage required for conduction to occur as shown in Fig. 8 [5,18]. The origin of this effect is the increase of the depletion layer due to a high value of Vds which reduces the equivalent channel length and consequently decreases the threshold voltage [5]. The resulting effect is increase in the subthreshold leakage current. For high enough values of the drain voltage, the source and the drain regions can be shorted together resulting to a sharp increase in current called punchthrough current (Ip) [18], indicated in Fig. 8. A simple model of DIBL is given

Due to non-uniform LDD

Vth

the surface potential; Vbs is the bulk-source voltage; K2 is the second order body bias coefficient; DVtSCE is the short channel effect on Vth; DVtNULD is the non-uniform lateral doping effect; and DVtDIBL is the drain induced barrier lowing effect of channel on Vth. Each of these factors is discussed next.

855

Due to short channel ff Channel length

Fig. 9. Illustration of channel effect and non-uniform lateral doping (LDD) in short channel MOSFET. The upper curve shows the effect of NULD while the lower one shows the effect of SCE. The two curves are not related, i.e, there is no implication that Vth due to NULD is bigger than SCE.

in Eq. (9) [5] DVtDIBL ¼
0:5E TA0 V ds ,

(9)

where ETA0 is the DIBL coefficient in the subthreshold region and Vds is the drain-source voltage. (iii) Non-uniform lateral doping (NULD). Lateral drain diffusion (LDD) is a method used in most modern technologies to reduce the peak channel fields in the MOS channel. In MOS devices, there exists a high doping concentration at the corners of the gate/source and gate/drain junctions creating a high field parasitic effect within these locations [4,5]. By depositing a light diffusion on these corners, the doping concentration is reduced and the effect mitigated. In situations where the lateral doping is non-uniform, the threshold voltage tends to increase at first before being influenced by the short channel effects as illustrated in Fig 9. This phenomenon is expressed by Eq. (10) sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ! pffiffiffiffiffi LPE0 DVtNULD ¼ K1 fs , (10)
1 1þ Leff where Leff is the effective channel length, LFE0 is lateral non-uniform doping parameter. (iv) Body bias effect. Eq. (7) shows that an increase in the source-body bias would increase the threshold voltage due to a widening of the bulk depletion region [18]. The result of the effect is the reduction of the subthreshold current. Fig. 10 shows the effect of back biasing an NMOS device in a 50 nm process with bulk voltage of 0 to –0.5 V as Vgs increases from 0 to 1.5 V. It is evident that the leakage current decreases as the back bias voltage increases.

Vth

3.3. Reverse-bias source/drain junction leakages

Drain-source voltage Fig. 8. DIBL effect for short channel MOSFET.

Though the p–n junctions between the source/drain and the substrate are reverse-biased, yet a small amount of current flows causing these junctions to leak [18]. This current is called reverse biased junction leakage current. The magnitude of this current depends on the area of the source/drain diffusion and the current density, which is in turn determined by the doping concentration. The highly

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band tunnelling currents there, especially as drain–bulk voltage (Vdb) is increased. Thinner oxide and higher supply voltage increase GIDL current. Controlling the doping concentration in the drain of the transistor is the best way to control GIDL. 3.5. Gate current due to hot-carrier injection (IH)

Fig. 10. Simulated Ids vs. Vgs of an NMOS transistor in a 50nm process (27 1C) at the bulk voltage of 0 (topmost) to
0.5 V. W ¼ 0.65 mm, L ¼ 0.05 mm.

doped shallow junctions and halo doping necessary to control SCE in the UDSM devices has escalated this leakage current [1,12,16]. Under this situation, electrons tunnel across the p–n junction causing junction leakage. The tunnelling current density resulting from this leakage phenomenon is given by Eq. (11) [16] ! BE 3=2 EV app g J b ¼ A 0:5 exp
, E Eg pffiffiffiffiffiffiffiffiffi 3 pffiffiffiffiffiffiffiffiffi 2m q 4 2m , ð11Þ ;B ¼ A¼ 3q_ 4p3 _2 where m* is the effective mass of electron, Eg is the energy bandgap; Vapp is the applied reverse bias; E is the electric field at the junction; q is the electronic charge; _ is 1=2p times Planck’s constant. Assuming a step junction, the electric field at the junction is given by Eq. (12) [16] sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2qN a N d ðV app þ V bi Þ E¼ , (12) esi ðN a þ N d Þ where Na and Nd are the doping in the p and n side, respectively; esi is the permittivity of silicon; and Vbi is the built in voltage across the junction. A reduction in the substrate doping near the substrate-drain/source junction is an effective way to reduce this leakage. Unfortunately, this increases the SCE resulting to considerable increase in the Isub [11].

This leakage current is due to drift over time of the threshold voltage in short channel devices [18]. The high electric field near the Si–SiO2 interface can cause electrons or holes to gain sufficient energy to overcome the interface potential and enter into the oxide layer. In this phenomenon known as hot carrier effect, the electron injection is more likely to occur than the hole as electron has both lower effective mass and barrier height than hole [16]. These carriers trapped in the oxide layer change the threshold voltage of the device and consequently the subthreshold current. Proportionate scaling down of the supply voltage with the device dimension is one possible way of controlling this leakage. 4. Leakage control techniques Among the different leakage currents in the UDSM, the subthreshold and gate leakage are the most dominant. While the latter is mainly due to electron tunnelling from the gate to the substrate, the former is caused by many other factors. As a result, the leakage control techniques to be discussed will focus more on subthreshold currents. Over the years, many techniques have been developed to reduce the subthreshold currents in both the active and standby modes in order to minimize the total power consumption of CMOS circuits. While the standby leakage currents are wasted currents when the circuit is in idle mode where no computation takes place, the active leakage currents are wasted current when the circuit is in use. Generally, reduction of leakage currents involves application of different device and circuit level techniques. At the device level, it involves controlling the doping profiles and physical dimensions of transistors [8,13] while at the circuit level, it involves the manipulation of Vth and source biasing of the transistor [14]. 4.1. Circuit level leakage control techniques

3.4. Gate induced drain leakage (GIDL) This leakage current is caused by high electric field effect in the drain junction of MOS transistors [9,12,16]. Over the years, transistor scaling has led to increasingly steep halo implants, where the substrate doping at the junction interfaces is increased, while the channel doping is low [9]. Its purpose is to control punch-through and draininduced barrier lowering with minimal impact on the mobility of the carrier in the channel. The steep doping profile that results at the drain edge increases the band-to-

4.1.1. Multi Vth techniques This technique involves fabrication of two types of transistors, high Vth and low Vth transistors, on a chip [9,12,16]. The high Vth is used to lower the subthreshold leakage current, while the low Vth is used to enhance performance through faster operation. Obtaining these different types of transistors is done through controlled channel doping, different oxide thickness, multiple channel lengths or multiple body biases. Notwithstanding, with technology scaling and continuous decrease in the supply

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voltage, the implementation of the high Vth transistor will become a major practical challenge. Dual threshold method. In logic circuits, leakage current can be reduced by assigning higher Vth to devices in noncritical paths, while maintaining performance with low Vth in the critical paths [11]. This technique is applicable to both standby and active mode leakage power dissipation control. It ensures that the circuit operates at a high speed and reduced power dissipation. Multi-threshold voltage method. As shown in Fig. 11, this method uses a high Vth device to gate supply voltage from a low Vth logic block thereby creating a virtual power rail instead of directly connecting the block to the main power rail. The high Vth switches are used to disconnect the power supplies during the standby state, resulting in very low leakage currents set by the high Vth of the series logic block [9,10,19]. In active mode operation, the high Vth transistors are switched on and the logic block, designed with low Vth, operates at fast speed. This enables leakage current reduction via the high Vth and enhanced performance via the low Vth block. Alternatively, this system could be implemented with a high Vth NMOS transistor connected between the GND and the low Vth block. The NMOS transistor insertion is preferred to the PMOS since it has a lower on-resistance at the same width and consequently can be sized smaller [16,18]. The use of these transistors increases circuit delay and area. Besides, to retain data during standby mode, extra high Vth memory circuit is needed. Due to the difficulty of making high Vth transistors in the UDSM with very low supply voltage, Super Cutoff CMOS (SCCMOS) [19] has been proposed as shown in Fig. 12. SSCMOS uses low Vth transistors with an inserted gate bias generator. For active mode, the gate of the inserted PMOS (NMOS) is connected to 0V (VDD) and in standby mode, the gate is applied to VDD+DV (VSS-DV) to fully cut off the leakage current [19]. The major drawbacks to this technique are area overhead and performance degradation [12]. Variable Vth method. This is a method mainly used to reduce standby leakage currents by using a triple well process where the device Vth is dynamically adjusted by biasing the body terminal [11,12,20]. Through application

Fig. 11. Multi-threshold leakage current control.

857

Fig. 12. Super cutoff CMOS leakage current control.

Fig. 13. Dynamic Vth scaling scheme hardware.

of maximum reverse biasing during the standby mode, Vth is increased and the subthreshold leakage current minimized. In addition, this method could be applied in active mode operation to optimize circuit performance by dynamically tuning the Vth based on workload requirements [12]. Through this tuning capability, the circuit is able to operate at the minimal active leakage power. Dynamic Vth method. This is a method used in active mode operation to control the leakage current in a circuit based on the desired frequency of operation. The frequency is dynamically adjusted through a back-gate bias in response to workload of a system [11]. At low workload, increasing the Vth reduces the leakage power. A block diagram of this control scheme is shown in Fig. 13 [20]. An error signal, generated from the difference between a reference clock frequency and oscillator frequency is fed into a feedback controller. The controller is used to generate body bias signals for the transistors in the system block. The continuous loop also compensates for temperature and supply voltage variations in the design [11,20]. 4.1.2. Body bias control As shown in Eq. (7), body biasing a transistor is an effective way of reducing both the active and standby

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leakage through its impact of increasing the threshold voltages of the MOS transistors. By applying a reverse body bias, the Vth is increased and subsequently reduces the subthreshold leakage currents [12]. This could be done during standby mode by applying a strong negative bias to the NMOS bulk and connecting the PMOS bulks to the VDD rail. Body biasing is also used to minimize DIBL effect and Vth-Rolloff associated with SCE. The Variable Threshold CMOS technique described above utilises body biasing to improve circuit performance [9,12]. It is important to note that the Vth is related by the square root of the bias voltage implying that a significant voltage level would be needed to raise the Vth. This could be a potential challenge in the UDSM where the supply has been severely scaled down.

4.1.3. Minimum leakage vector method The fundamental concept in this technique is to force the combinational logic of the circuit into a low-leakage state during standby periods [12]. This state enables the largest number of transistors to be turned off so as to reduce leakage and make use of multiple off transistors in stacks. Consider Table 2 [9], the leakage current of a two-input NAND gate built in a 0.18 mm CMOS technology with 0.2 V threshold voltage and 1.5 V supply voltage. It could be seen that the maximum leakage current is nearly three times the minimum leakage current. Also, there is difference between the leakage vector of A ¼ 0, B ¼ 1 and A ¼ 1, B ¼ 0 due to body effect. From this table, it is observable that logic gates exhibit a leakage current behaviour with respect to the applied input pattern and leakage current of a circuit is a strong indication of its input values [9]. Utilizing this concept, different algorithms are used to find the lowest leakage input vector pattern, which will minimize the leakage current, the most. Circuit size, complexity and size are some of the factors that determine the best-input vector pattern. Abdollahi et al. [21] formulated the problem of finding the minimum leakage vector (MLV) using a series of Boolean Satisfiability problems. Halter et al. [22] used an algorithm that uses a probabilistic theory to search a large number of random inputs looking for best MLV based on a certain confidence and error tolerance. Fig. 14 shows a CMOS gate and a possible way to modify it in order to reduce leakage current [9]. Addition of a transistor in series to either the P Table 2 Leakage values of a NAND gate [9] Input

Output

A

B

O

0 0 1 1

0 1 0 1

1 0 0 0

Leakage current (nA)

23.06 51.42 47.15 82.94

Fig. 14. CMOS gate and its modified version in reducing leakage at standby mode.

Fig. 15. Effect of transistor stacks in minimizing subthreshold current Vx4Vy40V .

or N networks provides a stacking effect, which lowers the leakage current. In the figure, an NMOS has been used in series to the N network; another alternative is to use a PMOS in series with the P network. The output of the circuit depends both on the input and control signals (sleep_bar) unlike in the CMOS gate which depends solely on the input signal. This arrangement shows how circuit internal signals could be controlled through modification of its gates. 4.1.4. Stack effect-based method The ‘‘stacking effect’’ is the reduction in subthreshold current when multiple transistors connected in series (in a stack) are turned off [11,12]. The transistor stacking (see Fig. 15) increases the source bias of the upper transistors in the stack as well as lowers the gate-source voltage (Vgs) of these transistors. All these effects contribute to lower subthreshold leakage current in the circuit. Minimizing leakage through transistor stacking depends on the pattern of the input sequence during standby periods as it

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determines the number of OFF transistors in the stack [11]. Finding the low leakage input vector involves either a complete enumeration of the primary inputs or random search of the primary inputs. While the former is used for small circuits, the latter is applied for more complex circuits. The idea is to use the input vector to determine the combination that results to the least leakage current [16]. When the input vector is obtained, the circuit is evaluated and if necessary, additional leakage control transistors are inserted in series at the non-critical paths to be turned OFF during the standby mode. Eq. (13) expresses a model of leakage reduction factor, X, due to a stack of two series OFF devices [10] as X ¼ 10ðld V dd =sÞð1þld =1þ2ld Þ ,

(13)

where S is the subthreshold swing; ld is the DIBL. This model assumes that the intermediate node voltage in the stacked transistors to be greater than 3kT/q [10]. 4.2. Device level leakage control techniques Silicon-on-insulator (SOI): This is a non-bulk technology that builds transistors on top of insulating layer instead of a semiconductor substrate. Using insulating layer reduces parasitic capacitance, which results to higher operational speed and lower dynamic power dissipation in integrated circuits [1,3]. Though the early SOI used crystals like sapphire, emerging technologies favour the use of silicon wafer, making it economically attractive. The ITRS 2005 projects the use of Ultra-thin body (UTB) SOI by 2008 to manage the increasing effects of leakage [6]. Double gate MOSFET (DG-MOS): In traditional bulk and SOI devices, immunity from SCE like Vth-rolloff and DIBL requires increasing the channel doping to enable reduction of the depletion depth in the substrate. The inherent drawbacks to this approach are increased substrate-bias sensitivity and degraded subthreshold swing. By replacing the substrate with another gate to form a double gate MOSFET, short channel immunity is achieved with an ideal subthreshold swing [23]. The arrangement is shown in Fig. 16. Separation by implantation of oxygen (SIMOX): This is a more modern and elegant technique for making the SO1

Source

Gate

Drain

859

structure by implanting heavy doses of oxygen directly into a silicon substrate [3]. The wafer is then annealed at very high temperatures, which induces oxide growth below the wafer surface and pushes a top layer of silicon on the top. The resulting SOI consumes lesser power than the bulk technologies. Other methods used in device level control include retrograde doping and halo doping [8,16]. Retrograde doping is a vertically non-uniform, low-high doping used to improve SCE and reduce mobility degradation and threshold mismatch by creating a low surface channel concentration followed by a highly doped surface [16,23]. While the low surface concentration increases surface channel mobility by minimizing channel impurity scattering, the highly doped subsurface acts as a barrier against punchthrough. The resulting effect is reduction to leakage current. Halo doping on the other hand is a laterally nonuniform profile introduced to manage the dependence of threshold voltage on channel length. The aim is to reduce the charge sharing effects from the source and the drain fields thereby reducing the depletion widths in the source–substrate and drain–substrate regions [16]. Taur [1,8] suggested the use of super-halo doping design to enable further scaling in the UDSM, by providing a means of controlling the depletion width despite further reduction in the channel width. This is done via abrupt optimised vertically and laterally non-uniform doping. 5. Conclusions As CMOS technology continues to scale down, leakage currents will become increasingly large due to the effects of electron tunnelling, short channel effects and other factors discussed in the paper. Managing these leakages by developing better circuits and processes would be vital to the continuous dominance of CMOS technologies in the semiconductor industry. The ITRS 2005 projects a 36% down scaling of the Vdd and allowable maximum power (with heatsink) increase of only 19% from 2005 to 2020 for high performance systems. Much of this allowable power would be leakage power, which is increasing at a much faster rate than the active power [24]. Thus, evolution of efficient control techniques in all aspects of CMOS design is needed to manage it. Acknowledgement The NSF provided the funding and research infrastructure for this work under ERC cooperative agreement EEC9731478.

Gate

References Channel

Fig. 16. Schematic cross section of DG-MOSFET.

[1] Y. Taur, E. Nowark, CMOS devices below 0.1 um: how high will performance go?, Electron Devices Meeting, Technical Digest., International Publication, 7-10 December 1997, pp. 215–218.

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