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Power semiconductor devices for the 1990s
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World Abstracts on Microelectronics and Reliability
2. RELIABILITY OF COMPONENTS, TUBES, TRANSISTORS AND ICs Rework of multi-chip modules: device removal. J. CHANG and C. SPOONER. Circuit World, 19(2), 13 (1993). This paper will review rework of multi-chip modules (MCMs). The issues of die removal from substrates (i.e. PCBs) with different chip-to-substrate interconnect technologies will be explored in detail. These different interconnect technologies (e.g., wire bonding, tape automated bonding and flip chip bonding) and die-attachment methods (e.g., eutectic and adhesive) have a strong influence on the MCM rework process and equipment selection. Traditional surface mount (SM) and current MCM rework technologies are also compared. It will be shown that traditional SMT rework processes and equipment are unable to solve the level of difficulty involved in fine-pitch MCM device removal--especially for systems which require heat removal through the substrate. A new type of fiber optic connector designed for military optical backplanes. R. J. PIMPINELLA. IEEE Transactions on Components, Hybrids and Manufacturing Technology, 15(6), 992 (1992). A new type of fiber optic connector designed to meet military stress requirements has been demonstrated. This reliable optical card-edge (ROC) connector is a multifiber backplane connector (four fibers, blind mate). The connector uses a unique expanded beam coupling design and micromachined silicon optical subassemblies to provide optimum coupling under high levels of shock and vibration. An additional feature of the ROC connector is its ability to self-seal or shield the optical fiber ends when unmated, protecting the fibers and internal mechanisms from environmental contamination and abusive handling. In this paper we discuss the design features of the ROC connector with respect to military stress requirements and present the prototype test results. Is boundary scan short on fault coverage? GORDOND. ROBINSON. Test and Measurement World, 71 (February 1993). By using a combination of test methods, you can maintain high fault coverage of shorts tests, even for boards with boundary-scan parts.
Experimental and analytical studies of encapsulated flip chip solder bumps on surface laminar circuit boards. J. LAU et al. Circuit World, 19(3), 18 (1993). The mechanical and thermal responses of encapsulated flip chip solder bumps on a surface laminar circuit (SLC) board have been determined in this study. The mechanical responses of the solder bumps and encapsulant have been obtained by shear, tension and torsion tests. The thermal stress and strain in the solder bumps and encapsulant have been determined by a non-linear finite element method and the thermal fatigue life of the corner solder bump is then estimated based on the calculated plastic strains,
Coffin-Manson law and isothermal fatigue data of solders. Also, an assembly process of the test boards is presented.
Design of precision capacitors for analog applications. STEPHEN A. ST. ONGE el al. IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 15(6), 1064 (1992). Precision capacitors are important elements in linear designs. One important source of error in the linearity of analog-to-digital converters (ADC's) is the variation of capacitance with applied voltage. This paper describes and analyzes two capacitors which are incorporated in a baseline BiCMOS technology without added process complexity. The first capacitor is formed between degenerately doped polysilicon and silicon. The second is formed between two degenerately doped polysilicon layers. In both structures, the insulator is a deposited or grown oxide. The sensitivity of the capacitor voltage coefficient to oxide thickness and surface dopant concentration is discussed theoretically and compared to measured data. The two capacitors are optimized to exhibit very low voltage coefficients. Fixed resistors serve to reduce equipment size. IWAO TSUCHIHASHI. JEE (Japan), 85 (1993). In 1991, the production of fixed resistors in Japan amounted to ¥138.9 billion or 124 billion resistors. The quantity of chip resistors accounted for more than 70% of all fixed resistor production. The size of the chip resistor was reduced from 3216 (3.2 × 1.6mm) to 2125 (2 × 1.25) or to the popular 1608 (1.6 x 0.8 mm) level. Some portable units use chip resistors of 1005 (1 × 0.5 mm) size. The chip resistor holds a lead over other surface-mounted devices (SMDs) for reduction in size. Ultra-miniature chip inductors for communications equipment down-sizing requirements. MITSUO SAKAKURA.JEE (Japan), 62 (May 1993). Chip fixed inductors are vital components for today's mobile communications and satellite receiver equipment. The rapid trend to miniaturized equipment is placing ultra-compact size and dense mounting constraints on these components. This article explains the required characteristics of high frequency/low inductance discrete chip inductors. The new laminated chip inductor LL-F series developed by Toko is used as an example. Power semiconductor devices for the 1990s. B. JAYANT BAL1GA. Microelectronics Journal, 24, 31 (1993). This paper reviews recent progress in power semiconductor technology. The introduction of MOS processing to power semiconductor devices has led to the development of an array of chips that can control large amounts of energy with very little input power. This
World Abstracts on Microelectronics and Reliability in turn has led to the creation of smart power technology, which has far-reaching applications in commercial and industrial systems. Although, currently, power semiconductor chips are all made from silicon, recent analysis has indicated that other semiconductor materials, such as silicon carbide, have the potential for completely displacing it in the future. HIMOS: an attractive flash EEPROM cell for embedded memory applications. J. VAN HOUDT, G. GROESENEKENand H. E. MAES. Microeleetronics Journal, 24(3), 190 (1993). Flash EEPROMs (electrically eraseable programmable read-only memory) are the most recent products in the field of non-volatile memories. They were introduced 6 years ago to cope with the low market volumes of the expensive full featured EEPROMs. Many forecasts are stating that flash EEPROM will become in the near future one of the main technology drivers, to be used in both stand-alone memories and in embedded memory applications for ASICs.
Portable, cordless phone requirements give rise to chip monolithic microfiiters. KIYOHIROKOBAYASm. J E E (Japan), 72 (February 1993). Portable and cordless phones now are progressing toward a second stage of development and moving to new levels of technology. As are other electronic products, these phones are subject to trends for diminished size and weight and lowered power use. In striving to meet the needs of this burgeoning market, Murata Manufacturing Co., Ltd. developed two surface-mount device (SMD) micro-miniature band-pass filters. Adopting a monolithic structure, the filters operate in the 700 MHz to 3 GHz band, using multi-layer ceramic technology. Boundary walking test: an accelerated scan method for greater system reliability. JOHNC. CHAN. IEEE Transactions on Reliability, 41(4), 496 (1992). This paper deals with printed circuit board (PCB) interconnect test and reliability. The boundary scan test methodology proposed in the IEEE Standard 1149.1 is reviewed. Its limitation is critically analyzed. Based on this, a new technique is proposed to automate the interconnect wiring test, which is performed as part of the Power-On Self-Test. Essential to the idea is the use of Walking Sequence for test stimulus, and response compression by the Multiple Input Signature Registers (MISR). The salient feature is its simplicity of operation. Unlike the existing boundary-scan methodology, interconnects are tested via on-site test generation; faults are detected by comparing the content of the MISR with the anticipated response. Formal analysis shows that the new technique has a high test-coverage for the most common defects. As a result, PCB interconnect test can be accomplished as part of the Power-on Self-Test without external test fixtures.
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Optimizing force and geometry parameters in design of reduced insertion force connectors. IRENESAWCHYN and EDWARDS. SPROLES,JR IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 15(6), 1025 (1992). The need to design connectors with large numbers of I/Os is hindered by the associated rise in connector insertion force. It is possible to lower an undesirably high insertion force by reducing the normal force of the contacts, but this raises the question of whether reduced normal force connectors are sufficiently reliable for telecommunications applications. This paper examined nine test connector designs fabricated with 150-, 75-, and 35-g nominal contact normal force, and with 150-, 70-, and 35-mil radii at the point of contact with the pin. The connectors were exposed to conditions of thermal stress (thermal aging and thermal cycling), atmospheric corrosion, and extreme dust contamination coupled with thermal/humidity exposure. Precision resistance measurements were made at various times before, during, and after the stress exposures. All nine designs performed reliably under the test conditions used in this paper. The results suggest that connectors which are designed with contact geometries that provide higher local pressures are more effective in overcoming the interference of the dust contamination. Curiosities in choosing system components: a Bayes analysis. TELBAZ. IRONY and RICHARDE. BARLOW. IEEE Transactions on Reliability, 42(I), 128 (1993). The paper introduces a Bayes-decision problem in which incorrect interpretation of unobservable parameters leads to counter-intuitive choices. A system is to be built and we (the engineers in charge) must choose between two different brands of components with the same average chances of failure. Our results show that under certain conditions, if the system has two components, we should choose the brand about which we are more uncertain (the brand whose chance of failure has the largest standard deviation). Moreover, if the system has more than two components, our best choice might depend on the number of components in the system. These counter-intuitive choices, and the value of an informative test, are discussed and explained. One must be careful when defining unobservable parameters in modeling situations. Their role in the model ought to be well understood and the actual average utility to be maximized must be well defined. A review of modern power semiconductor devices. J. L. HUDGINS. Microelectronics Journal, 24, 41 (1993). A broad overview of modern discrete power semiconductor devices is given. The discussion centers around new device designs and modifications of Schottky rectifiers, insulated gate bipolar transistors (IGBTs), MOS-controlled thyristors (MCTs), gate
World Abstracts on Microelectronics and Reliability
2. RELIABILITY OF COMPONENTS, TUBES, TRANSISTORS AND ICs Rework of multi-chip modules: device removal. J. CHANG and C. SPOONER. Circuit World, 19(2), 13 (1993). This paper will review rework of multi-chip modules (MCMs). The issues of die removal from substrates (i.e. PCBs) with different chip-to-substrate interconnect technologies will be explored in detail. These different interconnect technologies (e.g., wire bonding, tape automated bonding and flip chip bonding) and die-attachment methods (e.g., eutectic and adhesive) have a strong influence on the MCM rework process and equipment selection. Traditional surface mount (SM) and current MCM rework technologies are also compared. It will be shown that traditional SMT rework processes and equipment are unable to solve the level of difficulty involved in fine-pitch MCM device removal--especially for systems which require heat removal through the substrate. A new type of fiber optic connector designed for military optical backplanes. R. J. PIMPINELLA. IEEE Transactions on Components, Hybrids and Manufacturing Technology, 15(6), 992 (1992). A new type of fiber optic connector designed to meet military stress requirements has been demonstrated. This reliable optical card-edge (ROC) connector is a multifiber backplane connector (four fibers, blind mate). The connector uses a unique expanded beam coupling design and micromachined silicon optical subassemblies to provide optimum coupling under high levels of shock and vibration. An additional feature of the ROC connector is its ability to self-seal or shield the optical fiber ends when unmated, protecting the fibers and internal mechanisms from environmental contamination and abusive handling. In this paper we discuss the design features of the ROC connector with respect to military stress requirements and present the prototype test results. Is boundary scan short on fault coverage? GORDOND. ROBINSON. Test and Measurement World, 71 (February 1993). By using a combination of test methods, you can maintain high fault coverage of shorts tests, even for boards with boundary-scan parts.
Experimental and analytical studies of encapsulated flip chip solder bumps on surface laminar circuit boards. J. LAU et al. Circuit World, 19(3), 18 (1993). The mechanical and thermal responses of encapsulated flip chip solder bumps on a surface laminar circuit (SLC) board have been determined in this study. The mechanical responses of the solder bumps and encapsulant have been obtained by shear, tension and torsion tests. The thermal stress and strain in the solder bumps and encapsulant have been determined by a non-linear finite element method and the thermal fatigue life of the corner solder bump is then estimated based on the calculated plastic strains,
Coffin-Manson law and isothermal fatigue data of solders. Also, an assembly process of the test boards is presented.
Design of precision capacitors for analog applications. STEPHEN A. ST. ONGE el al. IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 15(6), 1064 (1992). Precision capacitors are important elements in linear designs. One important source of error in the linearity of analog-to-digital converters (ADC's) is the variation of capacitance with applied voltage. This paper describes and analyzes two capacitors which are incorporated in a baseline BiCMOS technology without added process complexity. The first capacitor is formed between degenerately doped polysilicon and silicon. The second is formed between two degenerately doped polysilicon layers. In both structures, the insulator is a deposited or grown oxide. The sensitivity of the capacitor voltage coefficient to oxide thickness and surface dopant concentration is discussed theoretically and compared to measured data. The two capacitors are optimized to exhibit very low voltage coefficients. Fixed resistors serve to reduce equipment size. IWAO TSUCHIHASHI. JEE (Japan), 85 (1993). In 1991, the production of fixed resistors in Japan amounted to ¥138.9 billion or 124 billion resistors. The quantity of chip resistors accounted for more than 70% of all fixed resistor production. The size of the chip resistor was reduced from 3216 (3.2 × 1.6mm) to 2125 (2 × 1.25) or to the popular 1608 (1.6 x 0.8 mm) level. Some portable units use chip resistors of 1005 (1 × 0.5 mm) size. The chip resistor holds a lead over other surface-mounted devices (SMDs) for reduction in size. Ultra-miniature chip inductors for communications equipment down-sizing requirements. MITSUO SAKAKURA.JEE (Japan), 62 (May 1993). Chip fixed inductors are vital components for today's mobile communications and satellite receiver equipment. The rapid trend to miniaturized equipment is placing ultra-compact size and dense mounting constraints on these components. This article explains the required characteristics of high frequency/low inductance discrete chip inductors. The new laminated chip inductor LL-F series developed by Toko is used as an example. Power semiconductor devices for the 1990s. B. JAYANT BAL1GA. Microelectronics Journal, 24, 31 (1993). This paper reviews recent progress in power semiconductor technology. The introduction of MOS processing to power semiconductor devices has led to the development of an array of chips that can control large amounts of energy with very little input power. This
World Abstracts on Microelectronics and Reliability in turn has led to the creation of smart power technology, which has far-reaching applications in commercial and industrial systems. Although, currently, power semiconductor chips are all made from silicon, recent analysis has indicated that other semiconductor materials, such as silicon carbide, have the potential for completely displacing it in the future. HIMOS: an attractive flash EEPROM cell for embedded memory applications. J. VAN HOUDT, G. GROESENEKENand H. E. MAES. Microeleetronics Journal, 24(3), 190 (1993). Flash EEPROMs (electrically eraseable programmable read-only memory) are the most recent products in the field of non-volatile memories. They were introduced 6 years ago to cope with the low market volumes of the expensive full featured EEPROMs. Many forecasts are stating that flash EEPROM will become in the near future one of the main technology drivers, to be used in both stand-alone memories and in embedded memory applications for ASICs.
Portable, cordless phone requirements give rise to chip monolithic microfiiters. KIYOHIROKOBAYASm. J E E (Japan), 72 (February 1993). Portable and cordless phones now are progressing toward a second stage of development and moving to new levels of technology. As are other electronic products, these phones are subject to trends for diminished size and weight and lowered power use. In striving to meet the needs of this burgeoning market, Murata Manufacturing Co., Ltd. developed two surface-mount device (SMD) micro-miniature band-pass filters. Adopting a monolithic structure, the filters operate in the 700 MHz to 3 GHz band, using multi-layer ceramic technology. Boundary walking test: an accelerated scan method for greater system reliability. JOHNC. CHAN. IEEE Transactions on Reliability, 41(4), 496 (1992). This paper deals with printed circuit board (PCB) interconnect test and reliability. The boundary scan test methodology proposed in the IEEE Standard 1149.1 is reviewed. Its limitation is critically analyzed. Based on this, a new technique is proposed to automate the interconnect wiring test, which is performed as part of the Power-On Self-Test. Essential to the idea is the use of Walking Sequence for test stimulus, and response compression by the Multiple Input Signature Registers (MISR). The salient feature is its simplicity of operation. Unlike the existing boundary-scan methodology, interconnects are tested via on-site test generation; faults are detected by comparing the content of the MISR with the anticipated response. Formal analysis shows that the new technique has a high test-coverage for the most common defects. As a result, PCB interconnect test can be accomplished as part of the Power-on Self-Test without external test fixtures.
1411
Optimizing force and geometry parameters in design of reduced insertion force connectors. IRENESAWCHYN and EDWARDS. SPROLES,JR IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 15(6), 1025 (1992). The need to design connectors with large numbers of I/Os is hindered by the associated rise in connector insertion force. It is possible to lower an undesirably high insertion force by reducing the normal force of the contacts, but this raises the question of whether reduced normal force connectors are sufficiently reliable for telecommunications applications. This paper examined nine test connector designs fabricated with 150-, 75-, and 35-g nominal contact normal force, and with 150-, 70-, and 35-mil radii at the point of contact with the pin. The connectors were exposed to conditions of thermal stress (thermal aging and thermal cycling), atmospheric corrosion, and extreme dust contamination coupled with thermal/humidity exposure. Precision resistance measurements were made at various times before, during, and after the stress exposures. All nine designs performed reliably under the test conditions used in this paper. The results suggest that connectors which are designed with contact geometries that provide higher local pressures are more effective in overcoming the interference of the dust contamination. Curiosities in choosing system components: a Bayes analysis. TELBAZ. IRONY and RICHARDE. BARLOW. IEEE Transactions on Reliability, 42(I), 128 (1993). The paper introduces a Bayes-decision problem in which incorrect interpretation of unobservable parameters leads to counter-intuitive choices. A system is to be built and we (the engineers in charge) must choose between two different brands of components with the same average chances of failure. Our results show that under certain conditions, if the system has two components, we should choose the brand about which we are more uncertain (the brand whose chance of failure has the largest standard deviation). Moreover, if the system has more than two components, our best choice might depend on the number of components in the system. These counter-intuitive choices, and the value of an informative test, are discussed and explained. One must be careful when defining unobservable parameters in modeling situations. Their role in the model ought to be well understood and the actual average utility to be maximized must be well defined. A review of modern power semiconductor devices. J. L. HUDGINS. Microelectronics Journal, 24, 41 (1993). A broad overview of modern discrete power semiconductor devices is given. The discussion centers around new device designs and modifications of Schottky rectifiers, insulated gate bipolar transistors (IGBTs), MOS-controlled thyristors (MCTs), gate