Presence of capacitive memory in indium doped TiO2 alloy thin film

Presence of capacitive memory in indium doped TiO2 alloy thin film

Journal of Alloys and Compounds 654 (2016) 529e533 Contents lists available at ScienceDirect Journal of Alloys and Compounds journal homepage: http:...

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Journal of Alloys and Compounds 654 (2016) 529e533

Contents lists available at ScienceDirect

Journal of Alloys and Compounds journal homepage: http://www.elsevier.com/locate/jalcom

Presence of capacitive memory in indium doped TiO2 alloy thin film Mitra Barun Sarkar a, Aniruddha Mondal b, *, Bijit Choudhuri a a b

National Institute of Technology Agartala, Department of Electronics and Communication Engineering, Jirania, Tripura (West), 799055, India National Institute of Technology Durgapur, Department of Physics, Durgapur, West Bengal, 713209, India

a r t i c l e i n f o

a b s t r a c t

Article history: Received 20 July 2015 Received in revised form 14 September 2015 Accepted 15 September 2015 Available online 16 September 2015

A capacitive memory effect has been reported for Indium (In) metal doped titanium dioxide (TiO2) alloy thin film (TF). Two distinct structures of Au/TiO2 TF/n-Si and Au/In doped TiO2 alloy TF/n-Si were fabricated by e-beam deposition technique. An instantaneous source of In was used to dope the TiO2 TF on the Si substrate. The frequency dependent capacitance (C) -voltage (V) and conductance (G) -voltage (V) characteristics were measured to analyze charge trapping behavior of both the devices. The study revealed that the frequency dispersion in the accumulation region decreases more for the undoped device (~3 nF) compared to doped alloy (~6.12 nF) device. The maximum memory window of 4.74 V was obtained from the In doped alloy device as compared to the undoped TF device with 1.16 V under sweeping top gate biasing of ±8 V. Large hysteresis in the depletion region was obtained for In doped TiO2 alloy TF device. © 2015 Elsevier B.V. All rights reserved.

Keywords: Thin films Vapor deposition Diffusion Alloy layers Memory devices

1. Introduction During last two decades, exercise of high K dielectric material has drawn enormous attention to enhance the capacitive memory effect [1]. Package density of memory devices has also been increased to synchronize with the pace of modern day's electronic requirement. The capacitive memory effect has been detected in many materials such as oxides [2], semiconductors [3], organic materials [4], etc. Presently, the dynamic random access memory (DRAM) exhibited high non-volatile nature [5,6], fast recognization [7] and reliability, those play a crucial role in computer operation. Since the memory capacity and performance of DRAM momentously affect the working speed of a computer, much attention has been paid to optimize DRAM structure. In order to ameliorate the charge storing capacity and continue the down-scale process of DRAMs, novel materials have been studied and implemented. There are plenty of materials with which DRAMs are fabricated, those demonstrate the capacitive memory effect. Intense research work to explore the use of miniature and low dimensional device resulted in the use of metal oxides such as TiO2 [8], NiO [9], Ta2O5 [10], CuO [11], Al2O3 [12] etc. as promising materials for the memory devices. Recently study on Titanium dioxide (TiO2) has immensely increased because of its novel applications in various

* Corresponding author. E-mail address: [email protected] (A. Mondal). http://dx.doi.org/10.1016/j.jallcom.2015.09.129 0925-8388/© 2015 Elsevier B.V. All rights reserved.

fields of science, technology and research [13]. It has already been established that TiO2 can be used as an ideal photocatalytic agent for environmental remediation processes [14], white pigment utilization [15], solar cells, gas sensing [16] and flexible electronics [17] because it shows a remarkable assortment of physical and chemical properties with high stability. Now a days, TiO2 layers are being examined extensively as one of the promising high K dielectric for high density DRAM applications [18]. Different strategies such as surface modification, metals [19e21] or non-metal ion doping [22e24], generation of an oxygen vacancy, combination with other semiconductors, etc., have been widely implemented to prepare TiO2 as a promising material for enhancing charge trapping inside the oxide-substrate interface. But there have been no report showing the enhancing capacitive memory effect for TiO2 doped with Indium (In) metal. In this paper, we have investigated the charge storing behavior of the undoped TiO2 TF device and In doped TiO2 alloy TF device in connection to the role of interface trap state density (Dit). Two distinct device structures of Au/TiO2 TF/n-Si and Au/In doped TiO2 alloy TF/n-Si were fabricated by physical vapor deposition technique. A comparative study of capacitance (C) -voltage (V) and conductance (G) -voltage (V) characteristics in open air room temperature condition as a function of gate bias voltage with varying frequency have been presented for analyzing charge trapping behavior of both the devices. Enhanced hysteresis in the depletion region and memory window have also been detected for In doped TiO2 TF alloy devices compared to undoped TiO2 TF

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devices. A capacitive memory effect has been reported for In metal doped TiO2 alloy TF in this paper. 2. Experiments An easy doping method has been done through a physical vapor technique followed by annealing method to introduce In dopant into the thin layer of TiO2 on n-type Si < 100 > substrate (35 U-cm). The technique of doping of In into TiO2 TF was described elsewhere in details [25]. Silicon (Si) substrates were cleaned through standard RCA-I cleaning method before fabrication processing. The entire deposition process was done at a base pressure of ~2  105 mbar inside the e-beam evaporator (Hind High Vacuum Co. (p) Ltd., 15F6) with a constant deposition rate 1.2 Å/s under constant monitoring by a quartz crystal. The TiO2 TF of 200 nm was deposited from 99.999% pure TiO2 (MTI, USA) source on n-type Si substrate and on the surface of the TiO2 TF, a 5 nm In metal film was developed using 99.999% pure In (MTI, USA). Then annealing was done on the samples in open air condition at 950  C for 1 h inside the tube furnace (GSL-1700X, MTI, USA) using even heating and cooling ramp of 4  C/min to diffuse the In into the TiO2. Aluminum mask hole of diameter 1.5 mm has been used to make Gold (Au) top contact through evaporation technique on TiO2 layers. The schematic in Fig. 1 represents different steps of fabrication of TiO2 TF based devices. The samples were then electronically characterized. The frequency dependent capacitances as a function of gate bias were measured by Agilent (E4980A) LCR meter using Au top contact for both of the In doped alloy TF and undoped TiO2 TF devices. Conductance (G) e voltage (V) measurement was also performed to explore the various charges trapping related behavior using aforementioned instrument. 3. Results and discussions 3.1. Capacitance (C) e voltage (V) characterization The electrical performance of the TiO2 TF based device deposited from high K dielectric material depends upon its crystal structure and trap states available in the TF. The deposited structures of undoped annealed TiO2 TF as well as In doped TiO2 TF have been found in rutile phase, which was reported earlier by the authors [25]. Therefore the function of defect states has been investigated by observing capacitance (C) e voltage (V) and conductance (G) e voltage (V) characteristics of both doped and undoped TiO2 TF devices. The entire experiment was carried out over a gate bias,

ranging from þ15 V to 15 V with distinct high frequency values (200 KHz, 500 KHz, 1 MHz and 2 MHz) under room temperature condition. The connecting leads of the LCR meter (Agilent E4980-A) were used across the top Au (Gold) contact and bottom contact with the substrate to measure the junction capacitance of both undoped Au/TiO2 TF/n-Si and Au/In doped TiO2 alloy TF/n-Si device structures. Fig. 2 (a) and (b) show the CeV characteristics at different frequencies having three distinct regions, namely accumulation, depletion, and inversion region for the undoped TiO2 TF device and In doped TiO2 alloy TF device respectively. For both the devices the changes in the inversion region are negligible, whereas measured capacitance values have sharply decreased from ~ (9.59 nFe6.59 nF) and ~ (11.3 nFe5.18 nF) for undoped device and In doped alloy device respectively with an increase in frequency value from 200 KHz to 2 MHz. These frequency dependent variations in strong accumulation capacitance value attributed to the effect of series resistance, oxide charges present in the high K dielectric material TF and at the interface of the substrate and dielectric TF [26]. It has also been observed that the frequency dispersion values of undoped device are low (~3 nF) compared to In doped device ~6.12 nF. The frequency dispersion in the accumulation region decreases in the undoped device compared to the In doped device may be due the presence of inhomogeneous surface layers [26]. In our case, the inhomogeneous layers of InxTiyO2 and TieOeIn were formed due to the bulk diffusion of In into the TiO2 TF as an effect of annealing [25] and shows the consonance in the CeV characteristics. These InxTiyO2 and TieOeIn layers act as series capacitor with TiO2 dielectric. A small hump was observed in case of doped TiO2 TF device (Fig. 2 (b)) at the transition boundary between accumulation and depletion region, which indicated a poor interface quality and drift in mobile charges [27]. But in the case of undoped TiO2 TF, a flat transition of the capacitance value has been obtained from accumulation to depletion region. The above observation also indicates the formation of InxTiyO2 and TieOeIn interface layers in the In doped TiO2 TF sample.

3.2. Conductance (G)- voltage (V) measurement An increase in the conductance value with frequency were observed in both undoped (Fig. 3(a)) and In doped (Fig. 3(b)) devices. The indium doped alloy device shows large conductance value ~9.42 mS at þ10 V compared to ~3.99 mS for the undoped device at the same voltage under 2 MHz frequency response. In case of metal-oxide-semiconductor devices the oxide capacitance acts in series with the interface trap resistance-capacitance [28], which

Fig. 1. Fabrication process steps of Indium doped and undoped TiO2 TF based devices.

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Fig. 2. Frequency dependent CeV characteristics for (a) undoped TiO2 TF and (b) In doped TiO2 alloy TF devices.

Fig. 3. Conductance (G) -voltage (V) characteristics of (a) undoped TiO2 TF devices and (b) In doped TiO2 alloy TF devices at different high frequencies.

increases the conductance value with applied frequency. Therefore, a large conductance value in Indium doped TiO2 TF alloy device was observed due to the presence of huge numbers of trap states as compared to the undoped TiO2 TF device as reported by the authors in the case of TiO2 nanowires [29]. It is already reported that the defects in TiO2 TF get reduced due to the open air annealing at around 950 C [30]. We have annealed the undoped TiO2 TF at 950 C in open air condition, which basically removes most of the defects in TiO2 film. The conductance (C) -Voltage (V) characteristic at all frequencies for undoped TiO2 TF shows normal behavior, whereas the same characteristic for Indium doped TiO2 TF reveals a

small peak and sudden increase in conductance value. The fact also supported the presence of more trap states due to inhomogeneous alloy layer formation in the doped TiO2 TF as compared to undoped TiO2 TF. 3.3. Memory windows The memory windows of both the devices were calculated from CeV hysteresis. To observe the charge retention phenomena into the devices, separate CeV analyses have been carried out at 1 MHz in room temperature with sweeping voltage from ±2 to ±8 V.

Fig. 4. CeV curves at 1 MHz under a sweeping top electrode voltage from ±2 to ±8 V for (a)Undoped TiO2 TF devices and (b) In doped TiO2 alloy device.

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states in inhomogeneous alloy layer in the dielectric material of In doped TiO2 alloy device. The maximum memory window of 4.74 V was obtained for the In doped TiO2 TF device as compared to undoped 1.16 V of TiO2 TF under sweeping top gate biasing voltage of ±8 V due to charge trapping in the trap states, which was due to modulation of TiO2 TF crystal structure as bulk In diffused into the TiO2 TF through high temperature annealing. Therefore, movement of charge carriers within the lattice structure was restricted during device operation and carrier mobility was affected. Finally large hysteresis in the depletion region and the presence of high memory windows manifested that the In doped TiO2 alloy TF device can be used as an efficient charge trapping capacitive memory device. Acknowledgment

Fig. 5. Memory windows of the devices.

Fig. 4 shows the formation of hysteresis in CeV characteristics under sweeping of the gate bias for In doped (Fig. 4. (a)) and undoped TiO2 TF (Fig. 4. (b)) devices. Further, it has also been observed that large amount of charges were stored in the depletion region of In doped TiO2 alloy TF compared to undoped TiO2 TF. Under forward sweeping, the carriers are trapped into the huge interface trap states present in Indium doped alloy TiO2 TF and retained for a longer voltage range in backward sweeping. As a result, large charge storage has been obtained in TiO2 alloy TF. Also, the capacitance increases with increasing sweeping voltages and frequency due to recombination and generation from the interface states [31]. Fig. 5 exhibits the corresponding memory windows for both devices. Memory windows of DV z 0.29 V for TiO2 TF device and DV z 1.61 V for the doped TiO2 alloy device have been measured under a sweeping top gate voltage (VG) from forward þ2 V to 2 V, and then backward 2 V to þ2 V without disconnecting the leads. With an increase in gate bias sweeping voltage, memory window has also increased. A maximal memory window in the CeV characteristic was observed about 4.74 V and 1.64 V under applied gate voltage of ±8 V for In doped alloy and undoped devices respectively. Therefore, a wide depletion region was created in In doped device during voltage sweeping, which may be due to the carrier holding into the trap states. The same phenomena of charge trapping and the creation of memory window due to the presence of artificial interface defects by Ag nanoparticles into TiO2 TF have already been reported by Mondal et al. [32]. So, doping of Indium into TiO2 TF also opens up a new technique of fabrication of capacitive memory device based on the charge trapping at the interface defects. 4. Conclusion The frequency dependent CeV characteristics reveal that the frequency dispersion value of ~3 nF for undoped device is less compared to ~6.12 nF for In doped device. The frequency dispersion in the accumulation region decreases more in the TiO2 TF device compared to In doped alloy device due to the formation of the inhomogeneous surface layers (InxTiyO2 alloy and TieOeIn). The capacitances of the TiO2 TF and In doped alloy TiO2 TF devices were measured with different gate biasing under the variation of frequency from 200 KHz to that of the 2 MHz. The frequency dependent conductance dispersion was measured for both devices. The maximum conductance value ~9.42 mS for the doped TiO2 alloy device was measured compared to ~3.99 mS at þ10 V for undoped devices under 2 MHz frequency response due to presence of trap

The authors are grateful to Department of Science and Technology, Govt. Of India SR/S3/EECE/0142/2012 dated 10.12.2012 and NIT Durgapur and NIT Agartala for financial support. References [1] K. Yim, Y. Yong, J. Lee, K. Lee, H. Nahm, J. Yoo, C. Lee, C. Hwang, S. Han, Novel high-Κ dielectrics for next-generation electronic devices screened by automated Ab initio calculations, Nature 7 (2015) 1e7. €hlich, TiO2 -based structures for nanoscale memory applications, Mater. [2] K. Fro Sci. Semicond. Process 16 (2013) 1186e1195. [3] R. Meyer, M. Miao, J. Wu, C. Chevallier, Resistive and capacitive memory effects in oxide insulator/oxide conductor hetero-structures, Bull. Am. Phys. Soc. 58 (2013) 1. [4] Y. Yang, J. Ouyang, L. Ma, R. Tseng, C. Chu, Electrical switching and bistability in organic/polymeric thin films and memory devices, Adv. Funct. Mater. 16 (2006) 1001e1014. [5] K. Park, S. Cristoloveanu, M. Bawedin, Y. Bae, K. Na, J. Lee, Double-gate 1TDRAM cell using nonvolatile memory function for improved performance, Solid-State Electron 59 (2011) 39e43. [6] F. Horiguchi, Advanced memory concepts for dram and nonvolatile memories, Solid-State Electron 50 (2006) 545e550. [7] S. Ghosh, Modeling of retention time for high-speed embedded dynamic random access memories, IEEE T Circuits. Syst. 61 (2014) 2596e2604. [8] I. Salaoru, Q. Li, A. Khiat, T. Prodromakis, Coexistence of memory resistance and memory capacitance in TiO2 solid-state devices, Nanoscale Res. Lett. 4 (2014), 552-1e552-7. [9] G. Ma, Xi Tang, Z. Zhong, H. Zhang, H. Su, Effect of Ni3þ concentration on the resistive switching behaviors of NiO memory device, Microelectron. Eng. 108 (2013) 8e10. [10] J. Chung, Y. Cheol Bae, A. Lee, G. Baek, M. Lee, H. Yoon, H. Park, J. Hong, Enhancement of memory windows in Pt/Ta2o5 e X/Ta bipolar resistive switches via a graphene oxide insertion layer, Thin Solid Films 587 (2015) 57e60. [11] C. Tu, C. Chang, C. Wang, H. Fang, M. Huang, Y. Li, H. Chang, C. Lu, Y. Chen, R. Wang, Y. Tzeng, C. Liu, Resistive memory devices with high switching endurance through single filaments in bi-crystal CuO nanowires, J. Alloys Comp. 615 (2014) 754e760. [12] E. Gusev, E. Cartier, D. Buchanan, M. Gribelyuk, M. Copel, H. Okorn-Schmidt, C. D'Emic, Ultrathin high-K metal oxides on silicon: processing, characterization and integration issues, Microelectron. Eng. 59 (2001) 341e349. [13] K. Hashimoto, H. Irie, A. Fujishima, TiO2 photocatalysis: a historical overview and future prospects, Jpn. J. Appl. Phys. 44 (2005) 8269e8285. [14] Y. Cong, J. Zhang, F. Chen, M. Anpo, D. He, Preparation, photocatalytic activity, and mechanism of nano-TiO2 co-doped with nitrogen and iron (III), J. Phys. Chem. C 111 (2007) 10618e10623. [15] L. Mcneil, R. French, Multiple scattering from rutile TiO2 particles, Acta Mater. 48 (2000) 4571e4576. [16] A. Ruiz, A. Cornet, J.R. Morante, Performances of LaeTiO2 nanoparticles AS gas sensing material, Sens. Actuators B 7 (111) (2005) 7e12. [17] A. Maliakal, H. Katz, P. Cotts, S. Subramoney, P. Mirau, Inorganic oxide core, polymer shell nanocomposite as a high K gate dielectric for flexible electronics applications, J. Am. Chem. Soc. 127 (2005) 14655e14662. [18] D. Rathee, S. Arya, M. Kumar, CapacitanceeVoltage Analysis Of A High-K Dielectric On Silicon, J. Semicond. 33 (2012), 22001-1e4. [19] E. Wang, W. Yang, Y. Cao, Unique surface chemical species on indium doped TiO2 and their effect on the visible light photocatalytic activity, J. Phys. Chem. C 113 (2009) 20912e20917. [20] R. Bechstein, M. Kitta, J. Schütte, H. Onishi, A. Kühnle, The effects of antimonydoping on the surface structure of rutile TiO2 (110), Nanotechnol 20 (2009), 264003-1e264003-7. [21] W. Choi, A. Termin, M.R. Hoffmann, Role of metal-ion dopants in quantumsized TiO2ecorrelation between photoreactivity and charge-carrier

M.B. Sarkar et al. / Journal of Alloys and Compounds 654 (2016) 529e533 recombination dynamics, J. Phys. Chem. 98 (1994) 13669e13679. [22] T. Ohno, T. Mitsui, M. Matsumura, Photocatalytic activity of S-doped TiO2 photocatalyst under visible light, Chem. Lett. 32 (4) (2003) 364e365. [23] X. Qiu, Y. Zhao, C. Burda, Synthesis and characterization of nitrogen-doped group IVB visible-light-photoactive metal oxide nanoparticles, Adv. Mater 19 (2007) 3995e3999. [24] J.C. Yu, L. Zhang, Z. Zheng, J. Zhao, Synthesis and characterization of phosphated mesoporous titanium dioxide with high photocatalytic activity, Chem. Mater. 15 (2003) 2280e2286. [25] M. Sarkar, A. Mondal, B. Choudhuri, B.K. Mahajan, S. Chakrabartty, C. Ngangbam, Enlarged broadband photodetection using Indium doped TiO2 alloy thin film, J. Alloys Compd. 615 (2014) 440e445. [26] O. Pakma, N. Serin, T. Serin, S. Altındal, The influence of series resistance and interface states on intersecting behavior of IeV characteristics of Al/TiO2/p-Si (MIS) structures at low temperatures, Semicond. Sci. Technol. 23 (2008) 105014. [27] D. Schroder, Electrical characterization of semiconductor materials and devices, microelectronics processing: inorganic materials characterization, ACS

533

Symp. Ser. 295 (1986) 18e33. [28] K. Shubham, R. Khan, Electrical characterization of TiO2 insulator based Pd/ TiO2/Si MIS structure deposited by solegel process, J. Nano Electron. Phys. 5 (2013), 01021e010215. [29] A. Mondal, J. Dhar, P. Chinnamuthu, N. Singh, K. Chattopadhyay, S. Das, S. Das, A. Bhattacharyya, Electrical properties of vertically oriented TiO2 nanowire arrays synthesized by glancing angle deposition technique electron, Mater. Lett. 9 (2013) 213e217. [30] P. Chinnamuthu, A. Mondal, N. Singh, J. Dhar, S. Das, K. Chattopadhyay, Structural and optical properties of glancing angle deposited TiO2 nanowires array, J. Nanosci. Nanotechnol. 12 (2012) 1e4. [31] M. Theodoropoulou, P. Karahaliou, S. Georga, C. Krontiras, M.N. Pisanias, M. Kokonou, A. Nassiopoulou, Interface traps density of anodic porous alumina films of different thicknesses on Si, J. Phys. Conf. Ser. 10 (2005) 222e225. [32] A. Mondal, A. Ganguly, A. Das, B. Choudhuri, R.K. Yadav, The Ag nanoparticles/ TiO2 thin film device for enhanced photoconduction and role of traps, Plasmonics 10 (2015) 667e673.