- Email: [email protected]
Process and device characteristics of self-assembled metal nano-crystal EEPROM
Superlattices and Microstructures, Vol. 28, No. 5/6, 2000 doi:10.1006/spmi.2000.0939 Available online at http://www.idealibrary.com on
Process and device characteristics of self-assembled metal nano-crystal EEPROM Z ENGTAO L IU , M YONGSEOB K IM , V ENKAT NARAYANAN , E DWIN C. K AN† School of Electrical and Computer Engineering, Cornell University, Ithaca, NY 14853, U.S.A. (Received 26 July 2000)
Metal nanocrystals self-assembled on gate tunneling oxide can be used to replace the conventional Si/Ge nanocrystals as the floating gate in EEPROM cells. We have demonstrated the successful use of Au and W with their respective process dependence and self-assembly characteristics. The new material options can potentially enhance the applicability and functionality of the nanocrystal EEPROM device. Implications on process integration, in particular the control oxide growth and overall thermal budget, are examined by microscopy, gate current injection and channel mobility monitoring. Charging by hot-carrier injection and control gate tunneling have both been observed by shifts in I –V characteristics. The electrostatic behavior of metal nanocrystals is similar to that of Si nanocrystals in terms of the asymmetrical threshold voltage on source–drain reversal after hot-carrier injection and the Coulomb blockade effects. The electrodynamic behavior is expected to be quite different due to the density of states, but further study is required for quantitative analysis. c 2000 Academic Press
Key words: nanocrystal memories, process integration, carrier injection and tunneling.
1. Introduction Self-assembled nanocrystals embedded in insulators can be used to replace the conventional floating gate in the EEPROM (electrically erasable programmable read-only memory) devices. The nonvolatile charge retention time can be significantly improved due to the Coulomb blockade effect [1], the reduction of charge leakage from weak spots in tunneling oxide [2], and the floating-gate strain release from self-assembly [3]. In addition, since the nanocrystals are more electrically coupled to the channel carriers than to each other, novel device structures such as multi-bit storage, interconnect fault-tolerant quad routers, and electronic synapse transistors [4, 5] can be configured from structural asymmetry. Conventionally the nanocrystals are formed by self assembly of wetting layers or implant-precipitation of Si [1, 2] or Ge [6] mostly due to the anticipated process compatibility. In this paper, we will first present the self-assembly behavior of Au and W on oxide in terms of initial-layer thickness and annealing temperature dependence. We will then compare the process and device characteristics of metal (Au and W) nanocrystal EEPROM with those of Si nanocrystals. † E-mail: [email protected]
0749–6036/00/110393 + 07
$35.00/0
c 2000 Academic Press
394
Superlattices and Microstructures, Vol. 28, No. 5/6, 2000
Before annealing
After annealing
200nm
A
100nm
B
100nm
C
100nm
D
Fig. 1. Dependence of Au nanocrystal self assembly on initial-layer thickness. The annealing is performed by 550 ◦ C RTA for 2 min. A, initial layer of 10 nm; B, initial layer of 5 nm; C, initial layer of 3 nm; D, initial layer of 2 nm.
2. Process characteristics Starting from a clean and atomically smooth Si (100) surface, we grew 5–8 nm gate oxide by lowtemperature dry oxidation. Then a wetting layer of metal (Au and W) was evaporated or sputtered, followed by a RTA (rapid thermal annealing) process with short temperature spikes (within 20 s) close to the bulk eutectic temperature for nanocrystal formation. Note that the nanocrystals may have a very different eutectic temperature due to the size effect—the bulk value is only used as a reference. Transport of metal atoms is limited by temperature-dependent surface mobility and growth is limited by activation of reaction/nucleation sites [7]. Due to length constraints, we will present here only the two most interesting growth phenomena observed in metal nanocrystal formation. In Fig. 1, the dependence of Au nanocrystal self-assembly on initial wetting layer thickness is demonstrated. When the wetting layer is thicker than 10 nm, an irregular island pattern is formed. By reducing the initial layer thickness, dots with rather uniform size and distribution are obtained. At 2 nm initial thickness, start of dot formation can be observed even without annealing. However, we were not able to finish the
Superlattices and Microstructures, Vol. 28, No. 5/6, 2000
395
After annealing
2 µm
A
500nm
C
2 µm
B
200nm
D
Fig. 2. Dependence of W nanocrystal self-assembly on annealing temperature profiles: A, 1000 ◦ C RTA for 2 min. Long spikes of W were formed with length of about 4 µm and width of 200 nm. Anisotropic nucleation is sensitive to the thermal profiles. B, 1050 ◦ C RTA for 2 min. C, 1100 ◦ C RTA for 2 min. Dot formation starts when more surface sites are available for nucleation. D, 1150 ◦ C RTA for 2 min. The size distribution is almost bimodal, with a group at size of 40 nm, and the other at 10 nm.
gate stack process to ascertain that the dots are electrically separated due to following thermal processes. In Fig. 2, the dependence of W nanocrystal self-assembly on annealing temperature profiles is shown. Configuration of W nanocrystals after RTA clearly shows that W nanocrystal growth is nucleation-site limited. At low annealing temperatures, distance between activated sites is much larger than the wetting layer thickness. The returned nucleation sites have slightly different activation energy for different orientation and curvature, which causes anisotropic needle growth. The W nanocrystal aspect ratio for 1000 ◦ C RTA is as high as 20, while it reduces to about 7 for 1050 ◦ C RTA. At higher annealing temperatures when nucleation site spacing is similar to or smaller than the wetting layer thickness, dot formation is obtained. The driving forces for atomic motion in Au self-assembly come from the gradient of the total energy (surface and elastic) and long-range forces [8], in particular electrical double layers [9] which provide the minimal dot separation. The electrical double-layer force comes from repulsion between the substrate depleted dopant charges. W nanocrystal formation has a much higher RTA temperature where intrinsic carriers effectively screen the depletion charges in bulk Si, and the nanocrystal distribution is more irregular. To avoid contamination after the formation of metal nanocrystals, low-temperature PECVD (plasma-enhanced
396
Superlattices and Microstructures, Vol. 28, No. 5/6, 2000
Silicide Control Gate
Possible Nano -pocket Control PECVD Oxide Au Nanocrystals Tunneling Oxide Bulk Si
100 nm
Fig. 3. Gate-stack cross-section of Au-nanocrystal EEPROM devices. The tunneling oxide has a thickness around 8 nm. Selective PECVD oxide growth may cause nano-pockets around the nanocrystals.
chemical vapor deposition) oxide at substrate temperature not exceeding 300 ◦ C was used for control oxide growth. By tuning the plasma energy, a wide range of selective growth can be achieved due to different affinity between metal and SiO2 . In extreme cases which are not appropriate for EEPROM but are very useful features for other applications, large nano-pockets containing the metal nanocrystal can be formed. For some PECVD conditions, we can observe a slow and small drift of subthreshold drain current in EEPROM devices (at times around a few seconds) under low VGS (0–2 V) and VDS (0.1 V) after charging the nanocrystals. This phenomenon seems to be only explainable by the charged nanocrystal adjusting its position in the nano-pocket, since other mechanisms such as oxide charge drift and interface traps have either dramatically different time constants or are inconsistent with the shift direction. After source/drain implants, the control gate and source/drain contacts are deposited with co-sputtered W silicides for electrical contacts. A sample cross-section of the gate stack in a large MOS capacitor area is shown in Fig. 3. In summary, different configurational forces, asymmetrical nucleation and selective deposition are the main processing differences from Si nanocrystals as floating gate materials.
3. Device characteristics Metal nanocrystal EEPROM devices have some similar characteristics to the Si nanocrystal ones. For comparison, a compatible process is used to fabricate Si nanocrystal devices, replacing the Au evaporation step with LPCVD (low-pressure chemical vapor deposition) growth of Si wetting layers followed by RTA. The process flow is similar to our previous runs [3]. The silicon nanocrystal EEPROM characteristics are shown in Figs 4 and 5, and the parallel subthreshold IV curve shift can be observed after charging and erasing from control gate tunneling. Retention time is much longer than 60 h, where additional accelerated stress tests are required for quantitative estimation. The charging time is quite small as a hysteresis IV loop can be observed even for a fast VGS sweep. The contact resistance to source/drain and poly-gate is large for this run, which limits our measurement in above-threshold saturation region. The size of the Si nanocrystal is probably too large to show the threshold voltage plateaus at room temperature [1]. However, Si nanocrystals are definitely formed at the floating-gate layer as seen from observation of asymmetrical IV on source–drain
Superlattices and Microstructures, Vol. 28, No. 5/6, 2000
397
1.E-07
VDS
1.E-08
VGS (A) ID
1.E-09
1.E-10
Initial curve 1.E-11
After -15V control gate charging 60 hours later After 15V control gate erasing
1.E-12 -2
-1.5
-1
-0.5
VGS (V)
Fig. 4. Channel currents with control gate bias sweep in low VDS (50 mV) for Si-nanocrystal EEPROM cell with W/L = 1.8 µm/1.2 µm. Threshold voltage shift caused by nonvolatile charges in nanocrystals can be maintained for much longer than days (stress tests to be done). Symbols used: initial (diamonds); charging from control gate tunneling (circles); charge retention after 60 h (triangles); erase from control gate tunneling (crosses). Notice that the extraction of threshold voltage shift is done at a gate bias much lower than the writing and erasing voltage. 1.E-05
1.E-06
1.E-07
(A) ID
1.E-08
GIDL region
1.E-09
1.E-10
1.E-11
sweep upward sweep downward
1.E-12
1.E-13 -20
-15
-10
-5
0
5
10
15
20
25
VGS (V)
Fig. 5. Typical IV hysteresis for the nanocrystal EEPROM devices above with a fast sweep of VGS . The gate-induced drain leakage (GIDL) at negative control gate bias can be clearly observed. Symbols used: VGS sweep upward (circles) immediately followed by sweeping downward (squares). This figure also demonstrates the property of continuous charging of the nanocrystal EEPROM devices from Fig. 4. The position of the threshold voltage hysteresis will continue to shift due to the large gate bias during the sweep.
reversal similar to Fig. 6. In Fig. 5, a small Esaki diode signature [10] can be observed in the gate-induceddrain-leakage (GIDL) region. Typical Au nanocrystal EEPROM characteristics are shown in Figs 6 and 7, where many similar electrostatic effects can be observed. Effective MOS interface mobility (around 150–300 cm2 V−1 s−1 with substrate doping about 1017 cm−3 ) and high-frequency MOS CV are frequently extracted to ascertain no metal contamination in bulk Si. Presently we have observed several important differences of the metal nanocrystal EEPROM devices from the Si nanocrystal ones. First, close to the conventional GIDL region, the IV curves
398
Superlattices and Microstructures, Vol. 28, No. 5/6, 2000 3.5E-05 Initial Curve (Source end) 3.0E-05 Initial Curve (Drain end) 10 sec after 4-7V Vg sweep at Vds=5V (Source end) 2.5E-05 10 sec after 4-7V Vg sweep at Vds=5V (Drain end)
(A) ID
2.0E-05
1.5E-05
1.0E-05
5.0E-06
0.0E+00 0
0.5
1
1.5
2
2.5
3
VGS (V)
Fig. 6. Above-threshold channel currents for the Au-nanocrystal EEPROM device at high VDS (5 V) with W/L = 1.8 µm/1.2 µm. Symbols used: initial measurement with source grounded and drain at 5 V(diamonds) and drain grounded and source at 5 V (squares); after VGS sweeping from 4 to 7 V for 10 s with source grounded and drain at 5 V (crosses) and with drain grounded and source at 5 V (circles). Si-nanocrystal EEPROM devices have similar behavior.
1.E-06
W/L=3/9, V DS =0.1V
1.E-07
I D(A)
1.E-08
1.E-09
1.E-10
1.E-11 0
0.5
1
1.5
2
2.5
3
3.5
4
VGS (V)
Fig. 7. Channel currents for Au-nanocrystal EEPROM the device in low VDS (0.1 V) with W/L = 5.4 µm/3.6 µm. Symbols used: initial (triangles); first-time charging by control gate tunneling (circles); after continuous VGS sweeping for 20 min (crosses). Note that the drain leakage current in the subthreshold region is much larger after gate-current stress.
have anomalous behavior which requires further investigation. Charging of the metal nanocrystals from the control gate tunneling will not saturate as easily as the Si ones. Furthermore, continuous gate current stress has possibly induce trap states in SiO2 and at the Si/SiO2 interface, which can potentially cause much higher gate and channel leakage current [11] in the deep subthreshold region. We have confirmed that the tunneling and control oxides are of sufficiently good quality for constant-voltage dielectric breakdown, and the gate tunneling oxide growth has identical conditions to the Si-nanocrystal devices. Exact reasons for the enlarged stress-induced channel leakage current again requires further investigation.
Superlattices and Microstructures, Vol. 28, No. 5/6, 2000
399
Acknowledgement—The authors wish to thank the National Science Foundation for financial support of this work.
References [1] S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi, Appl. Phys. Lett. 69, 1232 (1996). Single charge and confinement effects in nano-crystal memories. [2] K. Han, I. Kim, and H. Shih, Semicon Tech. Symp. (Seoul, Korea, 2000). Programming and erasing characteristics of p-channel Si nano-crystal memory. [3] E. C. Kan and Z. Liu, Superlatt. Microstruct. 27, 473 (2000). [4] C. Diorio, P. Hasler, B. A. Minch, and C. A. Mead, IEEE Trans. Electron Devices 43, 1972 (1996). A single-transistor silicon synapse. [5] E. C. Kan and Z. Liu, Sixth Foresight Conference on Nanotechnology (1998). Self-assembled nanoparticles as electronic devices. [6] T. I. Kamins and R. S. Williams, Appl. Phys. Lett. 71, 1201 (1997). Lithography positioning of selfassembled Ge islands on Si (001). [7] R. Notzel, N. N. Ledentsov, L. Daweritz, M. Hohenstein, and K. Ploog, Phys. Rev. Lett. 67, 3812 (1991). [8] Z. Suo and Z. Zhang, Phys. Rev. B58, 5116 (1998). Epitaxial films stabilized by long-range forces. [9] D. A. Bonnell, Y. Liang, M. Wagner, D. Carroll, and M. Ruhle, Acta. Mater. 46, 2263 (1998). Effect of size dependent interface properties on stability of metal clusters on ceramic substrates. [10] S. M. Sze, Physics of Semiconductor Devices (John Wiley and Sons, 1981) 2nd edn. [11] C. Hu, IEDM Tech. Dig., (1996) p. 319. Gate oxide scaling limits and projection.
Process and device characteristics of self-assembled metal nano-crystal EEPROM Z ENGTAO L IU , M YONGSEOB K IM , V ENKAT NARAYANAN , E DWIN C. K AN† School of Electrical and Computer Engineering, Cornell University, Ithaca, NY 14853, U.S.A. (Received 26 July 2000)
Metal nanocrystals self-assembled on gate tunneling oxide can be used to replace the conventional Si/Ge nanocrystals as the floating gate in EEPROM cells. We have demonstrated the successful use of Au and W with their respective process dependence and self-assembly characteristics. The new material options can potentially enhance the applicability and functionality of the nanocrystal EEPROM device. Implications on process integration, in particular the control oxide growth and overall thermal budget, are examined by microscopy, gate current injection and channel mobility monitoring. Charging by hot-carrier injection and control gate tunneling have both been observed by shifts in I –V characteristics. The electrostatic behavior of metal nanocrystals is similar to that of Si nanocrystals in terms of the asymmetrical threshold voltage on source–drain reversal after hot-carrier injection and the Coulomb blockade effects. The electrodynamic behavior is expected to be quite different due to the density of states, but further study is required for quantitative analysis. c 2000 Academic Press
Key words: nanocrystal memories, process integration, carrier injection and tunneling.
1. Introduction Self-assembled nanocrystals embedded in insulators can be used to replace the conventional floating gate in the EEPROM (electrically erasable programmable read-only memory) devices. The nonvolatile charge retention time can be significantly improved due to the Coulomb blockade effect [1], the reduction of charge leakage from weak spots in tunneling oxide [2], and the floating-gate strain release from self-assembly [3]. In addition, since the nanocrystals are more electrically coupled to the channel carriers than to each other, novel device structures such as multi-bit storage, interconnect fault-tolerant quad routers, and electronic synapse transistors [4, 5] can be configured from structural asymmetry. Conventionally the nanocrystals are formed by self assembly of wetting layers or implant-precipitation of Si [1, 2] or Ge [6] mostly due to the anticipated process compatibility. In this paper, we will first present the self-assembly behavior of Au and W on oxide in terms of initial-layer thickness and annealing temperature dependence. We will then compare the process and device characteristics of metal (Au and W) nanocrystal EEPROM with those of Si nanocrystals. † E-mail: [email protected]
0749–6036/00/110393 + 07
$35.00/0
c 2000 Academic Press
394
Superlattices and Microstructures, Vol. 28, No. 5/6, 2000
Before annealing
After annealing
200nm
A
100nm
B
100nm
C
100nm
D
Fig. 1. Dependence of Au nanocrystal self assembly on initial-layer thickness. The annealing is performed by 550 ◦ C RTA for 2 min. A, initial layer of 10 nm; B, initial layer of 5 nm; C, initial layer of 3 nm; D, initial layer of 2 nm.
2. Process characteristics Starting from a clean and atomically smooth Si (100) surface, we grew 5–8 nm gate oxide by lowtemperature dry oxidation. Then a wetting layer of metal (Au and W) was evaporated or sputtered, followed by a RTA (rapid thermal annealing) process with short temperature spikes (within 20 s) close to the bulk eutectic temperature for nanocrystal formation. Note that the nanocrystals may have a very different eutectic temperature due to the size effect—the bulk value is only used as a reference. Transport of metal atoms is limited by temperature-dependent surface mobility and growth is limited by activation of reaction/nucleation sites [7]. Due to length constraints, we will present here only the two most interesting growth phenomena observed in metal nanocrystal formation. In Fig. 1, the dependence of Au nanocrystal self-assembly on initial wetting layer thickness is demonstrated. When the wetting layer is thicker than 10 nm, an irregular island pattern is formed. By reducing the initial layer thickness, dots with rather uniform size and distribution are obtained. At 2 nm initial thickness, start of dot formation can be observed even without annealing. However, we were not able to finish the
Superlattices and Microstructures, Vol. 28, No. 5/6, 2000
395
After annealing
2 µm
A
500nm
C
2 µm
B
200nm
D
Fig. 2. Dependence of W nanocrystal self-assembly on annealing temperature profiles: A, 1000 ◦ C RTA for 2 min. Long spikes of W were formed with length of about 4 µm and width of 200 nm. Anisotropic nucleation is sensitive to the thermal profiles. B, 1050 ◦ C RTA for 2 min. C, 1100 ◦ C RTA for 2 min. Dot formation starts when more surface sites are available for nucleation. D, 1150 ◦ C RTA for 2 min. The size distribution is almost bimodal, with a group at size of 40 nm, and the other at 10 nm.
gate stack process to ascertain that the dots are electrically separated due to following thermal processes. In Fig. 2, the dependence of W nanocrystal self-assembly on annealing temperature profiles is shown. Configuration of W nanocrystals after RTA clearly shows that W nanocrystal growth is nucleation-site limited. At low annealing temperatures, distance between activated sites is much larger than the wetting layer thickness. The returned nucleation sites have slightly different activation energy for different orientation and curvature, which causes anisotropic needle growth. The W nanocrystal aspect ratio for 1000 ◦ C RTA is as high as 20, while it reduces to about 7 for 1050 ◦ C RTA. At higher annealing temperatures when nucleation site spacing is similar to or smaller than the wetting layer thickness, dot formation is obtained. The driving forces for atomic motion in Au self-assembly come from the gradient of the total energy (surface and elastic) and long-range forces [8], in particular electrical double layers [9] which provide the minimal dot separation. The electrical double-layer force comes from repulsion between the substrate depleted dopant charges. W nanocrystal formation has a much higher RTA temperature where intrinsic carriers effectively screen the depletion charges in bulk Si, and the nanocrystal distribution is more irregular. To avoid contamination after the formation of metal nanocrystals, low-temperature PECVD (plasma-enhanced
396
Superlattices and Microstructures, Vol. 28, No. 5/6, 2000
Silicide Control Gate
Possible Nano -pocket Control PECVD Oxide Au Nanocrystals Tunneling Oxide Bulk Si
100 nm
Fig. 3. Gate-stack cross-section of Au-nanocrystal EEPROM devices. The tunneling oxide has a thickness around 8 nm. Selective PECVD oxide growth may cause nano-pockets around the nanocrystals.
chemical vapor deposition) oxide at substrate temperature not exceeding 300 ◦ C was used for control oxide growth. By tuning the plasma energy, a wide range of selective growth can be achieved due to different affinity between metal and SiO2 . In extreme cases which are not appropriate for EEPROM but are very useful features for other applications, large nano-pockets containing the metal nanocrystal can be formed. For some PECVD conditions, we can observe a slow and small drift of subthreshold drain current in EEPROM devices (at times around a few seconds) under low VGS (0–2 V) and VDS (0.1 V) after charging the nanocrystals. This phenomenon seems to be only explainable by the charged nanocrystal adjusting its position in the nano-pocket, since other mechanisms such as oxide charge drift and interface traps have either dramatically different time constants or are inconsistent with the shift direction. After source/drain implants, the control gate and source/drain contacts are deposited with co-sputtered W silicides for electrical contacts. A sample cross-section of the gate stack in a large MOS capacitor area is shown in Fig. 3. In summary, different configurational forces, asymmetrical nucleation and selective deposition are the main processing differences from Si nanocrystals as floating gate materials.
3. Device characteristics Metal nanocrystal EEPROM devices have some similar characteristics to the Si nanocrystal ones. For comparison, a compatible process is used to fabricate Si nanocrystal devices, replacing the Au evaporation step with LPCVD (low-pressure chemical vapor deposition) growth of Si wetting layers followed by RTA. The process flow is similar to our previous runs [3]. The silicon nanocrystal EEPROM characteristics are shown in Figs 4 and 5, and the parallel subthreshold IV curve shift can be observed after charging and erasing from control gate tunneling. Retention time is much longer than 60 h, where additional accelerated stress tests are required for quantitative estimation. The charging time is quite small as a hysteresis IV loop can be observed even for a fast VGS sweep. The contact resistance to source/drain and poly-gate is large for this run, which limits our measurement in above-threshold saturation region. The size of the Si nanocrystal is probably too large to show the threshold voltage plateaus at room temperature [1]. However, Si nanocrystals are definitely formed at the floating-gate layer as seen from observation of asymmetrical IV on source–drain
Superlattices and Microstructures, Vol. 28, No. 5/6, 2000
397
1.E-07
VDS
1.E-08
VGS (A) ID
1.E-09
1.E-10
Initial curve 1.E-11
After -15V control gate charging 60 hours later After 15V control gate erasing
1.E-12 -2
-1.5
-1
-0.5
VGS (V)
Fig. 4. Channel currents with control gate bias sweep in low VDS (50 mV) for Si-nanocrystal EEPROM cell with W/L = 1.8 µm/1.2 µm. Threshold voltage shift caused by nonvolatile charges in nanocrystals can be maintained for much longer than days (stress tests to be done). Symbols used: initial (diamonds); charging from control gate tunneling (circles); charge retention after 60 h (triangles); erase from control gate tunneling (crosses). Notice that the extraction of threshold voltage shift is done at a gate bias much lower than the writing and erasing voltage. 1.E-05
1.E-06
1.E-07
(A) ID
1.E-08
GIDL region
1.E-09
1.E-10
1.E-11
sweep upward sweep downward
1.E-12
1.E-13 -20
-15
-10
-5
0
5
10
15
20
25
VGS (V)
Fig. 5. Typical IV hysteresis for the nanocrystal EEPROM devices above with a fast sweep of VGS . The gate-induced drain leakage (GIDL) at negative control gate bias can be clearly observed. Symbols used: VGS sweep upward (circles) immediately followed by sweeping downward (squares). This figure also demonstrates the property of continuous charging of the nanocrystal EEPROM devices from Fig. 4. The position of the threshold voltage hysteresis will continue to shift due to the large gate bias during the sweep.
reversal similar to Fig. 6. In Fig. 5, a small Esaki diode signature [10] can be observed in the gate-induceddrain-leakage (GIDL) region. Typical Au nanocrystal EEPROM characteristics are shown in Figs 6 and 7, where many similar electrostatic effects can be observed. Effective MOS interface mobility (around 150–300 cm2 V−1 s−1 with substrate doping about 1017 cm−3 ) and high-frequency MOS CV are frequently extracted to ascertain no metal contamination in bulk Si. Presently we have observed several important differences of the metal nanocrystal EEPROM devices from the Si nanocrystal ones. First, close to the conventional GIDL region, the IV curves
398
Superlattices and Microstructures, Vol. 28, No. 5/6, 2000 3.5E-05 Initial Curve (Source end) 3.0E-05 Initial Curve (Drain end) 10 sec after 4-7V Vg sweep at Vds=5V (Source end) 2.5E-05 10 sec after 4-7V Vg sweep at Vds=5V (Drain end)
(A) ID
2.0E-05
1.5E-05
1.0E-05
5.0E-06
0.0E+00 0
0.5
1
1.5
2
2.5
3
VGS (V)
Fig. 6. Above-threshold channel currents for the Au-nanocrystal EEPROM device at high VDS (5 V) with W/L = 1.8 µm/1.2 µm. Symbols used: initial measurement with source grounded and drain at 5 V(diamonds) and drain grounded and source at 5 V (squares); after VGS sweeping from 4 to 7 V for 10 s with source grounded and drain at 5 V (crosses) and with drain grounded and source at 5 V (circles). Si-nanocrystal EEPROM devices have similar behavior.
1.E-06
W/L=3/9, V DS =0.1V
1.E-07
I D(A)
1.E-08
1.E-09
1.E-10
1.E-11 0
0.5
1
1.5
2
2.5
3
3.5
4
VGS (V)
Fig. 7. Channel currents for Au-nanocrystal EEPROM the device in low VDS (0.1 V) with W/L = 5.4 µm/3.6 µm. Symbols used: initial (triangles); first-time charging by control gate tunneling (circles); after continuous VGS sweeping for 20 min (crosses). Note that the drain leakage current in the subthreshold region is much larger after gate-current stress.
have anomalous behavior which requires further investigation. Charging of the metal nanocrystals from the control gate tunneling will not saturate as easily as the Si ones. Furthermore, continuous gate current stress has possibly induce trap states in SiO2 and at the Si/SiO2 interface, which can potentially cause much higher gate and channel leakage current [11] in the deep subthreshold region. We have confirmed that the tunneling and control oxides are of sufficiently good quality for constant-voltage dielectric breakdown, and the gate tunneling oxide growth has identical conditions to the Si-nanocrystal devices. Exact reasons for the enlarged stress-induced channel leakage current again requires further investigation.
Superlattices and Microstructures, Vol. 28, No. 5/6, 2000
399
Acknowledgement—The authors wish to thank the National Science Foundation for financial support of this work.
References [1] S. Tiwari, F. Rana, K. Chan, L. Shi, and H. Hanafi, Appl. Phys. Lett. 69, 1232 (1996). Single charge and confinement effects in nano-crystal memories. [2] K. Han, I. Kim, and H. Shih, Semicon Tech. Symp. (Seoul, Korea, 2000). Programming and erasing characteristics of p-channel Si nano-crystal memory. [3] E. C. Kan and Z. Liu, Superlatt. Microstruct. 27, 473 (2000). [4] C. Diorio, P. Hasler, B. A. Minch, and C. A. Mead, IEEE Trans. Electron Devices 43, 1972 (1996). A single-transistor silicon synapse. [5] E. C. Kan and Z. Liu, Sixth Foresight Conference on Nanotechnology (1998). Self-assembled nanoparticles as electronic devices. [6] T. I. Kamins and R. S. Williams, Appl. Phys. Lett. 71, 1201 (1997). Lithography positioning of selfassembled Ge islands on Si (001). [7] R. Notzel, N. N. Ledentsov, L. Daweritz, M. Hohenstein, and K. Ploog, Phys. Rev. Lett. 67, 3812 (1991). [8] Z. Suo and Z. Zhang, Phys. Rev. B58, 5116 (1998). Epitaxial films stabilized by long-range forces. [9] D. A. Bonnell, Y. Liang, M. Wagner, D. Carroll, and M. Ruhle, Acta. Mater. 46, 2263 (1998). Effect of size dependent interface properties on stability of metal clusters on ceramic substrates. [10] S. M. Sze, Physics of Semiconductor Devices (John Wiley and Sons, 1981) 2nd edn. [11] C. Hu, IEDM Tech. Dig., (1996) p. 319. Gate oxide scaling limits and projection.