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Process modeling of integrated circuit device technology
902
World Abstracts on Microelectronics and Reliability
growth of the electronics industry has resulted from the continued development of new applications, for example, in cars, toys, games, and appliances.
tunately, some of the terms are already archaic because of rapid changes in technology.
A microelectronics technical dictionary. RONALD P. ANJARD. Microelectron. Reliab. 21 (4), 601 (1981). Microelectronic engineers have developed a sophisticated vocabulary over the years. But at the same time, they have included unique, often comical terms which only "'insiders" recognize. These terms deal with equipment, parts and processes. Imagine overhearing a group of engineers discussing their bean pots, yo-yo, white elephants and bat caves. They probably are not talking about sports, movies or rummage sales. All these terms are included in the New Revised Technical Dictionary. There follows a selection from this "'new" dictionary. Unfor-
Comparison of new technologies for VLSI: possibilities and limitations. YOSHIONISHt. Microelectronics J. 12 (6), 5 ( 1981 ). Device technology and microfabrication process technology for LSI and VLSI are discussed with respect to the present status and future prospects. Comparisons between MOS and bipolar, CMOS and NMOS, SOS and bulk are the primary subjects for discussion, and the practical limitation to reduction of device geometry is also considered in conjunction with technical feasibility of process technologies such as lithography, device isolation, and novel gate and intcrconnection materials.
5. M I C R O E L E C T R O N I C S - - D E S I G N
AND
CONSTRUCTION
Board testing meets the challenges of ECL. JOE PRANG. Electronics 146 (15 December 1981 ). ECL's negative voltages, terminator requirements, and design opportunities present special test problems in the production arena.
solution of impurity diffusion is considered, including grid and time step constraints. New efforts in two-dimensional process modeling are briefly discussed along with test structure work needed for parameter estimation.
Multi-layer 2 MIL line technology. TAMIO SAITO and YOSHIKATSU FUKUMOTO. Electrocomponent Sci. Technol. 8, 91 (1981). Multi-layer 2 mil line technology has been increasingly required for VLSI and very high speed logic devices. This technology makes it possible to shorten the length of interconnection lines between VLSI silicon chips. Thus the signal propagation delay on the transmission lines can be minimized. Multi-layer 2 mil line technology research history, the new method and usages are discussed in this paper.
IC makers turn to telecommunications. J. ROBERT LINEBACK. Electronics 84 (30 November 1981). Switchover to digital techniques makes market attractive, with systems houses expected to rely less on in-house work.
A survey of optimization techniques for integrated-circuit design. ROBERT K. BRAYTON, GARY D. HACHTEL and ALBERTO L. SANGIOVANNI-VINCENTELLI.Proc. IEEE 69 (10), 1334 (October 1981 ). We survey contemporary optimization techniques and relate these to optimization problems which arise in the design of integrated circuits. Theory, algorithms, and programs are reviewed, and an assessment is made of the impact optimization has had and will have on integratedcircuit design. Integrated circuits are characterized by complex tradeoffs between multiple nonlinear objectives with multiple nonlinear and sometimes nonconvex constraints. Function and gradient evaluations require the solution of very large sets of nonlinear differential equations, consequently they are inaccurate and extremely expensive. Furthermore, the parameters to be optimized are subject to inherent statistical fluctuations. We focus on those multiobjective constrained optimization techniques which are appropriate to this environment. Anisotropy control in dry etching. R. H. BRUCE. Solid-State Technology 64 (October 1981). The need for anisotropic dry etching techniques to accommodate shrinking device geometries is demonstrated. The importance of ion bombardment in attaining desired edge profiles, and the role of this process in attaining vertical and undercut profiles are discussed. Parameters of ion bombardment processes are reviewed, and the effects on etch profiles of varying these parameters are described. Process modeling of integrated circuit device technology. ROBERT W. DUTTON and STEPHEN E. HANSEN. Proc. IEEE 69 (10), 1305 (October 1981). This paper reviews the field of computer-aided design as applied to process modeling of integrated circuit technology and devices. Device design applications for process modeling are considered for both bipolar and NMOS technologies. The kinetics of oxidation and impurity diffusion in silicon are discussed. The numerical
Bulk charge effects in VLSI MOSFETs. RAJENDRA KU/vlAR and SAVVASG. CHAMBERLAIN.Solid-State Electronics 24 (l 1), 1071 (1981). An analysis of the relative magnitudes of the bulk charge for three MOSFET structures suitable for VLSI devices, such as N M O S (normal), VMOS (V slot) and UMOS (U slot), is carried out. It is shown that even for the same channel design (i.e. channel length, doping, source/ drain junction depth, and oxide thickness), the amount of bulk charge and hence the threshold voltage can be significantly different for the three structures. This effect becomes more important with decreasing channel length, and increasing source to substrate bias. Further, for a given channel length, the bulk charge and hence the threshold voltage of an NMOS decreases with increasing source/drain junction depth. However, for the VMOS and UMOS structures, the bulk charge as well as the threshold voltage do not depend on the junction depth of the source/drain diffusion. An expression is also derived for the bulk charge of UMOS transistors valid for both short and long channels. Multiuser IC cell library buys custom densities at gate-array prices. WILLIAM LOESCH and ALEX YOUNG. Electronics 114 (17 November 1981). Use of standard circuit blocks for chip design apportions development costs, trims turnaround times. CAD tools most change to meet the needs of VLSI. BENJAMIN K. LEE and CASEY JONES. Electronics 108 (17 November 1981). Application-specific chips demand greater man-machine interaction. Logic simulation of MOS circuits based on information obtained from their masks. LAD1SLAV SZANTO. TESLA Electronics 1, 8 (1981 ). Computer programs for logic function simulation were originally developed as a means for checking the correctness of a logic diagram being designed. Their use for checking the correctness of the corresponding masks requires a relatively complex task to be performed of logic diagram recognition based on information gained from the masks. The logic simulation proposed in this paper is based on the idea that the logic states propagate not from node to node of the logic elements network but rather through diffusion regions defined directly by the masks. In the paper
World Abstracts on Microelectronics and Reliability
growth of the electronics industry has resulted from the continued development of new applications, for example, in cars, toys, games, and appliances.
tunately, some of the terms are already archaic because of rapid changes in technology.
A microelectronics technical dictionary. RONALD P. ANJARD. Microelectron. Reliab. 21 (4), 601 (1981). Microelectronic engineers have developed a sophisticated vocabulary over the years. But at the same time, they have included unique, often comical terms which only "'insiders" recognize. These terms deal with equipment, parts and processes. Imagine overhearing a group of engineers discussing their bean pots, yo-yo, white elephants and bat caves. They probably are not talking about sports, movies or rummage sales. All these terms are included in the New Revised Technical Dictionary. There follows a selection from this "'new" dictionary. Unfor-
Comparison of new technologies for VLSI: possibilities and limitations. YOSHIONISHt. Microelectronics J. 12 (6), 5 ( 1981 ). Device technology and microfabrication process technology for LSI and VLSI are discussed with respect to the present status and future prospects. Comparisons between MOS and bipolar, CMOS and NMOS, SOS and bulk are the primary subjects for discussion, and the practical limitation to reduction of device geometry is also considered in conjunction with technical feasibility of process technologies such as lithography, device isolation, and novel gate and intcrconnection materials.
5. M I C R O E L E C T R O N I C S - - D E S I G N
AND
CONSTRUCTION
Board testing meets the challenges of ECL. JOE PRANG. Electronics 146 (15 December 1981 ). ECL's negative voltages, terminator requirements, and design opportunities present special test problems in the production arena.
solution of impurity diffusion is considered, including grid and time step constraints. New efforts in two-dimensional process modeling are briefly discussed along with test structure work needed for parameter estimation.
Multi-layer 2 MIL line technology. TAMIO SAITO and YOSHIKATSU FUKUMOTO. Electrocomponent Sci. Technol. 8, 91 (1981). Multi-layer 2 mil line technology has been increasingly required for VLSI and very high speed logic devices. This technology makes it possible to shorten the length of interconnection lines between VLSI silicon chips. Thus the signal propagation delay on the transmission lines can be minimized. Multi-layer 2 mil line technology research history, the new method and usages are discussed in this paper.
IC makers turn to telecommunications. J. ROBERT LINEBACK. Electronics 84 (30 November 1981). Switchover to digital techniques makes market attractive, with systems houses expected to rely less on in-house work.
A survey of optimization techniques for integrated-circuit design. ROBERT K. BRAYTON, GARY D. HACHTEL and ALBERTO L. SANGIOVANNI-VINCENTELLI.Proc. IEEE 69 (10), 1334 (October 1981 ). We survey contemporary optimization techniques and relate these to optimization problems which arise in the design of integrated circuits. Theory, algorithms, and programs are reviewed, and an assessment is made of the impact optimization has had and will have on integratedcircuit design. Integrated circuits are characterized by complex tradeoffs between multiple nonlinear objectives with multiple nonlinear and sometimes nonconvex constraints. Function and gradient evaluations require the solution of very large sets of nonlinear differential equations, consequently they are inaccurate and extremely expensive. Furthermore, the parameters to be optimized are subject to inherent statistical fluctuations. We focus on those multiobjective constrained optimization techniques which are appropriate to this environment. Anisotropy control in dry etching. R. H. BRUCE. Solid-State Technology 64 (October 1981). The need for anisotropic dry etching techniques to accommodate shrinking device geometries is demonstrated. The importance of ion bombardment in attaining desired edge profiles, and the role of this process in attaining vertical and undercut profiles are discussed. Parameters of ion bombardment processes are reviewed, and the effects on etch profiles of varying these parameters are described. Process modeling of integrated circuit device technology. ROBERT W. DUTTON and STEPHEN E. HANSEN. Proc. IEEE 69 (10), 1305 (October 1981). This paper reviews the field of computer-aided design as applied to process modeling of integrated circuit technology and devices. Device design applications for process modeling are considered for both bipolar and NMOS technologies. The kinetics of oxidation and impurity diffusion in silicon are discussed. The numerical
Bulk charge effects in VLSI MOSFETs. RAJENDRA KU/vlAR and SAVVASG. CHAMBERLAIN.Solid-State Electronics 24 (l 1), 1071 (1981). An analysis of the relative magnitudes of the bulk charge for three MOSFET structures suitable for VLSI devices, such as N M O S (normal), VMOS (V slot) and UMOS (U slot), is carried out. It is shown that even for the same channel design (i.e. channel length, doping, source/ drain junction depth, and oxide thickness), the amount of bulk charge and hence the threshold voltage can be significantly different for the three structures. This effect becomes more important with decreasing channel length, and increasing source to substrate bias. Further, for a given channel length, the bulk charge and hence the threshold voltage of an NMOS decreases with increasing source/drain junction depth. However, for the VMOS and UMOS structures, the bulk charge as well as the threshold voltage do not depend on the junction depth of the source/drain diffusion. An expression is also derived for the bulk charge of UMOS transistors valid for both short and long channels. Multiuser IC cell library buys custom densities at gate-array prices. WILLIAM LOESCH and ALEX YOUNG. Electronics 114 (17 November 1981). Use of standard circuit blocks for chip design apportions development costs, trims turnaround times. CAD tools most change to meet the needs of VLSI. BENJAMIN K. LEE and CASEY JONES. Electronics 108 (17 November 1981). Application-specific chips demand greater man-machine interaction. Logic simulation of MOS circuits based on information obtained from their masks. LAD1SLAV SZANTO. TESLA Electronics 1, 8 (1981 ). Computer programs for logic function simulation were originally developed as a means for checking the correctness of a logic diagram being designed. Their use for checking the correctness of the corresponding masks requires a relatively complex task to be performed of logic diagram recognition based on information gained from the masks. The logic simulation proposed in this paper is based on the idea that the logic states propagate not from node to node of the logic elements network but rather through diffusion regions defined directly by the masks. In the paper