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Process optimization and characterization of deep metal–junction contact
Microelectronic Engineering 71 (2004) 321–328 www.elsevier.com/locate/mee
Process optimization and characterization of deep metal–junction contact Junghwan Lee *, Jaehan Cha SoC Device Team, System IC R&D, Hynix Semiconductor Inc., 1, Hyangjeong-dong, Hungduk-ku, Cheongju-si 361-725, Republic of Korea Received 16 September 2003; received in revised form 13 January 2004; accepted 12 February 2004
Abstract In this paper, we elaborate a process optimization of deep metal contact in 0.25 lm embedded DRAM technology and investigate its electrical characteristic. The contact size is 0.32 lm and its height is varied between 2.1 and 3.8 lm which give aspect ratio from 6.7 to 11.9. It appears that both Ti thickness and aspect ratio play important role on contact resistance. Especially, Pþ contact resistance is more sensitive to these parameters. Pþ contact resistance in while Nþ contact contact array is increased from 1 to 4 KX per contact when Ti thickness decreases from 900 to 500 A, resistance is just increased from 300 to 400 X. TEM image reveals that the degree of Ti silicidation depends on the Ti however, it becomes thickness. The boundary between silicon and TiSi2 is non-uniform with Ti thickness of 500 A, To characterize the behavior of current flow in various contacts, both uniform and flat with Ti thickness of 900 A. contact array and Kelvin resistor patterns are used. It appears that Schottky barrier plays major role at low voltage region, while the spreading resistance dominates at high voltage region and thus contact resistance approaches to 220 X at high voltage region regardless of process condition. The Schottky barrier evaluated by thermionic emission model increases with decreasing Ti thickness and increasing aspect ratio. It appears that a relationship between Schottky barrier and process parameters is given by Schottky barrier energy ¼ (Ti thickness)0:26 (aspect ratio) 0:53 . Ó 2004 Elsevier B.V. All rights reserved. Keywords: Contact resistance; Ti thickness; Aspect ratio; Schottky barrier; Thermionic emission model
1. Introduction There has been increasing interest of embedded DRAM for a System-on-Chip (SOC) application * Corresponding author. Tel.: 82-43-270-3930/82-11-2381192; fax: 82-43-270-2778. E-mail addresses: [email protected] (J. Lee), [email protected] (J. Cha).
[1–4]. The advantages of embedding DRAM to logic circuits are increased bandwidth, reduced power consumption, and small die size. Various DRAM cells have been used for embedded DRAM. Mainly, it can be divided two ways. One is to use trench capacitor for memory cell [5–7]. In this case, the capacitor is formed before transistors are made. Therefore, the advantage of trench capacitor is that high logic performance can be achieved
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and contact formation between metal and junction is relatively easy. However, it has disadvantage such as difficulty in capacitor formation with scale down and relatively large soft error rate. The other is to use stack capacitor [8–10]. Stack capacitor has very strong immunity to soft error and easier scale down than trench capacitor. However, it is difficult to make high performance transistor which is compatible to standard logic since the capacitor formation usually requires over 800 °C annealing temperature at which Pþ doped gate and salicide layer are degraded. Also, since cylinder type capacitor is required to obtain necessary capacitance, the contact depth between metal and junction is very deep compared with standard logic device and embedded DRAM with trench capacitor. Note that this difficulty of contact formation in stack capacitor is critical in yield up of device. In general, barrier metal is used as sandwiching layer between metal and silicon to prevent their intermixing which results in a large of leakage current [11]. In deep submicron technology, the thickness of barrier metal plays a critical role in contact resistance and leakage current. For example, when Ti/TiN stack layer is used as barrier metal, the Ti thickness is a major factor on resistance since it reacts with silicon, and thus forms TiSi2 . The reaction rate depends on the Ti thickness and doping concentration in the junction [12,13]. Note that the thickness of Ti on the junction surface depends on the step height and angle of the contact. The physics in contact resistance has been interpreted by Schottky barrier conception. When a doping level in junction is low, Schottky barrier acts as a diode, which has lower turn on diode voltage compared with junction diode. Therefore, Schottky diode has been frequently used in highspeed devices such as GaAs [14,15]. With increasing doping concentration at interface, Schottky diode becomes Ohmic contact with severe barrier lowering which results in increased tunneling current [16,17]. Recently, thermionic emission theory has been developed to interpret the physics of metal contact [18,19]. As the impurity concentration increases, a thermionic emission becomes dominant factor and the current flow depends on both the barrier height and the impurity concentration. In thermionic emission model, the plot of
logarithmic current with applied voltage deviates from a linear behavior near the low voltage since the tunneling current is dramatically increased. To investigate the characteristics of Schottky diode, three methods such as current–voltage measurement, activation energy measurement and photoelectric measurement have been widely used [20]. However, for very small contact size used in deep sub micron technology, it is difficult to use activation energy measurement and photoelectric measurement due to area restriction. Therefore, current–voltage measurement is suitable method in this case. In this paper, we present the dependency of contact resistance both on barrier metal thickness and contact aspect ratio. Also, the behavior of contact with applied voltage is investigated and analyzed by thermionic emission model to evaluate Schottky barriers of small metal–semiconductor contacts.
2. Experiments A 0.25 lm embedded DRAM process is used to fabricate metal to junction contacts using p-type h1 0 0i silicon substrate with resistivity from 9 to 12 X-cm. After formation of modified LOCOS isolation and gate patterning, Nþ and Pþ junctions are formed. Tungsten polycide is used for gate material. After stack DRAM cell formation, a CMP process is used for planarization. The stack capacitor results in very deep metal contact after CMP process. In this study, the aspect ratio in which contact depth is divided by contact size is varied from 6.7 to 11.9. Note that contact size is 0.32 lm. After formation of contact by lithography and dry etching, barrier metal is deposited and annealed at 650 °C for 10 min to make ohmic contact by reaction between Ti and Si at the metal–junction interface. To investigate the variation of Schottky barrier height with barrier metal thickness, three different thickness of Ti is deposited. The thickness are 50, 70, and 90 nm, respectively. Contact holes are plugged with tungsten and wired with aluminum. Fig. 1 shows the cross section schematic and SEM picture of resulted device. Contact array and Cross Bridged Kelvin Resistor patterns are used to measure contact resis-
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Fig. 1. A cross-sectional view of device structure (a) and SEM picture (b). Note that very deep metal to junction contact due to cylinder type stack capacitor.
tance. The current–voltage characteristic of contact is measured by using a semiconductor parameter analyzer (HP4156A). Transmission Electron Microscopy (TEM) is used to investigate interface morphology between barrier metal and silicon junction.
3. Results and discussion Fig. 2 shows the variation of Nþ and Pþ contact resistances as a function of Ti thickness. The resistance is measured with 1000 contact arrays at
the aspect ratio of 7.8. It appears that Pþ contact resistance is more sensitive to Ti thickness. While the Nþ contact resistance increases from 300 to 400 X/contact, the Pþ contact resistance increases from 1000 to 4000 X/contact when Ti thickness Also, the standard decreases from 900 to 500 A. deviation increases with decreasing Ti thickness for both Pþ and Nþ contact resistances, however, the degree is much higher in Pþ contact. Therefore, it can be deduced from Fig. 2 that Pþ contact is very sensitive to Ti thickness and thus we focus to behavior of metal–Pþ contact resistance on process parameters.
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Fig. 2. A cumulative plot of metal–Nþ active contact resistance (a) and metal–Pþ active contact resistance (b) measured from 1 K contact array. Note that Ti thickness is varied while aspect ratio is 7.8.
Fig. 3. A cumulative plot of metal–Nþ active contact resistance (a) and metal–Pþ active contact resistance (b) measured from Kelvin resistor. Note that Ti thickness is varied while aspect ratio is 7.8.
For more detailed investigation of contact resistance on measurement condition, Kelvin pattern is also used. Note that, while Kelvin resistor gives contact resistance at the applied voltage of 1 V, contact array pattern gives contact resistance at very low voltage difference since adjacent contacts have similar potential. Fig. 3 shows the variation of Kelvin resistance of both Nþ and Pþ contacts as a function of Ti thickness. As mentioned, since Kelvin pattern is measured with directly applied voltage in contact, it gives lower contact resistance than that of chain pattern. However, the difference is much larger in Pþ contact resistance when the Fig. 3 is compared with Fig. 2. For example, when Kelvin pattern gives the Ti thickness is 500 A,
contact resistance of 850 X while chain pattern gives 4000 X. These results imply that current flow mechanism in Pþ contact is very much different depending on potential difference. Fig. 4 shows the variation of Pþ contact resistance as a function of aspect ratio at Ti thickness As shown, the contact resistance from of 900 A. Kelvin pattern is almost constant with increasing aspect ratio, while the contact resistance from chain pattern slightly increases. Therefore, it appears that contact resistance has a little dependency on aspect ratio when the Ti thickness is 900 This suggests that the enough Ti for reaction A. with silicon to make TiSi2 is deposited in the aspect ratio given in Fig. 4. Also, similar experiment
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Fig. 4. A variation of metal–Pþ contact resistance as a function Circle is of aspect ratio at constant Ti thickness of 900 A. contact resistance obtained from array pattern and triangle is contact resistance obtained from Kelvin resistor.
It is found is performed with Ti thickness of 500 A. that a little current flow occurs in Pþ contact when the aspect ratio is over 9.0. The contact resistance at this condition exceeds 15 KX/contact. This implies that enough TiSi2 layer for ohmic contact is not formed due to poor step coverage of Ti during sputtering deposition. Fig. 5 shows the TEM image at different Ti respectively, tathickness of 500, 700, and 900 A, ken with aspect ratio of 7.8. As shown, the shape and thickness of grown TiSi2 by the reaction between Ti and Si substrate are different depending on the deposited Ti thickness. It seems that the grown TiSi2 thickness increases with increasing deposited Ti thickness. However, more distinguishable result is a boundary shape between TiSi2 and Si substrate. The boundary is non-uniform at of Ti, however, it is rounded when Ti 500 A It becomes flat on the thickness increased to 700 A. These bottom side when Ti thickness is 900 A. results suggest that about 900 A Ti is necessary to grow uniform Ti silicide layer. To investigate voltage dependency of contact resistance, Kelvin resistor is used. Fig. 6 shows the result with different Ti thickness (Fig. 6(a)) and aspect ratio (Fig. 6(b)). As shown, contact resistance increases with decreasing bias voltage. In particular, this phenomenon is very large with Ti at aspect ratio of 8.5. It should thickness of 500 A
Fig. 5. TEM image of contact region at different Ti thickness: (a), 700 A (b), and 900 A (c). The aspect ratio is 7.8. 500 A
be noticed that the components of contact resistance can be divided into two parts. One is a Schottky barrier at the interface and the other is a spreading resistance due to the current crowding at the contact. Note that the Schottky barrier depends on the voltage difference across the contact
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in metal–semiconductor contacts are thermionic emission and carrier tunneling. In an ideal metal– semiconductor system, the potential energy barrier to the flow of charge carriers is primarily determined by the work-function difference between the metal and the semiconductor. In practice, however, the barrier height also varies as a function of electric field and impurity concentration at the interface. The characteristic of Schottky barrier height can be evaluated by Padovani and StrattonÕs theory. The details are given elsewhere [21]. Briefly, the current flow near zero bias voltage is given by 1=2 Ap1=2 E00 ðEB þ n2 Þ1=2 n 2 EB þ n 2 JS0 ¼ exp ; kT coshðE00 =kT Þ kT E00 ð1Þ
Fig. 6. The variation of contact resistance as a function of bias voltage in Kelvin resistor at constant aspect ratio of 8.5 (a) and (b). constant Ti thickness of 900 A
and the spreading resistance depends on the contact size and doping concentration. Hence, as the applied bias voltage is increased, contribution from Schottky barrier becomes negligible, and thus pure spreading resistance contributes to contact resistance. Fig. 6 shows that this value is 220 X regardless of Ti thickness and aspect ratio. Since the spreading resistance is constant, the increase of contact resistance at the low bias voltage is due to the increased Schottky barrier height. In Schottky barrier, carrier transport occurs four different mechanisms: thermionic emission over the potential barrier, carrier tunneling through potential barrier, carrier recombination and/or generation in the depletion region, and carrier recombination in the neutral region. Among them, the dominant factors of current flow
where JS0 is the saturation current without applied voltage, A is a classical Richardson constant, E00 is a constant related to barrier characteristic, EB is the Schottky barrier height, n2 is the energy of the Fermi level of the semiconductor measured with respect to the bottom of its conduction band, k is the Boltzmann constant, and T is a Kelvin temperature. Since E00 can be obtained from the logarithmic plot of the current density as a function of the applied voltage, the Schottky barrier (EB ) is calculated with Eq. 1. Fig. 7 shows the result. As shown, the EB increases with increasing aspect ratio and decreasing Ti thickness. EB is increased from 0.485 to 0.54 eV when the Ti thickness is at a constant aspect decreased from 900 to 500 A ratio of 6.7. When the aspect ratio is increased to 7.5, sharper increase in EB occurs with decreasing Ti thickness. Also, it appears that EB is dependent to aspect ratio at constant Ti thickness and the degree of variation strongly depends on Ti thickness. As shown, when the aspect ratio is increased from 6.7 to 7.5, EB is increased 1.05 times with Ti However, when the thickness thickness of 900 A. of Ti is 500 A, the increment is 1.1 times. These imply that the thickness of TiSi2 layer formed by the reaction between Ti and silicon plays important role on EB . Due to step coverage during Ti sputtering, longer deposition time and lower aspect ratio result in thicker TiSi2 layer. Indeed, TEM in Fig. 5 reveals that the thickness of TiSi2 on the bottom of contact hole is increased from
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shown, N d is varied within error boundary regardless of process conditions. Therefore, as a summary of the results from Figs. 7 and 8, it can be concluded that Ti thickness at the silicon surface is the major factor to affect on EB . A mathematical simulation is performed for more elaborated investigation of Schottky barrierÕs dependency to Ti thickness and aspect ratio. Fig. 9 shows the result. It reveals that a linear
Fig. 7. A plot showing Schottky barrier energy as a function of Ti thickness and aspect ratio.
when the Ti thickness is increased 450 to 700 A Jeon et al. [22] reported that from 500 to 900 A. TiSi2 could be either C49 or C54 phase depending on the TiSi2 thickness when the annealing temperature is about 650 °C. Since the annealing is performed at 650 °C during 10 min, the thicker TiSi2 layer might have more C54 phase which is thermodynamically stable. Note that resistivity of C54 is 15 lX-cm while resistivity of C49 is 60 lXcm [23]. One more important parameter on EB is the doping concentration at the interface between TiSi2 and silicon. It is shown that the doping concentration can be obtained from E00 by the following equation [21] rffiffiffiffiffiffiffiffiffiffiffiffi Nd 11 ½eV; ð2Þ E00 ¼ 1:85 10 er mr where Nd is the doping concentration at the TiSi2 / Si interface, er is relative dielectric constant of silicon, and mr is the effective tunneling mass measured in the unit of free electron mass. As mentioned earlier, E00 can be obtained from the logarithmic plot of the current density as a function of the applied voltage. Since er and mr are constants, N d can be calculated by Eq. (2). Fig. 8 shows the variation of N d as a function of barrier metal thickness at two different aspect ratios. As
Fig. 8. A variation of surface doping concentration as a function of Ti thickness at different aspect ratio.
Fig. 9. Shcottky barrier energy as a function of (Ti thickness)0:26 (aspect ratio)0:53 gives linear line.
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relationship is obtained among them and given by Schottky barrier energy ¼ (Ti thickness)0:26 (aspect ratio)0:53 . However, since the Ti thickness at the bottom of contact hole is determined by step coverage being varied with sputtering condition and machine, it should be noticed that the dependency of Schottky barrier energy on aspect ratio should be modified when a different deposition system is used. In this study, Ti deposition is performed by IMP (Ion Metal Plasma) Ti sputter system (Endura5500, AMAT). It appears that step coverage of Ti depends on aspect ratio. The step coverage is 18% with aspect ratio of 7.5 and 38% with aspect ratio of 4.2, respectively.
4. Conclusion In this paper, process optimization of deep metal to junction contact is performed. It appears that both Ti thickness and aspect ratio play important role on contact resistance. Especially, Pþ contact resistance is more sensitive to these parameters. Pþ contact resistance in contact array is increased from 1 to 4 KX per contact when Ti while Nþ thickness decreases from 900 to 500 A, contact resistance is just increased from 300 to 400 X. TEM image reveals that the degree of Ti silicidation depends on the Ti thickness. The boundary between silicon and TiSi2 is non-uniform with however, it becomes uniTi thickness of 500 A, form and flat with Ti thickness of 900 A. To investigate voltage dependency of contact resistance, both contact array and Kelvin resistor patterns are used. It appears that Schottky barrier plays major role at low voltage region, while the contact resistance approaches to 220 X at high voltage region regardless of process condition. The Schottky barrier increases with decreasing Ti thickness and increasing aspect ratio. Thermionic
emission model is used to evaluate Schottky barrier height. It appears that a relationship between Schottky barrier and process parameters is given by Schottky barrier energy ¼ (Ti thickness)0:26 (aspect ratio)0:53 .
References [1] Y.H. Park, S.H. Han, J.H. Lee, H.J. Yoo, J. Solid-State Circuits 36 (6) (2001) 944. [2] N. Yanagiya et al., IEDM Tech. Dig. (2002) 57. [3] S. Lyer, H. Kalter, IEEE Spectrum 36 (1999) 56. [4] K. Kim, C.G. Hwang, J.G. Lee, IEEE Trans. Electron. Dev. 45 (1998) 598. [5] S. Crowder et al., IEDM Tech. Dig. (1998) 1017. [6] H. Yoshimura, et al., Symp. On VLSI Tech. (2000) 144. [7] K. Inoh, et al., Symp. On VLSI Tech. (2003) 63. [8] D.W. Ha, D.W. Shin, G.H. Koh, J.G. Lee, S.H. Lee, Y.S. Ahn, H.S. Jeong, T.Y. Chung, K.N. Kim, IEEE Trans. Electron Dev. 47 (7) (2000) 1499. [9] J.M. Park et al., IEDM Tech. Dig. (2002) 823. [10] S. Nakamura et al., IEDM Tech. Dig. (1998) 1029. [11] S. Wolf (Ed.), Silicon Processing for the VLSI Era, vol. 2, Lattice Press, 1990, p. 121. [12] R.W. Bower, Appl. Phys. Lett. 23 (1973) 99. [13] M.M. Farhani, T.E. Turner, J.J. Narnes, J. Electrochem. Soc. (1987) 2835. [14] S. Sassen, B. Witzigmann, C. Wolk, H. Brugger, IEEE Trans. Electron Dev. 47 (2000) 24. [15] K. Shenai, R.W. Dutton, IEEE Trans. Electron Dev. 35 (1988) 468. [16] A.Y.C. Yu, Solid-State Electron. 13 (1970) 239. [17] C.Y. Chang, Y.K. Fang, S.M. Sze, Solid-State Electron. 14 (1971) 541. [18] C.R. Crowell, S.M. Sze, Solid-State Electron. 9 (1966) 1035. [19] F.A. Padovani, R. Stratton, Solid-State Electron. 9 (1996) 695. [20] S.M. Sze, Physics of Semiconductor Devices, second ed., Wiley, New York, 1981. [21] M.G. Jang, J.H. Lee, ETRI J. 24 (6) (2002) 455. [22] H. Jeon, C.A. Sukow, J.W. Honeycutt, G.A. Rozgonyi, R.J. Nemanich, J. Appl. Phys. 71 (1992) 4269. [23] K. Maex, Mater. Sci. Eng. R11 (1993) 53.
Process optimization and characterization of deep metal–junction contact Junghwan Lee *, Jaehan Cha SoC Device Team, System IC R&D, Hynix Semiconductor Inc., 1, Hyangjeong-dong, Hungduk-ku, Cheongju-si 361-725, Republic of Korea Received 16 September 2003; received in revised form 13 January 2004; accepted 12 February 2004
Abstract In this paper, we elaborate a process optimization of deep metal contact in 0.25 lm embedded DRAM technology and investigate its electrical characteristic. The contact size is 0.32 lm and its height is varied between 2.1 and 3.8 lm which give aspect ratio from 6.7 to 11.9. It appears that both Ti thickness and aspect ratio play important role on contact resistance. Especially, Pþ contact resistance is more sensitive to these parameters. Pþ contact resistance in while Nþ contact contact array is increased from 1 to 4 KX per contact when Ti thickness decreases from 900 to 500 A, resistance is just increased from 300 to 400 X. TEM image reveals that the degree of Ti silicidation depends on the Ti however, it becomes thickness. The boundary between silicon and TiSi2 is non-uniform with Ti thickness of 500 A, To characterize the behavior of current flow in various contacts, both uniform and flat with Ti thickness of 900 A. contact array and Kelvin resistor patterns are used. It appears that Schottky barrier plays major role at low voltage region, while the spreading resistance dominates at high voltage region and thus contact resistance approaches to 220 X at high voltage region regardless of process condition. The Schottky barrier evaluated by thermionic emission model increases with decreasing Ti thickness and increasing aspect ratio. It appears that a relationship between Schottky barrier and process parameters is given by Schottky barrier energy ¼ (Ti thickness)0:26 (aspect ratio) 0:53 . Ó 2004 Elsevier B.V. All rights reserved. Keywords: Contact resistance; Ti thickness; Aspect ratio; Schottky barrier; Thermionic emission model
1. Introduction There has been increasing interest of embedded DRAM for a System-on-Chip (SOC) application * Corresponding author. Tel.: 82-43-270-3930/82-11-2381192; fax: 82-43-270-2778. E-mail addresses: [email protected] (J. Lee), [email protected] (J. Cha).
[1–4]. The advantages of embedding DRAM to logic circuits are increased bandwidth, reduced power consumption, and small die size. Various DRAM cells have been used for embedded DRAM. Mainly, it can be divided two ways. One is to use trench capacitor for memory cell [5–7]. In this case, the capacitor is formed before transistors are made. Therefore, the advantage of trench capacitor is that high logic performance can be achieved
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and contact formation between metal and junction is relatively easy. However, it has disadvantage such as difficulty in capacitor formation with scale down and relatively large soft error rate. The other is to use stack capacitor [8–10]. Stack capacitor has very strong immunity to soft error and easier scale down than trench capacitor. However, it is difficult to make high performance transistor which is compatible to standard logic since the capacitor formation usually requires over 800 °C annealing temperature at which Pþ doped gate and salicide layer are degraded. Also, since cylinder type capacitor is required to obtain necessary capacitance, the contact depth between metal and junction is very deep compared with standard logic device and embedded DRAM with trench capacitor. Note that this difficulty of contact formation in stack capacitor is critical in yield up of device. In general, barrier metal is used as sandwiching layer between metal and silicon to prevent their intermixing which results in a large of leakage current [11]. In deep submicron technology, the thickness of barrier metal plays a critical role in contact resistance and leakage current. For example, when Ti/TiN stack layer is used as barrier metal, the Ti thickness is a major factor on resistance since it reacts with silicon, and thus forms TiSi2 . The reaction rate depends on the Ti thickness and doping concentration in the junction [12,13]. Note that the thickness of Ti on the junction surface depends on the step height and angle of the contact. The physics in contact resistance has been interpreted by Schottky barrier conception. When a doping level in junction is low, Schottky barrier acts as a diode, which has lower turn on diode voltage compared with junction diode. Therefore, Schottky diode has been frequently used in highspeed devices such as GaAs [14,15]. With increasing doping concentration at interface, Schottky diode becomes Ohmic contact with severe barrier lowering which results in increased tunneling current [16,17]. Recently, thermionic emission theory has been developed to interpret the physics of metal contact [18,19]. As the impurity concentration increases, a thermionic emission becomes dominant factor and the current flow depends on both the barrier height and the impurity concentration. In thermionic emission model, the plot of
logarithmic current with applied voltage deviates from a linear behavior near the low voltage since the tunneling current is dramatically increased. To investigate the characteristics of Schottky diode, three methods such as current–voltage measurement, activation energy measurement and photoelectric measurement have been widely used [20]. However, for very small contact size used in deep sub micron technology, it is difficult to use activation energy measurement and photoelectric measurement due to area restriction. Therefore, current–voltage measurement is suitable method in this case. In this paper, we present the dependency of contact resistance both on barrier metal thickness and contact aspect ratio. Also, the behavior of contact with applied voltage is investigated and analyzed by thermionic emission model to evaluate Schottky barriers of small metal–semiconductor contacts.
2. Experiments A 0.25 lm embedded DRAM process is used to fabricate metal to junction contacts using p-type h1 0 0i silicon substrate with resistivity from 9 to 12 X-cm. After formation of modified LOCOS isolation and gate patterning, Nþ and Pþ junctions are formed. Tungsten polycide is used for gate material. After stack DRAM cell formation, a CMP process is used for planarization. The stack capacitor results in very deep metal contact after CMP process. In this study, the aspect ratio in which contact depth is divided by contact size is varied from 6.7 to 11.9. Note that contact size is 0.32 lm. After formation of contact by lithography and dry etching, barrier metal is deposited and annealed at 650 °C for 10 min to make ohmic contact by reaction between Ti and Si at the metal–junction interface. To investigate the variation of Schottky barrier height with barrier metal thickness, three different thickness of Ti is deposited. The thickness are 50, 70, and 90 nm, respectively. Contact holes are plugged with tungsten and wired with aluminum. Fig. 1 shows the cross section schematic and SEM picture of resulted device. Contact array and Cross Bridged Kelvin Resistor patterns are used to measure contact resis-
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Fig. 1. A cross-sectional view of device structure (a) and SEM picture (b). Note that very deep metal to junction contact due to cylinder type stack capacitor.
tance. The current–voltage characteristic of contact is measured by using a semiconductor parameter analyzer (HP4156A). Transmission Electron Microscopy (TEM) is used to investigate interface morphology between barrier metal and silicon junction.
3. Results and discussion Fig. 2 shows the variation of Nþ and Pþ contact resistances as a function of Ti thickness. The resistance is measured with 1000 contact arrays at
the aspect ratio of 7.8. It appears that Pþ contact resistance is more sensitive to Ti thickness. While the Nþ contact resistance increases from 300 to 400 X/contact, the Pþ contact resistance increases from 1000 to 4000 X/contact when Ti thickness Also, the standard decreases from 900 to 500 A. deviation increases with decreasing Ti thickness for both Pþ and Nþ contact resistances, however, the degree is much higher in Pþ contact. Therefore, it can be deduced from Fig. 2 that Pþ contact is very sensitive to Ti thickness and thus we focus to behavior of metal–Pþ contact resistance on process parameters.
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Fig. 2. A cumulative plot of metal–Nþ active contact resistance (a) and metal–Pþ active contact resistance (b) measured from 1 K contact array. Note that Ti thickness is varied while aspect ratio is 7.8.
Fig. 3. A cumulative plot of metal–Nþ active contact resistance (a) and metal–Pþ active contact resistance (b) measured from Kelvin resistor. Note that Ti thickness is varied while aspect ratio is 7.8.
For more detailed investigation of contact resistance on measurement condition, Kelvin pattern is also used. Note that, while Kelvin resistor gives contact resistance at the applied voltage of 1 V, contact array pattern gives contact resistance at very low voltage difference since adjacent contacts have similar potential. Fig. 3 shows the variation of Kelvin resistance of both Nþ and Pþ contacts as a function of Ti thickness. As mentioned, since Kelvin pattern is measured with directly applied voltage in contact, it gives lower contact resistance than that of chain pattern. However, the difference is much larger in Pþ contact resistance when the Fig. 3 is compared with Fig. 2. For example, when Kelvin pattern gives the Ti thickness is 500 A,
contact resistance of 850 X while chain pattern gives 4000 X. These results imply that current flow mechanism in Pþ contact is very much different depending on potential difference. Fig. 4 shows the variation of Pþ contact resistance as a function of aspect ratio at Ti thickness As shown, the contact resistance from of 900 A. Kelvin pattern is almost constant with increasing aspect ratio, while the contact resistance from chain pattern slightly increases. Therefore, it appears that contact resistance has a little dependency on aspect ratio when the Ti thickness is 900 This suggests that the enough Ti for reaction A. with silicon to make TiSi2 is deposited in the aspect ratio given in Fig. 4. Also, similar experiment
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Fig. 4. A variation of metal–Pþ contact resistance as a function Circle is of aspect ratio at constant Ti thickness of 900 A. contact resistance obtained from array pattern and triangle is contact resistance obtained from Kelvin resistor.
It is found is performed with Ti thickness of 500 A. that a little current flow occurs in Pþ contact when the aspect ratio is over 9.0. The contact resistance at this condition exceeds 15 KX/contact. This implies that enough TiSi2 layer for ohmic contact is not formed due to poor step coverage of Ti during sputtering deposition. Fig. 5 shows the TEM image at different Ti respectively, tathickness of 500, 700, and 900 A, ken with aspect ratio of 7.8. As shown, the shape and thickness of grown TiSi2 by the reaction between Ti and Si substrate are different depending on the deposited Ti thickness. It seems that the grown TiSi2 thickness increases with increasing deposited Ti thickness. However, more distinguishable result is a boundary shape between TiSi2 and Si substrate. The boundary is non-uniform at of Ti, however, it is rounded when Ti 500 A It becomes flat on the thickness increased to 700 A. These bottom side when Ti thickness is 900 A. results suggest that about 900 A Ti is necessary to grow uniform Ti silicide layer. To investigate voltage dependency of contact resistance, Kelvin resistor is used. Fig. 6 shows the result with different Ti thickness (Fig. 6(a)) and aspect ratio (Fig. 6(b)). As shown, contact resistance increases with decreasing bias voltage. In particular, this phenomenon is very large with Ti at aspect ratio of 8.5. It should thickness of 500 A
Fig. 5. TEM image of contact region at different Ti thickness: (a), 700 A (b), and 900 A (c). The aspect ratio is 7.8. 500 A
be noticed that the components of contact resistance can be divided into two parts. One is a Schottky barrier at the interface and the other is a spreading resistance due to the current crowding at the contact. Note that the Schottky barrier depends on the voltage difference across the contact
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in metal–semiconductor contacts are thermionic emission and carrier tunneling. In an ideal metal– semiconductor system, the potential energy barrier to the flow of charge carriers is primarily determined by the work-function difference between the metal and the semiconductor. In practice, however, the barrier height also varies as a function of electric field and impurity concentration at the interface. The characteristic of Schottky barrier height can be evaluated by Padovani and StrattonÕs theory. The details are given elsewhere [21]. Briefly, the current flow near zero bias voltage is given by 1=2 Ap1=2 E00 ðEB þ n2 Þ1=2 n 2 EB þ n 2 JS0 ¼ exp ; kT coshðE00 =kT Þ kT E00 ð1Þ
Fig. 6. The variation of contact resistance as a function of bias voltage in Kelvin resistor at constant aspect ratio of 8.5 (a) and (b). constant Ti thickness of 900 A
and the spreading resistance depends on the contact size and doping concentration. Hence, as the applied bias voltage is increased, contribution from Schottky barrier becomes negligible, and thus pure spreading resistance contributes to contact resistance. Fig. 6 shows that this value is 220 X regardless of Ti thickness and aspect ratio. Since the spreading resistance is constant, the increase of contact resistance at the low bias voltage is due to the increased Schottky barrier height. In Schottky barrier, carrier transport occurs four different mechanisms: thermionic emission over the potential barrier, carrier tunneling through potential barrier, carrier recombination and/or generation in the depletion region, and carrier recombination in the neutral region. Among them, the dominant factors of current flow
where JS0 is the saturation current without applied voltage, A is a classical Richardson constant, E00 is a constant related to barrier characteristic, EB is the Schottky barrier height, n2 is the energy of the Fermi level of the semiconductor measured with respect to the bottom of its conduction band, k is the Boltzmann constant, and T is a Kelvin temperature. Since E00 can be obtained from the logarithmic plot of the current density as a function of the applied voltage, the Schottky barrier (EB ) is calculated with Eq. 1. Fig. 7 shows the result. As shown, the EB increases with increasing aspect ratio and decreasing Ti thickness. EB is increased from 0.485 to 0.54 eV when the Ti thickness is at a constant aspect decreased from 900 to 500 A ratio of 6.7. When the aspect ratio is increased to 7.5, sharper increase in EB occurs with decreasing Ti thickness. Also, it appears that EB is dependent to aspect ratio at constant Ti thickness and the degree of variation strongly depends on Ti thickness. As shown, when the aspect ratio is increased from 6.7 to 7.5, EB is increased 1.05 times with Ti However, when the thickness thickness of 900 A. of Ti is 500 A, the increment is 1.1 times. These imply that the thickness of TiSi2 layer formed by the reaction between Ti and silicon plays important role on EB . Due to step coverage during Ti sputtering, longer deposition time and lower aspect ratio result in thicker TiSi2 layer. Indeed, TEM in Fig. 5 reveals that the thickness of TiSi2 on the bottom of contact hole is increased from
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shown, N d is varied within error boundary regardless of process conditions. Therefore, as a summary of the results from Figs. 7 and 8, it can be concluded that Ti thickness at the silicon surface is the major factor to affect on EB . A mathematical simulation is performed for more elaborated investigation of Schottky barrierÕs dependency to Ti thickness and aspect ratio. Fig. 9 shows the result. It reveals that a linear
Fig. 7. A plot showing Schottky barrier energy as a function of Ti thickness and aspect ratio.
when the Ti thickness is increased 450 to 700 A Jeon et al. [22] reported that from 500 to 900 A. TiSi2 could be either C49 or C54 phase depending on the TiSi2 thickness when the annealing temperature is about 650 °C. Since the annealing is performed at 650 °C during 10 min, the thicker TiSi2 layer might have more C54 phase which is thermodynamically stable. Note that resistivity of C54 is 15 lX-cm while resistivity of C49 is 60 lXcm [23]. One more important parameter on EB is the doping concentration at the interface between TiSi2 and silicon. It is shown that the doping concentration can be obtained from E00 by the following equation [21] rffiffiffiffiffiffiffiffiffiffiffiffi Nd 11 ½eV; ð2Þ E00 ¼ 1:85 10 er mr where Nd is the doping concentration at the TiSi2 / Si interface, er is relative dielectric constant of silicon, and mr is the effective tunneling mass measured in the unit of free electron mass. As mentioned earlier, E00 can be obtained from the logarithmic plot of the current density as a function of the applied voltage. Since er and mr are constants, N d can be calculated by Eq. (2). Fig. 8 shows the variation of N d as a function of barrier metal thickness at two different aspect ratios. As
Fig. 8. A variation of surface doping concentration as a function of Ti thickness at different aspect ratio.
Fig. 9. Shcottky barrier energy as a function of (Ti thickness)0:26 (aspect ratio)0:53 gives linear line.
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relationship is obtained among them and given by Schottky barrier energy ¼ (Ti thickness)0:26 (aspect ratio)0:53 . However, since the Ti thickness at the bottom of contact hole is determined by step coverage being varied with sputtering condition and machine, it should be noticed that the dependency of Schottky barrier energy on aspect ratio should be modified when a different deposition system is used. In this study, Ti deposition is performed by IMP (Ion Metal Plasma) Ti sputter system (Endura5500, AMAT). It appears that step coverage of Ti depends on aspect ratio. The step coverage is 18% with aspect ratio of 7.5 and 38% with aspect ratio of 4.2, respectively.
4. Conclusion In this paper, process optimization of deep metal to junction contact is performed. It appears that both Ti thickness and aspect ratio play important role on contact resistance. Especially, Pþ contact resistance is more sensitive to these parameters. Pþ contact resistance in contact array is increased from 1 to 4 KX per contact when Ti while Nþ thickness decreases from 900 to 500 A, contact resistance is just increased from 300 to 400 X. TEM image reveals that the degree of Ti silicidation depends on the Ti thickness. The boundary between silicon and TiSi2 is non-uniform with however, it becomes uniTi thickness of 500 A, form and flat with Ti thickness of 900 A. To investigate voltage dependency of contact resistance, both contact array and Kelvin resistor patterns are used. It appears that Schottky barrier plays major role at low voltage region, while the contact resistance approaches to 220 X at high voltage region regardless of process condition. The Schottky barrier increases with decreasing Ti thickness and increasing aspect ratio. Thermionic
emission model is used to evaluate Schottky barrier height. It appears that a relationship between Schottky barrier and process parameters is given by Schottky barrier energy ¼ (Ti thickness)0:26 (aspect ratio)0:53 .
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