- Email: [email protected]
Processor-processor communication
Processor- processor communicaUon Joe Gallacher discusses the use of byte oriented serial links in communicating between processors in multimicroprocessor systems
The ready availability of low cost processing power in the form of microcomputers has started a trend towards the use of loosely coupled multimicroprocessor industrial data acquisition and control systems. Relative to a centralized computer system, such distributed systems have the advantages of lower costs and greater security of operation of the plant. However, problems are introduced in transferring data between microcomputers of different configuration. These problems include protocol, transmission error detection and deadlock. In connecting microprocessors it is desirable to avoid excessive complexity and the need for special hardware for transmission and reception. It is becoming common to implement relatively low bandwidth links to transmit information from one system to another. These simpte links use standard input/output interfaces and the microcomputer configurations can be connected together with minimal disruption of hardware and software. This paper reviews the software engineering required to achieve communication over such a link, and considers the hardware necessary to construct the link. From the software point of view the simplest arrangement is the unidirectional transfer of data from one processor to another using a parallel connection which is handshaken at hardware level. However cost considerations preclude the use of parallel links except for very short distances, i.e. within a room. The distances involved in industrial plants will be hundreds of meters, and can be thousands of meters. This dictates the use of serial links and a software protocol which will support twoway communication. This places an emphasis on the software protocol to ensure that deadlocks are avoided.
An example of a loosely coupled distributed microcomputer system is shown in Figure I. In this system information is transferred from where it is gathered by the multiplexer microcomputer to where it is processed by the master microcomputer and to the man-plant interface at the console microcomputer. In addition there is a master microcomputer to console microcomputer link. The master microcomputer also has other data inputs and carries out process calculations. The function of the console is the
vol 3 no 7 september 79
r----'----I
Multiplexer ~
Inputs
Ana)ogue ~
ImlcrocomputerH
molt'P'exer ]..~_P~a~_
L
m~r~mpu~r~_
tl I Console Figure 1. Loosely coupled multimicrocomputer system selection and display of process values as required by the operator. Console displays are also initiated, modified and cancelled by the master microcomputer. The remainder of this paper will describe the communications protocol, software and hardware used in the master microcomputer to console microcomputer link. A byte oriented serial link is used and asynchronous transfer of information is achieved by arranging for both microcomputers to write into and read from a block of the console microcomputer memory.
BYTE ORIENTED
SERIAL
LINKS
Using a byte oriented serial link has the following advantages: •
Portability: using the byte instead of one of the computers word sizes means that either end of the link can be disconnected and connected to another machine with minimum disruption of hardware and software. • Maximum use of existing software: system routines will already exist to convert data in the file to and from character strings. • Ease of testing: one end of a link may be disconnected and connected to a visual display unit. Three fields are defined within the byte as follows:
LOOSELY COUPLED SYSTEMS
Praxis Instruments BV, Willem Barentszstraat I, Netherlands
I
I Master I microcomputerI_ I-
Loosely coupled distributed microcomputer systems require communication finks between different computer configurations. Byte oriented serial links provide a simple way of overcoming the problems of incompability between the computer configurations. The communications protocol, hardware and software for handling such links are discussed.
Leiden, The
7 FI
• •
6
,5
4
F2
3
2
I
0
F3
Field FI is the parity bit (b7) and should provide odd parity over the other seven bits. Field F2 is the identification field (b4-b6) and defines the contents of F3:
0141-9331/79/070317-04 $02.00 © IPC Business Press
317
Write Or clear
~
Master computer
Write: scan push buttonstate
Console
micr°compLrter
I
-I .Read: light or n I ~extinguish lamps, ~ __...~ set display values
Read
Figure 2. Transfer o f information using memory block Table 1. Parameter block format F1 Parameter 1 2 3 4 5 6
F2
F3
1 1 l 1 1 I
R/W/C Code GRP 1 GRP2 ENTRY NWRDS 1 NWRDS 2
if F2 = 3 then F3 = data if F2 = I then F3 = parameter if F2 -- 0 then F3 = control code •
Field F3 is the data/parameter/control field (b0- b3)
The format of the parameter block is fixed as shown in Table 1. •
•
•
Parameter 1 defines whether the master computer is sending data (code W) or receiving data (code R) or instructing the console to clear (code C) certain entries in the data block, i.e. set hexadecimal value F into that location. Parameters 2, 3 and 4 define the address in the console microcomputer memory block at which the operation should start. Parameters 5 and 6 define the number of consecutive entries in the console microcomputer memory block which must be read, written or cleared.
A list of control codes is given below: 1 2 3 4 5 6 7
= = = :: : --
SOH STX ETX EOT NAK ACK INT
CONSOLE
= = -= = = =
start of parameter block from master start of data block end of data block end of transmission negative acknowledgement acknowledgement interrupt
MEMORY
BLOCK
The state of each push button, indication lamp and digital display is stored in a memory block location as a hexadecimal code. The principle of information transfer using this memory block is shown in Figure 2. The console microcomputer scans the console push buttons and stores the state of each push button, or group of push buttons e.g, a decimal column, as a hexademical code [n a defined location in the memory block. The master computer writes
318
the required state of indication lamps into the memor!, block. The memory block is continually scanned b,/ tht: console microcomputer which then sets indication lamps and displays as required. It will be seen that the merher~ block is organized into a number of groups each of which contains a number of entries. Four bits (F3) of the bT'le are allocated to the parameter value. Examination el the pa., a., meter block shows that the organization oi riffs particular system permits up to FF groups each containing F entries. Each entry contains a hexadecimal code thus I:)ermi~fin~ the definition of 1 6 different states per ent;-~. Group 0 is used by the console microcompute~ when interrupts are generated to the master microcomputer. The master computer is thereiore not permitted to write into Group 0. Other groups are designated by the sv:~tem designer. Some examples of group entries are given m table 2.
PROTOCOL The protocol is based on a master-slave relationship. However this relationship is modified to take into account that the console microcomputer has certain tasks such as scanning the push buttons which must be accomplished within a defined time which could be upset by interrupt handling. The interrupt from the master computer it, handled by a very short routine which merely sets a flag. This flag is polled by the console microcomputer executive program. If the console microcomputer has information to transmit to the master microcomputer it transmits an INT
Table 2. Examples of group entries Group
Entry
Description
!
2
Function
6
A
Indication lamp communication fail
t
Header block 8
bytes
IP 0
INT
IP
0
SON
IP
I
W
I
GRP
[P
O
STX
Data block 3-19
[P
2
Data I
IP
ell temperature flow pressure level densiw ,fit ,~n stcad~ on f ash lg
4 F I 2
o '"ACK/NAK 1
i
0
ETX
IP
CHKSUM
IP
o
EOT
O
ACK --7
Q
ACK
o
ACK __3
I
t
IP
~ I P -=
i, n 2 Data
IP
[P
----[P
i CHKSUM
I
byies
F 0 i ,~~
~---[P
I
IP
Significance
~IP . . . .
[P
Value
~
l
[p
0 ACKINAK
O
ACK
O
ACK
P o IP IP
O O
I
i~
]
ACK I ACK/NAKI
Figure 3. WRITE operation ttom master compuZet
microprocessors and microsystems
code and stores the group entry location of the interrupting function in Group 0. The master microcomputer will deal with this request for an interrupt according to the priority of the task it is executing. An example of the protocol is shown in Figure 3 which describes a WRITE operation from the master computer. The master computer transmits an I NT code to the console microcomputer which sets a flag. On polling this flag the executive program will examine the received byte. If the received byte is not recognized as an INT code the console microcomputer responds with a N A K and the master computer will try again. If the received byte is recognized as an INT code the console microcomputer responds with an ACK and the master computer transmits an eight byte header block which consists of a SOH, six parameter bytes as already described, and a checksum byte. The hardware generates and checks for odd parity on each byte. Parity error on any byte in the block sets an error flag, as will checksum error on receipt of the complete header block. If the error flag has been set the console microcomputer will respond with a NAK to receipt of the header block. If the error flag has not been set the console microcomputer will respond with an ACK. In the latter case the master microcomputer will transmit the data block which consists of a STX, up to 16 words of data, an ETX and a checksum byte. The console microcomputer will respond with an ACK or NAK and receive an EOT. Transmission errors are examined by checking for parity error and checksum error. System errors are observed by checking that control codes, parameters and data are received at the correct place in the protocol and that the correct control codes are received. Theproblem of deadlock 'both listening', i.e. when each processor is waiting for a response from the other before sending, occurs whenever a command or an acknowledgement is missing. The problem is re~olved by the use of timeouts. The problem of deadlock 'both talking' is avoided in the system under consideration by the use of asynchronous duplex serial transmission. This is because neither processors' transmission of a byte is held up because the other is transmitting. The executive program ensures an orderly examination of the receive ready and transmit ready flags.
SO F T W A R E The flowchart of the console microcomputer executive program is shown in Figure 4. The executive program links together a number of major routines. After the power up/ reset initialization routines the executive loop commences with KBI N which inputs the sta.te of the console pushbuttons to the memory block. This is followed by LPDR which sets the indicator lamps and displays in accordance with the required states stored in the memory block. The interrupt from the master computer flag is then examined. If it is set R X D A T inputs the header and data blocks. If it is a READ operation T X D A T will transmit the required data to the master computer. If it is not a READ operation UPGRP will update the memory block as required by the master computer. In either case the program now loops back to examine the interrupt to master computer flag. This is the point in the program where the executive loop would be if there had been no interrupt from the master computer. If the interrupt to ma:ster computer flag has been set T X I N T transmits ~n interrupt request to the main computer, the MPX flag is then examined as it would
vol 3 no 7september 79
Cs -)
Z [ RXDATI N
TXI~T
i
Figure 4. Executive program flowsheet be if the interrupt to the master computer flag had not been set. MPDRV, the multiplexer driver routine, is called or not according to the state of the MPX flag and the executive program loops back to KBI N. Figure 5 shows the essential parts of the header block reception section of the RXDAT routine flowsheet in order to illustrate the operation of the time out and the transmission and system error handling. On entering the routine an ACK is sent to the master computer and the byte counter is set to zero. The first byte of the header block is then awaited. If it is not received within the time out period an EOT is transmitted to the master computer and the routine returns to the executive program. The received byte is examined to see if it is an EOT in which case the routine returns to the executive program. If the received byte is not an EOT it is loaded into the input buffer aod the byte counter is incremented. If the byte counter is not y e t equal to eight the error flag is examined. If the error flag has been set an ACK is transmitted to the master computer and the routine loops to input the next byte. If the error flag has not been set and the byte counter is equal to one the byte is examined to see if it is a SOH, i.e. the first byte of the header block. According to whether the byte is a SOH or not the error flag is set. An ACK is then sent to the master computer and the routine loops to input the next byte. Bytes 2 to 7 are examined to see if the error flag has been set and dealt with as previously described. In addition bytes 2 to 7 are examined to see if they are parameters. If they are not parameters the error flag is set. In either case an ACK is sent to the master computer and the next byte is input.
319
.... PT[M ......
f
I Byte counter =0
1 I !nterr LIF't r(i~21 J
_ i . . . . . . - 1 - .....
F_L_l DPCM tR)(-RDh7 z
u
Console
Seriol links to master computer and multiplexer
¥
Figure 6. Console microcomputer system modu/e layouz
L°~dtbyte.,u "x. _
/
input buffer
After the eighth and last byte has been received the error flag, the checksum flag, the correct code flag and the group entry validity flag are examined in order. An incorrect answer at any stage results in a NAK being transmitted to the master computer and the routine returning to the executive program. If the various conditions are satisfactory an ACK is transmitted to the master computer and the routine returns.
t
I Increment , byte counter
N
HARDWARE The hardware is implemented using standard system modules~ The console microcomputer system module layout is shown i Figure 6. These modules use LSI (large scale integrated) subsystem ICs (integrated circuits) The DPCM (dual peripheral communications module; provides interfaces for two duplex serial links i.e, the master computer link and the multiplexer link. The main component of the DPCM is the Intel 8251 Universal Synchronous/Asynchronous Receiver Transmitter (USART). This device is a programmable communication interface. It is software programmable. A mode instruction word defines such things as transmission rate, character length, parity generation and check, number of stop bits, etc. It is also possible to obtain by software a status word which gives information on parity error, state of transmit and receive buffers and so on. It also gives a number of status signals by hardware, these signals being brought out on the device's pins. RXRDY is such a signal and indicates that the receiver buffer is full. In the system being described this Facility is used in handling the interrupt from the master computer. The incoming byte containing the interrulSt code fills the receive buffer of the 8251 and sets RXRDY. This pin on the 8251 is connected to the interrupt logic on tile PTIM module. The interrupt logic signals an interrupt to the processor and jams a one byte call instruction on to the microcomputer system bus. This one byte call contains the start address of the interrupt service routine which sets d-m master computer interrupt flag.
Y
i,
l%rl
4
1
N
4
N
i
Y
/ Reception
of dote block
Figure 5. RXDA T t/owsheet
?20
NA
CONCLUSION This paper has described the use of simple byte oriented serial transmission links in loosely coupled distributed multimicroprocessor systems. It has dealt with questions of format, organization, protocol, transmission errors, software and hardware. A number of these links have been implemented and are operating satisfactorily in industrial environments.
microprocessbrs and microsystems
The ready availability of low cost processing power in the form of microcomputers has started a trend towards the use of loosely coupled multimicroprocessor industrial data acquisition and control systems. Relative to a centralized computer system, such distributed systems have the advantages of lower costs and greater security of operation of the plant. However, problems are introduced in transferring data between microcomputers of different configuration. These problems include protocol, transmission error detection and deadlock. In connecting microprocessors it is desirable to avoid excessive complexity and the need for special hardware for transmission and reception. It is becoming common to implement relatively low bandwidth links to transmit information from one system to another. These simpte links use standard input/output interfaces and the microcomputer configurations can be connected together with minimal disruption of hardware and software. This paper reviews the software engineering required to achieve communication over such a link, and considers the hardware necessary to construct the link. From the software point of view the simplest arrangement is the unidirectional transfer of data from one processor to another using a parallel connection which is handshaken at hardware level. However cost considerations preclude the use of parallel links except for very short distances, i.e. within a room. The distances involved in industrial plants will be hundreds of meters, and can be thousands of meters. This dictates the use of serial links and a software protocol which will support twoway communication. This places an emphasis on the software protocol to ensure that deadlocks are avoided.
An example of a loosely coupled distributed microcomputer system is shown in Figure I. In this system information is transferred from where it is gathered by the multiplexer microcomputer to where it is processed by the master microcomputer and to the man-plant interface at the console microcomputer. In addition there is a master microcomputer to console microcomputer link. The master microcomputer also has other data inputs and carries out process calculations. The function of the console is the
vol 3 no 7 september 79
r----'----I
Multiplexer ~
Inputs
Ana)ogue ~
ImlcrocomputerH
molt'P'exer ]..~_P~a~_
L
m~r~mpu~r~_
tl I Console Figure 1. Loosely coupled multimicrocomputer system selection and display of process values as required by the operator. Console displays are also initiated, modified and cancelled by the master microcomputer. The remainder of this paper will describe the communications protocol, software and hardware used in the master microcomputer to console microcomputer link. A byte oriented serial link is used and asynchronous transfer of information is achieved by arranging for both microcomputers to write into and read from a block of the console microcomputer memory.
BYTE ORIENTED
SERIAL
LINKS
Using a byte oriented serial link has the following advantages: •
Portability: using the byte instead of one of the computers word sizes means that either end of the link can be disconnected and connected to another machine with minimum disruption of hardware and software. • Maximum use of existing software: system routines will already exist to convert data in the file to and from character strings. • Ease of testing: one end of a link may be disconnected and connected to a visual display unit. Three fields are defined within the byte as follows:
LOOSELY COUPLED SYSTEMS
Praxis Instruments BV, Willem Barentszstraat I, Netherlands
I
I Master I microcomputerI_ I-
Loosely coupled distributed microcomputer systems require communication finks between different computer configurations. Byte oriented serial links provide a simple way of overcoming the problems of incompability between the computer configurations. The communications protocol, hardware and software for handling such links are discussed.
Leiden, The
7 FI
• •
6
,5
4
F2
3
2
I
0
F3
Field FI is the parity bit (b7) and should provide odd parity over the other seven bits. Field F2 is the identification field (b4-b6) and defines the contents of F3:
0141-9331/79/070317-04 $02.00 © IPC Business Press
317
Write Or clear
~
Master computer
Write: scan push buttonstate
Console
micr°compLrter
I
-I .Read: light or n I ~extinguish lamps, ~ __...~ set display values
Read
Figure 2. Transfer o f information using memory block Table 1. Parameter block format F1 Parameter 1 2 3 4 5 6
F2
F3
1 1 l 1 1 I
R/W/C Code GRP 1 GRP2 ENTRY NWRDS 1 NWRDS 2
if F2 = 3 then F3 = data if F2 = I then F3 = parameter if F2 -- 0 then F3 = control code •
Field F3 is the data/parameter/control field (b0- b3)
The format of the parameter block is fixed as shown in Table 1. •
•
•
Parameter 1 defines whether the master computer is sending data (code W) or receiving data (code R) or instructing the console to clear (code C) certain entries in the data block, i.e. set hexadecimal value F into that location. Parameters 2, 3 and 4 define the address in the console microcomputer memory block at which the operation should start. Parameters 5 and 6 define the number of consecutive entries in the console microcomputer memory block which must be read, written or cleared.
A list of control codes is given below: 1 2 3 4 5 6 7
= = = :: : --
SOH STX ETX EOT NAK ACK INT
CONSOLE
= = -= = = =
start of parameter block from master start of data block end of data block end of transmission negative acknowledgement acknowledgement interrupt
MEMORY
BLOCK
The state of each push button, indication lamp and digital display is stored in a memory block location as a hexadecimal code. The principle of information transfer using this memory block is shown in Figure 2. The console microcomputer scans the console push buttons and stores the state of each push button, or group of push buttons e.g, a decimal column, as a hexademical code [n a defined location in the memory block. The master computer writes
318
the required state of indication lamps into the memor!, block. The memory block is continually scanned b,/ tht: console microcomputer which then sets indication lamps and displays as required. It will be seen that the merher~ block is organized into a number of groups each of which contains a number of entries. Four bits (F3) of the bT'le are allocated to the parameter value. Examination el the pa., a., meter block shows that the organization oi riffs particular system permits up to FF groups each containing F entries. Each entry contains a hexadecimal code thus I:)ermi~fin~ the definition of 1 6 different states per ent;-~. Group 0 is used by the console microcompute~ when interrupts are generated to the master microcomputer. The master computer is thereiore not permitted to write into Group 0. Other groups are designated by the sv:~tem designer. Some examples of group entries are given m table 2.
PROTOCOL The protocol is based on a master-slave relationship. However this relationship is modified to take into account that the console microcomputer has certain tasks such as scanning the push buttons which must be accomplished within a defined time which could be upset by interrupt handling. The interrupt from the master computer it, handled by a very short routine which merely sets a flag. This flag is polled by the console microcomputer executive program. If the console microcomputer has information to transmit to the master microcomputer it transmits an INT
Table 2. Examples of group entries Group
Entry
Description
!
2
Function
6
A
Indication lamp communication fail
t
Header block 8
bytes
IP 0
INT
IP
0
SON
IP
I
W
I
GRP
[P
O
STX
Data block 3-19
[P
2
Data I
IP
ell temperature flow pressure level densiw ,fit ,~n stcad~ on f ash lg
4 F I 2
o '"ACK/NAK 1
i
0
ETX
IP
CHKSUM
IP
o
EOT
O
ACK --7
Q
ACK
o
ACK __3
I
t
IP
~ I P -=
i, n 2 Data
IP
[P
----[P
i CHKSUM
I
byies
F 0 i ,~~
~---[P
I
IP
Significance
~IP . . . .
[P
Value
~
l
[p
0 ACKINAK
O
ACK
O
ACK
P o IP IP
O O
I
i~
]
ACK I ACK/NAKI
Figure 3. WRITE operation ttom master compuZet
microprocessors and microsystems
code and stores the group entry location of the interrupting function in Group 0. The master microcomputer will deal with this request for an interrupt according to the priority of the task it is executing. An example of the protocol is shown in Figure 3 which describes a WRITE operation from the master computer. The master computer transmits an I NT code to the console microcomputer which sets a flag. On polling this flag the executive program will examine the received byte. If the received byte is not recognized as an INT code the console microcomputer responds with a N A K and the master computer will try again. If the received byte is recognized as an INT code the console microcomputer responds with an ACK and the master computer transmits an eight byte header block which consists of a SOH, six parameter bytes as already described, and a checksum byte. The hardware generates and checks for odd parity on each byte. Parity error on any byte in the block sets an error flag, as will checksum error on receipt of the complete header block. If the error flag has been set the console microcomputer will respond with a NAK to receipt of the header block. If the error flag has not been set the console microcomputer will respond with an ACK. In the latter case the master microcomputer will transmit the data block which consists of a STX, up to 16 words of data, an ETX and a checksum byte. The console microcomputer will respond with an ACK or NAK and receive an EOT. Transmission errors are examined by checking for parity error and checksum error. System errors are observed by checking that control codes, parameters and data are received at the correct place in the protocol and that the correct control codes are received. Theproblem of deadlock 'both listening', i.e. when each processor is waiting for a response from the other before sending, occurs whenever a command or an acknowledgement is missing. The problem is re~olved by the use of timeouts. The problem of deadlock 'both talking' is avoided in the system under consideration by the use of asynchronous duplex serial transmission. This is because neither processors' transmission of a byte is held up because the other is transmitting. The executive program ensures an orderly examination of the receive ready and transmit ready flags.
SO F T W A R E The flowchart of the console microcomputer executive program is shown in Figure 4. The executive program links together a number of major routines. After the power up/ reset initialization routines the executive loop commences with KBI N which inputs the sta.te of the console pushbuttons to the memory block. This is followed by LPDR which sets the indicator lamps and displays in accordance with the required states stored in the memory block. The interrupt from the master computer flag is then examined. If it is set R X D A T inputs the header and data blocks. If it is a READ operation T X D A T will transmit the required data to the master computer. If it is not a READ operation UPGRP will update the memory block as required by the master computer. In either case the program now loops back to examine the interrupt to master computer flag. This is the point in the program where the executive loop would be if there had been no interrupt from the master computer. If the interrupt to ma:ster computer flag has been set T X I N T transmits ~n interrupt request to the main computer, the MPX flag is then examined as it would
vol 3 no 7september 79
Cs -)
Z [ RXDATI N
TXI~T
i
Figure 4. Executive program flowsheet be if the interrupt to the master computer flag had not been set. MPDRV, the multiplexer driver routine, is called or not according to the state of the MPX flag and the executive program loops back to KBI N. Figure 5 shows the essential parts of the header block reception section of the RXDAT routine flowsheet in order to illustrate the operation of the time out and the transmission and system error handling. On entering the routine an ACK is sent to the master computer and the byte counter is set to zero. The first byte of the header block is then awaited. If it is not received within the time out period an EOT is transmitted to the master computer and the routine returns to the executive program. The received byte is examined to see if it is an EOT in which case the routine returns to the executive program. If the received byte is not an EOT it is loaded into the input buffer aod the byte counter is incremented. If the byte counter is not y e t equal to eight the error flag is examined. If the error flag has been set an ACK is transmitted to the master computer and the routine loops to input the next byte. If the error flag has not been set and the byte counter is equal to one the byte is examined to see if it is a SOH, i.e. the first byte of the header block. According to whether the byte is a SOH or not the error flag is set. An ACK is then sent to the master computer and the routine loops to input the next byte. Bytes 2 to 7 are examined to see if the error flag has been set and dealt with as previously described. In addition bytes 2 to 7 are examined to see if they are parameters. If they are not parameters the error flag is set. In either case an ACK is sent to the master computer and the next byte is input.
319
.... PT[M ......
f
I Byte counter =0
1 I !nterr LIF't r(i~21 J
_ i . . . . . . - 1 - .....
F_L_l DPCM tR)(-RDh7 z
u
Console
Seriol links to master computer and multiplexer
¥
Figure 6. Console microcomputer system modu/e layouz
L°~dtbyte.,u "x. _
/
input buffer
After the eighth and last byte has been received the error flag, the checksum flag, the correct code flag and the group entry validity flag are examined in order. An incorrect answer at any stage results in a NAK being transmitted to the master computer and the routine returning to the executive program. If the various conditions are satisfactory an ACK is transmitted to the master computer and the routine returns.
t
I Increment , byte counter
N
HARDWARE The hardware is implemented using standard system modules~ The console microcomputer system module layout is shown i Figure 6. These modules use LSI (large scale integrated) subsystem ICs (integrated circuits) The DPCM (dual peripheral communications module; provides interfaces for two duplex serial links i.e, the master computer link and the multiplexer link. The main component of the DPCM is the Intel 8251 Universal Synchronous/Asynchronous Receiver Transmitter (USART). This device is a programmable communication interface. It is software programmable. A mode instruction word defines such things as transmission rate, character length, parity generation and check, number of stop bits, etc. It is also possible to obtain by software a status word which gives information on parity error, state of transmit and receive buffers and so on. It also gives a number of status signals by hardware, these signals being brought out on the device's pins. RXRDY is such a signal and indicates that the receiver buffer is full. In the system being described this Facility is used in handling the interrupt from the master computer. The incoming byte containing the interrulSt code fills the receive buffer of the 8251 and sets RXRDY. This pin on the 8251 is connected to the interrupt logic on tile PTIM module. The interrupt logic signals an interrupt to the processor and jams a one byte call instruction on to the microcomputer system bus. This one byte call contains the start address of the interrupt service routine which sets d-m master computer interrupt flag.
Y
i,
l%rl
4
1
N
4
N
i
Y
/ Reception
of dote block
Figure 5. RXDA T t/owsheet
?20
NA
CONCLUSION This paper has described the use of simple byte oriented serial transmission links in loosely coupled distributed multimicroprocessor systems. It has dealt with questions of format, organization, protocol, transmission errors, software and hardware. A number of these links have been implemented and are operating satisfactorily in industrial environments.
microprocessbrs and microsystems