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Microprocessors and Microsystems 21 (1997) 249-256

PROTOS A microcontroller/FPGA-based prototyping system for embedded applications Zoran Salcic* Auckland University, Department of Electrical and Electronic Engineering, 20 Symonds St., Auckland, New Zealand Received 27 January 1997; received in revised form 17 July 1997; accepted 17 July 1997

Abstract

Embedded applications usually require the use of standard microcomputers and customized interfaces. Performance of the computers often can not meet the requirement of the intended application. Combination of a standard microcontroller and a Field-Programmable Gate Array (FPGA) may lead to the solution in both prototyping systems and target, operational systems. In this article we describe a microcontrolleff FPGA-based prototyping system, called PROTOS, which provides a flexible and effective hardware/software co-design environment for embedded applications. The PROTOS is using software and hardware development tools present on a standard PC Windows platform. It also extends their capabilities enabling more flexible use of both implementation technologies and their combinations by employing flexibility of software and reconfigurability of FPGAs. © 1997 Elsevier Science B.V.

Keywords: Microcontroller; FPGA; Prototyping; Embedded system; Hardware/software co-design

I. Introduction

FPGAs have become one of the prevailing implementation technologies for complex digital systems in both prototyping and operational systems [1]. Very often they are used as a sort of coprocessor for existing processors, for example as the PC-bus add-on boards, or the boards for the other bus types [2,3] with the aim of accelerating some of the time-critical operations. Another typical use is in various sorts of custom-computing systems, in which the whole computational device is customized and implemented in FPGA [4-6]. Such systems are very interesting for embedded applications because they can be optimized in terms of used hardware resources. Embedded applications often require partitiening a solution into hardware and software implementation parts. The boundary between hardware and software is usually pretty soft allowing more or less of the solution to be implemented by programs or by pure hardware. The price and performance requirements represent major criteria to chose between hardware and software implementation of the solution. Standard single-chip microcomputers often suffice

* E-mail: [email protected],nz 0141-9331/97/$17.00 © 1997 Elsevier Science B.V. All rights reserved PII S 0 1 4 1 - 9 3 3 1 ( 9 7 ) 0 0 0 4 1 - 0

application requirement, and only software has to be developed for a given application. If additional hardware interfacing is required, it is usually implemented using standard specialized chips, or using general MSI/SSI chips. This leads to a fixed solution that can not be altered without PCB redesign. Field-Programmable static RAM based Gate Arrays offer easy reprogrammability and change of the function without change of the PCB design using simple downloading of a new bitstream representing new circuit design. The feature of dynamic reconfigurability can be further used to dynamically change the function of an FPGA in a time-multiplexed manner. By connecting standard microcontroller with an FPGA, a highly flexible system, which allows different partitioning lines to draw between software and hardware becomes feasible. It also represents a frst-stage testbed for experimenting with methodologies for hardware/software co-design [2] for a class of embedded applications. In this article we describe PROTOS, a microcontroller/ FPGA-based system for prototyping of embedded applications. It consists of a standard Motorola 68HC 11 microcontroller and one or more Altera FLEX 8000 FPGAs, as well as additional SRAM and EEPROM resources to accommodate a fairly wide class of embedded applications. The development tools which can be used for both software

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and hardware development for the system run on a PC with the Windows environment. They contain standard suit of programming languages and compilers for 68HC11, complete integrated hardware design environment for FPGAs, as well as additional software which facilitates the use of all resources in the system in both development and run-time stages. In the following sections we first describe the overall system features and environment in which it is used. Then, we present hardware designs for the system, modes of operation and software features from the user point of view. Finally, two application examples show how easily system can be used in a typical embedded application. The implemented, first generation of the protyping system contains one or two FPGAs, though the design is ready to accommodate more FPGA chips when needed.

2. The PROTOS framework In order to use capabilities and advantages of both microcontrollers, with their standard interfacing and programming resources, and FPGAs, with their flexibility to implement additional hardware structures for interfacing or improvement of computational performance, we have set a number of current system objectives the PROTOS system should fulfil. These objectives are presented and briefly discussed later. Some other long-term objectives are discussed in the conclusion. 2.1. Prototyping and run-time environment The system should provide a platform for development of embedded applications that require not only application software but also hardware customized according to application requirements. The system has to provide easy and fast modification of both application programs and hardware structures associated to the standard microcontroller not only during prototyping process, but also in the working, operational system, without new hardware (for example, PCB re-design) interventions. Feasible interventions are mostly in the form of change of EEPROM contents in order to supply new versions of programs and/or hardware interfaces or other hardware structures. These hardware structures are represented by bitstreams, which are the result of hardware design process and are stored in EEPROM or SRAM before downloaded into an FPGA. 2.2. Standard microcontroller A Motorola 68HC 11 [9] microcontroller was selected as a standard, providing a powerful 8-bit microprocessor with a rich instruction set and programming model, parallel and serial ports for interfacing, timers, and multichannel A/D converter.

2.3. Standard FPGA chip A standard Altera FLEX 8000 [7] chip is used as a major resource for implementation of application-specific hardware structures, which are a part of embedded system solution. In our case we decided to implement a PCB with a FLEX8282-84 devices, but it can be easily modified to accommodate any other FPGA from the FLEX 8000 family because they have the same architecture and reconfiguration mechanism. 2.4. Memory Existing 68HC 11 on-the-chip memory resources are not sufficient for most of intended applications. This was the reason for using the microcontroller in the expanded bus mode, and extend memory resources with external 8KB of SRAM and 32KB of EEPROM. Larger memory resources are needed to store programs and data, but also to store hardware configurations that are implemented in the FPGA chip. 2.5. Serial communication link A serial communication link is needed to provide communication with a personal computer, which is used as a software/hardware development platform. It enables both programs which run on the microcontroller and hardware configurations from the PC to the prototyping board to be downloaded. It can also be used in the target application. 2.6. Simple input/output devices for testing purpose In order to provide flexibility for system operation, different options, and to indicate the current state of the system a number of input switches, which are switched on or off manually, and a number of led indicators are provided. 2.7. System clocks The PROTOS system provides two system clocks. One is used to drive the microcontroller at 2 MHz, and the other one to drive sequential circuits, which are implemented in the FPGA at higher frequencies (up to 50 MHz in our case). 2.8. Access to the FPGA through memory-mapped I/0 As the 68HCll supports memory-mapped I/O, our decision was to extend this I/O method to the FPGA. This enables access to the FPGA resources through a number of registers, implemented in an EPLD, that appear in the address space of the 68HC 11. However, this does not prevent a user to implement more registers within the FPGA, as an application requires.

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Operational(embedded)system Fig. 1. Prototypingsystemenvironment. 2.9. Access to the external signals The FPGA itself provides a number of applicationspecific input/output ports, which are connected to a connector and can be used to interconnect prototyping system with the external signals. Minimum number of these signals is 43, and if a larger number has to be accessed we have to use an FPGA chip with larger number of user input/output pins.

2.10. Modes of operation Prototyping board supports two basic modes of operation. 1. Configuration mode in which hardware configuration of the FPGA is being downloaded. This mode is entered always at the system power-up or system initialization whenever a new configuration has to be downloaded from memory or from the host development PC. 2. System operation (or user) mode, in which prototyping system carries out presumed function in embedded system.

2.11. Hardware reconfiguration Hardware reconfiguration is performed in a passive parallel reconfiguration asynchronous scheme [8]. It means that reconfiguration process is controlled by the 68HC11 as a host, which finds configuration bitstream in external memory (SRAM or EEPROM) and downloads it into the FPGA using appropriate control signals of FLEX8000 device. One configuration bitstream for FLEX8282 device requires 5KB of memory space, so several configurations can be stored at the same time in memory chips. This further allows dynamic reconfiguration of hardware in some embedded applications at a fairly high rate. The other type of reconfiguration is available during prototyping process. Under software control, a configuration bitstream can be downloaded directly from the host PC to the FPGA. The overall structure of the prototyping environment is presented in Fig. 1. As the Figure shows, the prototyping board is placed between the PC, which is used as software/ hardware development environment, and the target system, which is controlled/supervised by prototyping system. Once

the application is finalized, an operational (embedded) system is used without development environment. The system yet gives another possibility and degree of flexibility. It can be modified and changed remotely, using instead of standard RS232 serial link, a modem link on both ends, of the PC and of the prototyping board. This means that both modifications of system's software and hardware can be performed without any rewiring. The structure of the hardware of the prototyping board is presented in Fig. 2. As the 68HCll must be used in expanded bus mode, proper address/data bus demultiplexing and mapping of the FPGA resources into the 68HCll address space must be provided. It is all done in an Altera EPLD (MAX7096) which in fact extends original 68HC11 capabilities and resources enabling simple addition of the other resources such as memories or FPGA chips. The current version of the design supports multi-FPGA structure, so the board can easily accommodate more than one FLEX8000 chips. In its current form, the PROTOS environment supports development of programs using a number of crosscompilers/assemblers/simulators for 68HC11, which run under MS Windows. Object code can be downloaded into the SRAM or EEPROM by software residing in EEPROM, and, then executed. If needed, a more complex monitor, like Motorola Buffalo monitor, can be stored in EEPROM, as well. Besides programs, EEPROM is used to store hardware configuration bitstreams that represent different hardware designs that can be downloaded into FLEX 8000 device. Downloading program supports selection of the configuration, which will be downloaded, or automatically downloads configuration indicated by the set-up of the input switches. Any user program can use a system provided subprogram to download a selected configuration, effectively supporting dynamic reconfiguration. Starting address of a configuration file in either EEPROM or SRAM is an input parameter to this subprogram. Hardware design is supported by Altera Max + Plus II design environment. As a result of design process and compilation of the design entry file, a bitstream file is produced and stored on the hard disk. It can be downloaded and stored into any of the PROTOS memories. Starting address to which configuration bitstream is downloaded is defined by a designer, and subsequently used during configuration

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process. Hardware design entry may be performed by a number of entry tools supported by Max + Plus II, namely VHDL, AHDL (which stands for Altera Hardware Description Language), graphic design entry, or imported from another design tools [7]. Prototyping program and design development, as well as the manipulations with the object program files and bitstream configuration files are illustrated by design process flow given in Fig. 3.

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operated in the expanded bus mode in order to address external memories and the FPGA. In this mode, port B becomes the address bus upper byte. Port C becomes the multiplexed bus of address lower byte and data. Together with the signals R/W, AS and CLK, these lines are connected to the EPLD MAX7096. They are used to control the other components such as the memory chips. The 68HCll is connected to a PC through the built-in serial communication interface (SCI) in port D and an RS232 interface. The SCI uses bits 1 and 0 of port D to transmit and receive data to and from PC. The remaining bits in port D are connected to the 4 single-bit switches. Two pins from port A are used to capture the control signals from the FLEX8282 during configuration. The rest of the pins in port A and port E are connected to an external connector. The users can make use of the timer system in port A or the A/D converter in port E in their applications. However,

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Z. Salcic/Microprocessorsand Microsystems21 (1997) 249-256 these ports can also be used as general purpose I/Os. The IRQ line is also connected to the external connector so user can connect external devices that generate interrupts. 3.2. EPLD MAX7096 The EPLD MAX7096 interconnects the 68HCll and the FPGA and other components on the board. This EPLD receives the address, data and other control signals such as R/W and AS from the 68HCll. The main function of this chip is to decode the address from 68HC 11 to enable the EPROM, RAM or one of six internal registers. It also demultiplexes the lower byte address and data from the 6811. The six internal registers in EPLD are used as buffers when the 68HC11 communicate with the FLEX8282 and the LED circuitry. These registers appear in the address space of the 68HC11 providing easy use by user programs. 3.3. FPGA FLEX 8282 The FLEX8282-84 is the lowest-capacity device in the Altera FLEX8000 family. There is a total of 208 logic elements in the device, and together with input/output blocks, there are 282 flip-flops available to the users. The whole device is equivalent to 2500 usable two-input logic gates to implement logic functions. The device has 84 pins. It uses a number of pins to connect to other devices on the prototyping board. There are 43 pins left unused. All these pins are connected to I/O connectors on the board. The users can use them for input and output purposes in their applications. There are two clock sources provided on the prototyping board. One of the clocks is from 68HC11 and runs at 2 MHz. The other source is the user clock. The user can plug in a separate clock to change the operating frequency of the FPGA. The users can select the clock source by using a fifth jumper on the prototyping board. 3.4. Led circuitry The LED circuitry contains five LEDs. They can be used for any purpose to display the status of the board. For example, they can be used to indicate which set of configuration data is currently downloaded to the FPGA. 3.5. Reset circuitry The Reset circuitry is designed such that the operation of the 68HC 11 will be delayed by about half a second when the board is powered up. This ensures the power supply has reached a stable value of 5 V. This delay only occurs when the board is powered up, but does not occur during normal reset.

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4. Modes of operation and user view The PROTOS board can be used in two operation modes: configuration and user mode, depending on the status of the FLEX8282 device. All other components on the board are used in the same way in both operating modes. 4.1. Configuration mode The FLEX8282 is configured using passive parallel asynchronous (PPA) scheme [8]. The 68HC11 reads configuration bitstream from the EEPROM and transfers it to the FPGA. The control signals are generated by a configuration program and transferred to the FPGA through registers implemented in MAX7096. Status signals are transferred from FLEX8282 to the 68HCll through another status registers or directly through the 68HC11 port A. Transfer of individual configuration bytes is carried out asynchronously using simple program controlled handshaking. The data for configuring the FLEX8282 in the PPA scheme is stored in Raw Binary File which is generated by Max + Plus II compiler. It has a fixed size of 5120 bytes for any design using FLEX8282. The program for configuring the FLEX8282 was written as a subroutine for 68HC11. It implements all timing and other requirement for configuration protocol. The user can start the configuration process at any time by calling this subroutine. In this way, in-circuit reconfiguration is performed. The subroutine is located in EEPROM at fixed location. Actual configuration data set is selected by passing its starting address to this subroutine. 4.2. User mode After the FLEX 8282 was configured properly, the PROTOS board enters the user mode. Except dedicated pins, all other pins used by the FLEX8282 for configuration are now used for communication between the 68HC11 and the FPGA. Data transfers between 68HC11 and FLEX8282 are achieved using two 8-bit registers implemented in MAX7096. Other register implemented in MAX7096 controis the FLEX8282 lines. The user can make use of bit 2 of input port A, PA2, as of input capture input to generate interrupt in the 68HC11 if necessary. 4.3. PROTOS memory map The memory map is important for both hardware and software design. The global memory map is shown in Fig. 4, without presenting the details of EEPROM map. All internal 68HC 11 RAM and control registers are left at their default locations without remapping. Registers Reg 1-6 are implemented in MAX7096 and appear in the 68HC11 address space. The external RAM is placed at addresses $2000 to $3FFF, while external EEPROM is placed at addresses $8000 to $FFFF. The internal 68HC11 EEPROM

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5. Application examples

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Two examples that illustrate the use of prototyping system are briefly presented in this section. The first one is a classical example of a traffic light controller that is implemented by a number of different hardware designs, which are activated at different times of the day or depending on the current traffic conditions. In the second example the FPGA chip is used as a kind of coprocessor to the 68HC 11 to perform direct digital synthesis of two sinusoidal waveforms that are used to modulate an input data stream generated by program. The program sets requirements on the frequencies with which 0 and 1 values of the data stream are modulated.

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is disabled by software. In the user mode some of the port A and B input and output pins are available to the user.

4.4. Clocks The globe clock pin of the FLEX8282 is connected to the E-clock pin of the 68HC 11. However, the FLEX8282 can operate at a much higher clock frequency than the 68HC11. Therefore, a clock socket is reserved on the prototyping board to allow the user to use a higher clock frequency for the FLEX8282. A jumper is used to switch between E-clock and user-supplied clock.

4.5. Other software support The PROTOS board can be connected to the host PC by using SCI port of the 68HC11 and RS-232 interface on the board. Two basic system subroutines are written that transmit and receive data from the PC and are stored in the EEPROM. The subroutine to receive data stores them in the external SRAM. If this data, for instance, is a configuration bitstream for the FPGA, the user can configure the FPGA using configuration subroutine subsequently. Also, user can reprogram EEPROM if new configuration will be needed during the later development. The transmitting subroutine is used to transmit a string to the PC. It is useful when the user wants to display messages on the PC screen to show the status of the protyping board, transfer results of its operation, etc.

The light pattern of a typical traffic light at an intersection changes according to the time of the day or the day in the week as the traffic varies. To implement a traffic light controller, one of the ways is to use a finite state machine. The whole implementation is illustrated in Fig. 5. The finite state machine can be easily specified in HDL and implemented in a FPGA. To display different light patterns for different traffic conditions, several finite state machines are designed and stored in EEPROM. The time between transitions of traffic is stored within registers/timers implemented in the FPGA. The times can be changed by microcontroller, which monitors traffic conditions and communicate with the higher hierarchical level in the traffic control. The 68HC11 program reconfigures FPGA accordingly. It also enables a completely new configuration, not present in EEPROM, to be received from a remote place, and in SRAM, and activated when needed. The entire reconfiguration process of the FPGA is finished within 100 ms. During this process all inputs and outputs from the FPGA are disabled, and all traffic lights brought to a safe state. This example shows how software/hardware partitioning and co-design is achieved. The hardware part of the solution, represented by the finite state machine and a number of registers/timers that are 'hard core' of the solution, is implemented in the FPGA. The main reason for this is because finite state machine can be easily synthesized in FPGA and provides reliable and robus part of solution, which does not change during its operation, however, global timing and control is provided software, which can easily perform reconfiguration control. The high degree of flexibility in the design is achieved because both software and hardware can be used to implement the application. Designing various hardware solutions we have proved that device of the low-cost flex8282 can accommodate solution for any traffic conditions.

5.2. Direct digitial signal synthesis This example illustrates a different use of FPGA. The whole application provides direct digital synthesis of

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the look-up table in which sine waveform patterns are stored. The output from the FPGA is 8-bit data that represents the value of the generated output sine waveform. For the situations when up to 64 sample values are sufficient to represent generated signal, the whole design, including the look-up table, can be implemented in the FPGA. The lookup table is implemented as an ordinary combinational circuit specified by truth table in HDL. If a higher number of samples is used to represent generated signal, external memory can be used to implement look-up table.

implement various interfaces on the time-multiplexed basis without having to change physically the hardware of the board. The board can be used as both prototyping one and the board in the working embedded system.

Acknowledgements The author acknowledges his former students Dong Hui and Peter Ling for contributing to the first implementation of the PROTOS board and software environment.

6. Discussion and conclusion In this article we presented the PROTOS prototyping system that is aimed at the development of embedded applications which require both microcontroller and external logic resources for implementation. The 68HCll microcontroller and additional equivalent of 5 000 usable gates are available for application development. The power of both technologies can be used efficiently to demonstrate not only reprogrammability of a microcontroller, but also the reconfigurability of hardware. Current implementation of PROTOS is using only one FLEX8282 FPGA, but it is ready to accommodate multiple FPGAs. It does support the access to the external memories from the microcontroller, but direct memory access from the FPGA is not provided. The major reason for this is the limited number of user pins on FPGA chip, which would be further reduced if direct memory access from FPGA were provided. As such, PROTOS is more suitable for applications with high interfacing requirements and lower memory access requirements. However, if the overall system has lower number of outputs, as in the case of direct digital synthesis, external memory can be controlled by FPGA as well. Configuration process of FPGA can be started at any time, and it is under full program control. It requires 5 KB to be transferred from the external memory into FPGA. In some applications, regardless of relatively slow speed, dynamic in-circuit reconfiguration is feasible. Software support for the PROTOS board in the implemented system is rudimentary consisting of the library of low-level subroutines, which can be linked to the application program, and will be expanded to integrate the whole development environment more tightly. The board was used successfully to design various custom-configurable solutions, of which two are presented briefly in this article. Four sets of configuration data can be stored in the EEPROM on the PROTOS board. They can be used to

References Ill Z. Salcic, FPGAs and CPLDs--a challenge for complex digital system design, IPENZ '97 Conference (to be published), Wellington, February 1997. [2] S. Guccione, List of FPGA-based computing machines, http:// www.io.com/~ guccione/HW-list.html. [3] S.H.M Ludwig, The design of a coprocessor board using Xilinx's XC6200 FPGA--An experiment report, FPL '96, Darmstadt, also Lecture Notes in Computer Science, Springer, 1996. [41 Z. Salcic, B. Maunder, CCSimP--An instruction-level customconfigurable processor for FPLDs, FPL '96, Darmstadt, also Lecture Notes in Computer Science, Springer, 1996. [5] M.J. Wirthlin, B.J. Hutchings, A dynamic instruction set computer, IEEE Symp. on FPGAs for Custom Computing Machines, 1995. [6] R. Hartenstein, J. Becker, R. Kress, Custom computing machines vs. hardware/software co-design: From globalized point of view, FPL '96, Darmstadt, also Lecture Notes in Computer Science, Springer, 1996. [7] Altera Data Book, Altera Corporation, March 1995. [8] Configuring FLEX8000 Devices, Altera Corporation, May 1994. [9] Motorola M68HCI 1 Reference Manual, Prentice-Hall, 1988. Z. Salcic was born in Sarajevo, Bosnia and Herzegovina, in 1950. He received his" B.E., ~~

ing from Sarajevo University in 1972, 1974 and 1976, respectively. The part of his graduate work he did at the City College of the City University in New York was in 1974 and 1975. He worked as an assistant professor, and associate professor at the Sarajevo Universio, and Czech Technical University, Prague. Between 1985 --and 1990 he was deputy and then CEO of the Institute for Computer and Information Systems ~[' Energoinvest Corporation, Sarajevo. He has been at the Universi~' of Auckland since 1994. He has published over 70 technical papers, numerous technical reports" and four books. His current research interests are custom-computing machines, field-programmable logic and its applications in embedded and reconfigurable systems, complex digital systems design, automatic vehicle tracking, and applications ~?ie mobile computing. ,