Pseudo-differential second-order band-reject filter using current conveyors

Accepted Manuscript Title: Pseudo-differential second-order band-reject filter using current conveyors Author: id="aut0005" orcid="0000-0003-4263-5875" > Jaroslav Koton id="aut0010" orcid="0000-0002-9504-2275" > Norbert Herencsar id="aut0015" > Ondrej Sladok id="aut0020" > Jiun-Wei Horng PII: DOI: Reference:

S1434-8411(16)30078-4 http://dx.doi.org/doi:10.1016/j.aeue.2016.03.009 AEUE 51587

To appear in: Received date: Revised date: Accepted date:

27-7-2015 26-1-2016 15-3-2016

Please cite this article as: Jaroslav Koton, Norbert Herencsar, Ondrej Sladok, JiunWei Horng, Pseudo-differential second-order band-reject filter using current conveyors, (2016), http://dx.doi.org/10.1016/j.aeue.2016.03.009 This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

Pseudo-differential second-order band-reject filter using current conveyors Jaroslav Kotona,∗, Norbert Herencsara , Ondrej Sladoka , Jiun-Wei Horngb of Telecommunications, Brno University of Technology, Technicka 3082/12, 616 00 Brno, Czech Republic b Department of Electronic Engineering, Chung Yuan Christian University, Chung-Li, 32023, Taiwan

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a Department

Abstract

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A voltage-mode high input impedance differential input-differential output second-order band-reject filter based on two differential difference current conveyors (DDCCs) and one second-generation current conveyor (CCII) is presented. The proposed structure features high input impedance, a minimum number of passive elements - all being grounded, high common-mode rejection ratio, and low sensitivity. The tracking error and sensitivity analysis of the proposed circuit are given. The performance of the filter structure is verified by simulations and also experimentally measured using the UCC-N1B integrated circuit.

1. Introduction

an AC coupled second-order low-pass filter was presented by Alzaher et al. [7], where the fully differential secondgeneration current conveyor (FDCCII) and ten passive elements have been used. Also Al-Shahrani [8] employs three FDCCIIs and together with four resistors and two capacitors obtains second-order low-pass and band-pass frequency responses. Ibrahim et al. [9] present a KerwinHuelsman-Newcomb (KHN)-equivalent voltage-mode biquad that uses three dual output differential difference current conveyors (DO-DDCCs) and seven passive elements, whereas the low-, band- and high-pass response can be obtained simultaneously. Similarly, Beg et al. [10] proposed fully differential biquadratic filter operating in both voltage- and transadmittance-modes simultaneously. The proposed circuit is based on five digitally current controlled differential voltage current conveyor (DCCDVCC) and three passive components in floating form. Usefulness of the recently introduced current differencing current conveyor (CDCC) in pseudo-differential filter design is investigated by Singh and Kumar in [11]. The proposed current-mode filter employs excessive number of CDCCs and passive components, i.e. seven and ten, respectively. On the other hand, the circuit allows independently tunable gain, bandwidth, and pole frequency simultaneously. In practice, typical application of band-reject (or notch) filter is in biopotential signal processing systems, where it serves as powerline interference unit [25]. To the best knowledge of the authors, the only solution providing a second-order band-reject frequency response has been presented by Ibrahim et al. [12]. In [12] only single differential voltage current conveyor (DVCC) is used, however, the proposed structure uses excessive number of floating passive elements and furthermore component matching is required. Other circuit solutions of differential first-order

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In analog circuit design one of the most discussed function blocks are the frequency filters. Due to the trends towards low-voltage and low-power applications, there is a growing interest in designing fully differential frequency filters [1]−[18]. Compared to their single ended counterparts [19]–[24], the differential filters have the advantage of rejecting the common-mode noise signals, exhibit higher capability to reject power supply noise and feature enhanced dynamic range along with reduced harmonic distortion of the signal being processed. For the design of fully differential function blocks the operational transconductance amplifiers (OTA) are commonly employed [1]−[5]. As an example, the low-pass filter [2] can be mentioned, where operational transconductance amplifiers (OTAs) are employed. Another OTA-based filter has been presented in [5], where five active and three passive elements are used to implement the basic frequency responses. Other circuit solutions using OTAs as active elements have been also presented: e.g. Pankiewiczby et al. [1], Hwang et al. [3] or Carrillo et al. [4]. Besides OTA-based differential circuits, other types of active building blocks (ABBs), generally based on current conveyors, are also used for the design of such function blocks, as compared to standard operational amplifiers these active elements mainly offer higher frequency bandwidth, higher slew-rate and higher dynamic range [6]. Based on the topology of SK (Sallen-Key) high-pass filter,

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Keywords: Analog signal processing, current conveyor, fully differential filter, band-reject, voltage-mode.

∗ Corresponding

author. Email addresses: [email protected] (Jaroslav Koton ), [email protected] (Norbert Herencsar), [email protected] (Ondrej Sladok), [email protected] (Jiun-Wei Horng) ¨ Preprint submitted to Int. J. Electron. Commun. (AEU)

January 26, 2016

Page 1 of 10

Table 1: Comparative study with previously reported true- and pseudo-differential filters. Filter responses

No. of ABBs

[1] [2] [3] [4] [5] [7] [8] [9] [10] [11]

True-Diff. True-Diff. True-Diff. True-Diff. True-Diff. True-Diff. True-Diff. Pseudo-Diff. True-Diff. Pseudo-Diff.

2002 2006 2007 2011 2011 2000 2004 2004 2013 2014

11 OTA 28 CMOSa 7 OTA 2 FD OTA 5 DCBOTA 1 FDCCII 3 FDCCII 3 DO-DDCC 5 DCCDVCC 7 CDCC

[12]

Pseudo-Diff.

2006

[13]

Pseudo-Diff.

2015

[14] [15]

Pseudo-Diff. Pseudo-Diff.

2014 2014

5th -order LP 6th -order LP 3rd -order LP 2nd -order LP 2nd -order LP, BP, HP 2nd -order LP 2nd -order LP, BP 2nd -order LP, BP, HP 2nd -order LP, BP, HP 2nd -order LP, BP, HP 1st -order AP 2nd -order AP, BR 1st -order LP, AP 1st -order HP, AP 1st -order LP, HP, AP 1st -order AP

[16]

True-Diff.

2010

2nd -order BP nd

[17]

True-Diff.

2013

2

[18] Proposed

True-Diff. Pseudo-Diff.

2015 2015

1st -order AP 2nd -order BR

b

2 DPDVCC 2 1 1 1 1 1 1 1

DC-DVCC DDCC DACA, 4 CF DACA, 6 CF DACA, 4 CF DACA, 6 CF ACA, 2 CF CCII, 2 DDCC

: Based on OTA and two integrator loop with negative resistance load : Effective output node capacitances used

Passive el./ ABB param. matching Yes No Yes Yes Yes Yes No No No No

Operation mode

Simul./ meas.

VM VM VM VM VM VM VM VM VM&TAM CM

Both Simul. Both Meas. Simul. Both Meas. Simul. Simul. Simul.

Yes

VM

Simul.

Yes

VM

Simul.

Yes Yes

CM VM

Simul. Simul.

Yes

CM

Simul.

Yes

CM

Simul.

Yes No

CM VM

Simul. Both

an

a

-order BP

1 DVCC

No. of grounded/floating C/R 9 fl./0 0b /0 6 gr./0 4 gr./0 2 fl./1 fl. 2 gr., 4 fl./2gr., 2 fl. 2 fl./4 fl. 2 gr./5 gr. 2 fl./1 fl. 2 gr./8 gr. 3 fl./1 gr. 1 gr., 2 fl./3 fl. 2 fl./2 gr. 2 gr./2 fl. 1 gr., 1 fl./1 gr., 3 fl. 1 gr./2 gr., 1 fl. 2 fl./4 fl. 2 fl./4 fl. 2 fl./4 fl. 2 fl./4 fl. 1 fl./0 2 gr./2 gr.

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Year

cr

Filter type

us

Ref.

where vid , vic and vod denote differential-mode input, common-mode input and differential-output voltage, respectively. The differential input signal vid is simply the difference between the two input signals vi1 and vi2 , whereas the common-mode input signal vic is the average of the two input signals. The differential-output voltage vod is then represented as:

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all-pass filters have been recently presented by Khan et al. [13], Ansari and Soni [14], and Horng et al. [15], where the digitally controllable DVCC or DDCC are used as active elements. For the frequency filter design also current followers with unity and controllable current gain can be used to implement fully differential current-mode band-pass filters [16], [17], or to design a pole frequency and pass-band gain tunable all-pass filter as presented by Herencsar et al. [18]. The summary of above mentioned and previously reported fully differential filters based on various relevant criteria can be found in Table 1. In this paper, using two DDCCs and one second generation current conveyor (CCII) the voltage-mode differential second-order band-reject filter is presented. Except the three active elements, only two resistors and two capacitors are required, whereas all are grounded. The input impedance of the filter is infinitely high in theory and hence the filter is suitable for being connected in cascade. The proposed structure assumes both differential input and output voltages, however, the inner structure of the filter is not differential. Nevertheless, the such pseudodifferential frequency filter still features high common-mode rejection ratio and low sensitivities. The behavior of the voltage-mode band-reject filter is verified by Spice simulations and furthermore by the experimental measurements that show the feasibility of the function block.

Generally, once analyzing the performance of voltagemode differential circuits the following notation is assumed [26]: vic =

vi1 + vi2 , 2

(2)

where Adm and Acm are the differential and common-mode gains, respectively. To evaluate the rejection of commonmode signals in preference to differential signals, commonmode rejection ratio (CMRR): Adm CM RR = 20 log (3) Acm is used. To design a fully differential frequency filter, mostly single-ended prototype is mirrored about the ground plane [27]. Such design technique results in the usage of fully differential active elements and also a symmetry in passive elements can be observed. Hence, such circuits are also fully differential from the viewpoint of their implementation and can be referred to as “true”-fully, also “true” or just simply differential. Such circuits generally feature very high common-mode rejection ratio, but the complexity of the circuit topology significantly increases [1]–[5], [7], [8], [16]–[18]. However, as obvious from the mathematical description point of view using (1)–(3), for sake of analysis only the input and output signals are considered. Therefore, “pseudo”-fully (or just simply “pseudo”) differential function blocks can generally be design that feature both dif-

2. True- vs. Pseudo-Fully Differential Circuits

vid = vi1 − vi2 ,

vod = Adm vid + Acm vic ,

vod = vo1 − vo2 , (1) 2

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vi1 vid vi2

Truedifferential circuit

Truedifferential circuit

Pseudodifferential circuit

vo1

Pseudodifferential circuit

iY1

vo2

vY1

vi

Z1 Z2

vid Remaining part of the singleended circuit

vi2

vX

Remaining part of the singleended circuit

vZ1

(b)

Figure 3: Circuit symbols of (a) DDCC, (b) CCII.

vo1 vo1

DDCC2 1 voltages vo1 vand vDDCC o2 do not have to be mutually shifted i1 vod CCII1 Y1 Y1 vid DDCC DDCC in phase by 180 deg. further reduces 1Z1Such an approach 2 Z1 Y Z1 Y2 Y2 vi1 vi2 vod CCII Y1 Y3 Z2 Y1 Y3 Z2 vid X 1is Z2 the complexity of the final circuit solution and also used Y Z1 Y2 Z1 Y2 Z1 X X vi2 vo2 to design new pseudo-differential second-order band-reject Y3 Z2 C1 Y3 Z2 C2 X Z2 R R X X filter that is discussed in section 1 4. 2 vo2

DDCC Y1 Y2 Z2 Y3 Z1 X

vo

cr

Z1 Z2

vY

iZ1 iZ2 iZ1 vZ1 vZ2

C1

vo1

R1

C2

R2

3. DDCC and CCII Description

vod

us

Y X

iY vY iX

CCII Y Z1 CCII X Z2 vXY Z1 iZ2 X Z2 vZ2 iX

(a)

Y1 Y2 Z1 Y3 Z2 X

Remaining part of the singleended circuit

CCII

vY2 iY3 vY3 iX vY3 vX

DDCC

(a) Remaining part of the singleended circuit

vY2

iZ1 Z1 Y1 Y3 Z2 iZ2 iZ1 v iY2 X Z1 XZ1 iZ2 vZ2 Y3 Z2 vX vZ1 X vZ2

DDCC Y2

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CCII Y X

iY3

vY1 iY2

iY

Y1

iY2

Figure 1: The use of pseudo-differential circuits together with truedifferential function blocks. vi1

DDCC

iY1

vod

vo2

The differential difference current conveyor (DDCC), whose electrical symbol is shown in Fig. 3(a), is a sixterminal network with one low-impedance current input X, three high-impedance voltage inputs Y1, Y2, Y3, and two high-impedance current outputs Z1, Z2. For ideal active element the relationship between the terminal currents and voltages is described as follows:

(b)

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Figure 2: Transformation of (a) single-ended input to differential, (b) single-ended output to differential [9] to design pseudo-differential circuits.

ferential input and output voltages, however, do not feature a fully differential inner structure as it is the case of true-differential circuits, but rather the inner structure of the circuit remains single-ended. Such an approach can still ensure sufficiently high common-mode rejection ratio, while keeping the inner structure less complex compared to the true-differential solutions. In practice, in combination with true-differential circuits the pseudo-differential function blocks can be used as the last section(s) of frontend analog signal processing path (Fig. 1), where very high common-mode rejection ratio is no more required. A simple approach of designing pseudo-differential filters using DDCCs has been presented by Ibrahim et al. [9]. In Fig. 2(a), the transformation of the single-ended input to differential is shown. As it can be obvious, to perform the transformation it is assumed that the input voltage is directly applied to the high-impedance terminal Y of the active element. The transformation of the singleended output to differential is given in Fig. 2(b). In this case, the inverting voltage terminal Y2 of DDCC is used to obtain a differential output voltage vod . Here, it can be seen that the voltage inverter within the active element is used just to generate a phase shift of 180 deg between the voltages vo1 and vo2 . To reduce the complexity of pseudo-differential filter, it is not necessarily required to employ DDCC at the output, since only a simple inverting second-generation current conveyor (ICCII) [28] could be used. Other circuit realizations of pseudo-differential filters generally based on the above mentioned principle can be found in the literature [11]−[15]. However, as shown by Horng et al. [15] to obtain required differential frequency response the output

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vX = vY1 − vY2 + vY3 , iY1 = iY2 = iY3 = 0, iZ1 = iX , iZ2 = −iX .

(4)

The second-generation current conveyor (CCII) is generally a four-terminal network as shown in Fig. 3(b). Compared to DDCC, the CCII features only single high-impedance voltage input terminal Y and the relation between the terminal currents and voltages for ideal CCII is given as: vX = vY ,

iY = 0,

iZ1 = iX ,

iZ2 = −iX .

(5)

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4. Proposed Pseudo-Differential Band-Reject Filter The proposed pseudo-differential frequency filter is shown in Fig. 4. Once ideal active elements are assumed, the output voltages vo1 and vo2 can be expressed as: vo1 =

s2 C1 C2 R1 R2 + sC1 R2 + 1 vid + 0 · vic , s2 C1 C2 R1 R2 + sC1 R2 + 1

(6)

sC1 R2 vid + 0 · vic , (7) s2 C1 C2 R1 R2 + sC1 R2 + 1 and according to (1), for differential output voltage vod it holds: vo2 =

vod =

s2 C1 C2 R1 R2 + 1 2 s C1 C2 R1 R2 + sC1 R2

+1

vid + 0 · vic .

(8)

Comparing (2) to (8), the differential gain Adm of the proposed pseudo-differential filter is: Adm =

s2 C1 C2 R1 R2 + 1 , s2 C1 C2 R1 R2 + sC1 R2 + 1

(9)

3

Page 3 of 10

vo1

vo1 RW

vi1 vidm vi2

DDCC1

DDCC2

Y1 Y2 Z1 Y3 Z2 X

Y1 Y2 Z1 Y3 Z2 X

C1

CCII1 Y X

C2

R1

vi1

vodm

vidm

Z1 Z2

vi2 RX

vo2

DDCC1

DDCC2

Y1 Y2 Z1 Y3 Z2 X

Y1 Y2 Z1 Y3 Z2 X

C1

Cv

R2

Rv

R1'

CW

CCII1 Y X

RX

C2

vodm

Z1 Z2 vo2

R2

Figure 5: Proposed fully differential band-reject filter assuming parasitic impedances of the active elements.

whereas the common-mode gain Acm is zero, and therefore CM RR → ∞. From (9) it can be seen that a second-order band-reject response is obtained from the proposed circuit. As only four passive elements are used, no matching conditions are required. Since the input signal is directly applied to the Y terminals of DDCC1 , the circuit features high input impedance, which is also advantageous once connecting the circuit in cascade. Furthermore, no capacitors are connected to the low-impedance terminals X of the active elements and hence no additional parasitic poles are created in the transfer function once non-ideal active elements will be assumed. The angular pole-frequency ω0 and quality factor Q of the filter are given as: r C 2 R1 1 , Q= , (10) ω0 = √ C 1 R2 C1 C2 R1 R2

Assuming the non-ideal voltage and current gains of the active elements, the reanalysis of the proposed filter yields the following differential and common-mode gains:

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Figure 4: Proposed pseudo-differential band-reject filter.

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s2 C1 C2 R1 R2 + sC1 R2 α2 (β3 − β2 δ) + +α1 α2 β1 γδ β1 + β2 , Adm = 2 s2 C1 C2 R1 R2 + sC1 R2 α2 β3 + α1 α2 β1 γ2 δ (13) s2 C1 C2 R1 R2 + sC1 R2 α2 (β3 − β2 δ) + +α1 α2 β1 γδ . Acm = (β1 − β2 ) 2 s C1 C2 R1 R2 + sC1 R2 α2 β3 + +α1 α2 β1 γ2 δ (14) According to (3), the common-mode rejection ratio is then: β1 + β2 , CM RR = 20 log (15) 2 (β1 − β2 ) hence to ensure high rejection of common-mode voltage at the output, the voltage tracking errors εvj must be of such values to maintain β1 ≈ β2 . Due to the non-ideal voltage and current gains of the active elements, the angular pole-frequency, quality factor and differential pass-band gains are affected: r r r α1 α2 β1 γ2 δ 1 α 1 β1 γ 2 δ C 2 R 1 ω0 = , Q= , C1 C2 R1 R2 β3 α2 C 1 R2 (16) β1 + β2 G0dm = G∞dm = , 2 however, once the voltage and current tracking errors of the active elements are minimal, the influence of non-ideal voltage and current gains to the filter parameters is negligible. The active and passive sensitivities to the angular-pole frequency, quality factor, and pass-band gain are obtained as:

and the pass-band voltage gains below (G0 ) and above (G∞ ) the pole-frequency f0 (f0 = ω0 /(2π)) are unity.

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5. Non-ideality Analyses

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Taking into consideration the non-idealities of the active elements used, the terminal relations of DDCC can be expressed as: vX = β1 vY1 − β2 vY2 + β3 vY3 ,

iZ2 = −α2 iX , (11) where βj = 1 − εvj and αk = 1 − εik (for j = {1, 2, 3} and k = {1, 2}) are the voltage and current gains of the DDCC, whereas |εvj | << 1 and |εik | << 1 denote the voltage and current tracking error, respectively. Similarly, the non-ideal behavior of the CCII can be defined as follows: vX = δvY ,

iZ1 = α1 iX ,

iZ1 = γ1 iX ,

iZ2 = −γ2 iX ,

Sαω10 = Sαω20 = Sβω10 = Sγω20 = Sδω0 = 12 , ω0 ω0 ω0 ω0 SC = SC = SR = SR = − 21 , 1 2 1 2

(12)

where δ = 1 − εv and γk = 1 − εik (for k = {1, 2}) are the voltage and current gains of the CCII, whereas |εv | << 1 and |εik | << 1 represents the voltage and current tracking error, respectively. Note that the currents iYj flowing into the Yj terminals of the active elements are assumed to be zero due to in practice high input impedance of these terminals.

SαQ1 = −SαQ2 = SβQ1 = SγQ2 = SδQ = 12 ,

SβQ3 = −1,

Q Q Q Q SC = −SC = −SR = SR = − 12 , 1 2 1 2

SβG10dm ;G∞dm =

β1 β1 +β2 ,

SβG20dm ;G∞dm =

(17)

β2 β1 +β2 ,

which are in absolute value less or equal to unity and hence can be considered as low. 4

Page 4 of 10

Taking into account the important parasitic impedances of the active elements as shown in Fig. 5 (for sake of simplicity the voltage and current gains are assumed to be unity), the following differential gain can be derived: 0

0

0

−30

s2 C1 C2 R1 R2 Rv Rw + sC1 R1 R2 Rv + 0 0 0 0 +sC2 R1 R2 Rw + sC1 RX Rv Rw + 0 0 +R1 R2 + Rw (Rv + RX )

Adm =

2

0

0

0

0

0

0

0

0

−35

0

−40

,

0

s C1 C2 R1 R2 Rv Rw + sC1 R1 R2 Rv + 0 0 0 0 0 +sC2 R1 R2 Rw + sC1 R2 Rv Rw + 0

−25

0

−45 −50 −10 10



+sC1 RX Rv Rw + R1 R2 + Rw R2 + RX + Rv (18) 0 0 0 where C1 = C1 + Cv , C2 = C2 + Cw , R1 = R1 + RX , 0 R2 = R2 + RX , Rv = RZ1 kRY1 , Rw = RZ2 kRY3 kRY , Cv = CZ1 + CY1 , Cw = CZ2 + CY3 + CY , whereas RX , RY and RZ , and CY and CZ are the parasitic resistances and capacitances of the terminal X, Y, and Z, respectively. Analyzing (18) it can be shown that to maintain proper operation of the frequency filter it must hold R1 ; R2 << Rv ; Rw , which yields the following approximate angular pole-frequency and quality factor: s 0 0 C 2 R1 1 (19) ω0 ≈ p 0 0 0 0 , Q ≈ 0 0 . C 1 R2 C 1 C 2 R1 R2

10

−9 −8

10

−7

10

10

−10

10

−9

10

−8

−7

C 2 [F]

cr

C 1 [F]

10

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0

Figure 6: Variation of differential gain Adm at pole-frequency f0 (f0 = 100 kHz, Q = 1.05). 10 0

an

-10

us

0

−20 |A dm(f0 )| [dB]

0

−15

Adm [dB]

-20

-30

M

-40

ed

To describe the properties of the frequency filter by means of passive elements, i.e. using (10), for the values of passive elements it should hold C1 >> Cv , C2 >> Cw , and R1 ; R2 >> RX .

-50 Ideal Simulated Measured

-60 -70 3 10

10

4

5

10 Frequency [Hz]

10

6

10

7

6. Simulation and Experimental Measurements

pt

To verify the behavior of the proposed pseudo-differential filter, first the simulations have been performed. Although numerous CMOS and BJT implementations of the DDCC and CCII are presented in the literature [29]−[32], in this case to implement the required active elements the UCC-N1B [33] integrated circuit has been used. The UCCN1B was designed at our workplace, manufactured in cooperation with ON Semiconductor, Ltd. using 0.35 µm CMOS technology and in this paper it has been also used for experimental verification of the proposed filter as it will be described below. The UCC-N1B combines an universal current conveyor (UCC) used to implement the DDCC, and second-generation current conveyor. According to the notation used above, the non-ideal parameters of the active elements are summarized in Table 2. Once parasitic impedances of the active elements are assumed, optimum values of passive elements can be determined to reach the maximum stopband attenuation at the required pole-frequency and quality factor of the filter. In Fig. 6, the variation of differential gain Adm at polefrequency f0 while changing the values of capacitors C1 and C2 is shown. These results are valid for f0 = 100 kHz, Q = 1.05, whereas using (10) the values of resistors R1 and R2 are derived. As it can be seen from Fig. 6, the

Figure 7: Simulation and experimental measurement results of the differential gain Adm of the proposed filter.

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maximum stopband attenuation can be reached choosing capacitors from the range of C1 = h1, 100i nF and C2 = h1, 4i nF. Using (10) and taking into consideration the recommendations to minimize the influence of parasitic impedances as described in Section 5, the values of passive elements are R1 = 620 Ω, R2 = 560 Ω, C1 = C2 = 2.7 nF to obtain a band-reject response featuring pole-frequency f0 = 100 kHz and quality factor Q = 1.05. The differential gain obtained by simulations (dashed line) compared to ideal (dotted line) response is shown in Fig. 7. Since the product of coefficients α1 α2 β1 γ2 δ ≈ 1.009 in (16) is very close to unity, the shift in pole-frequency is minimal. The quality factor has decreased from the theoretical value to 1.046, which also corresponds to the theoretical presumptions stated by (16). For the simulations, the SPICE macromodel of the UCC-N1B that assumes the non-ideal parameters listed in Table 2, Table 3 and voltage and current limitations as described in [33] has been used. Due to the parasitic impedances of the active elements, the stopband attenuation at pole-frequency obtained by 5

Page 5 of 10

UCC-N1B [33] (typical values). [ΩkpF] 348 · 106 k4.9 355 · 106 k4.5 644 · 106 k3.9 88 · 106 k4.6 702 · 103 k5.3 847 · 103 k6.7 1.1 · 106 k2.7 1.2 · 106 k3.6 2.4

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Table 2: Non-ideal parameters of DDCC and CCII according to the properties of Parameter [-] Parameter Voltage gain β1 0.975 Y1 terminal impedance RY1 kCY1 Voltage gain β2 0.968 Y2 terminal impedance RY2 kCY2 Voltage gain β3 1.009 Y3 terminal impedance RY3 kCY3 Voltage gain δ 0.999 Y terminal impedance RY kCY Current gain α1 0.965 Z1a terminal impedance RZ1 kCZ1 Current gain α2 1.029 Z2a terminal impedance RZ2 kCZ2 Current gain γ1 0.985 Z1b terminal impedance RZ1 kCZ1 Current gain γ2 1.043 Z2b terminal impedance RZ2 kCZ2 Xa,b terminal impedance RX a Valid for DDCC implemented by UCC b Valid for CCII

60

simulations is not infinitely high but approx. 32 dB. This value corresponds to attenuation of 44 dB at pole-frequency that can be derived from (18). The difference in the attenuation at pole-frequency obtained by simulations is mainly caused due to the fact that (18) assumes only the most significant parasitic impedances of the active elements and their voltage and current gains to be unity. From the simulations, the pass-band gain below (G0dm ) and above (G∞dm ) the pole-frequency is −0.25 dB, which also corresponds to the previous presumptions given by (16) very well. According to (15) and using the typical values of voltage gains (Table 2) the theoretical value of CMRR of the differential filter is approx. 43 dB. As it can be seen from Fig. 8, the common-mode rejection ratio obtained by meas of simulations (dashed line) agrees well to these expectations. Up to frequency of 1 MHz the CMRR is almost constant. Above 1 MHz the common-mode rejection ratio decreases, which is mainly caused by different frequency bandwidth limitations of the corresponding voltage gains of the active elements [33] as listed in Table 3. The behavior of the proposed pseudo-differential frequency filter has also been verified by the experimental measurements using the Agilent 4392A Network/Spectrum Analyzer. To generate a differential input signal and to evaluate the common-mode rejection ratio, additional circuitry was required as shown in Fig. 9, whereas readily available integrated circuits were used. The AD 8476 [34] at the input was used to generate a differential signal from the single-ended input signal vdm . To emulate commonmode input signal and to be able to evaluate the commonmode rejection ratio, two AD 8271 [35] operating as summing amplifiers were used. At the output, the differential voltage response is converted to a single-ended voltage vo using AD 8429 [36]. The printed circuit board (PCB) of the prototype filter together with the single-to-differential (S/D) and differential-to-single (D/S) ended convertors is

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Table 3: Voltage and current gain bandwidth (BW) of DDCC and CCII according to the properties of UCC-N1B [33] (minimal values). Parameter [MHz] Parameter [MHz] 43 40 Current gain BW f−3dB-α1 Voltage gain BW f−3dB-β1 49 46 Current gain BW f−3dB-α2 Voltage gain BW f−3dB-β2 Voltage gain BW f−3dB-β3 44 Current gain BW f−3dB-γ1 45 48 Voltage gain BW f−3dB-δ 32 Current gain BW f−3dB-γ2

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Figure 8: The common-mode rejection ratio (CMRR) obtained by simulations and experimental measurements.

shown in Fig. 10. The differential gain Adm obtained by experimental measurements is shown in Fig. 7 (solid line) and is compared to the ideal and simulated response. As it can be seen also the experimental measurements agree to the expected results very well as the obtained response is almost identical to the simulated one. Compared to simulations, the reached stopband attenuation the pole-frequency has decreased by only 1.2 dB to the final value of 30.8 dB. The screenshot of the Network/Spectrum Analyzer showing the magnitude and phase of the differential gain Adm is given in Fig. 11. The common-mode rejection ratio CMRR has also been experimentally verified. The results are given in Fig. 8 and as it can be seen, the value of CMRR reached by measurements (solid line) is higher than expected by theoretical assumptions or simulations. Such difference is caused by the fact that once determining the theoretical value using (15) and even the UCC and CCII Spice simulation mod6

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vdm

AD 8476

AD 8271

vi1

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Fully differential filter AD 8271

vi2

AD 8429 vo vo2

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Figure 9: The block diagram of the measurement workplace.

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Figure 11: The screenshot of the differential gain magnitude and phase. 4.5

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Figure 10: Prototype PCB of the proposed pseudo-differential filter together with S/D and D/S converters.

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els assume the typical values of the voltage (and current) gains [37] and obviously within in the experimental measurements the difference between β1 and β2 of the UCC used to implement the DDCC1 was smaller. However, also in experimental measurements a pattern very similar to simulations can be observed as for frequencies above approx. 1 MHz the value of CMRR starts to decrease due to different frequency bandwidth limitations of the voltage gains. Except the differential gain Adm and common-mode rejection ratio CMRR also the total harmonic distortion THD of the differential filter has been evaluated by experimental measurements. The change in THD according to the differential input signal amplitude Vid is shown in Fig. 12, whereas the frequency of the input signal was 1 kHz. As it can be seen, for input signal amplitude below 0.5 V the total harmonic distortion is less than 1 %. For higher input signal amplitudes THD starts to increase as the active elements start to reach their voltage and current saturation levels [33]. Finally, the measured time-domain responses of the pseudo-differential filter are depicted in Fig. 13 and Fig. 14. The voltages at vi1 , vi2 , vo1 and vo2 (according to Fig. 9) represented by corresponding traces are shown in Fig. 13. The results in Fig. 13(a), Fig. 13(b) and Fig. 13(c) show the behavior of the filter below, at and above the polefrequency f0 , respectively. The results agree to the expected behavior described by the output voltages (6) and (7) since for all assumed frequencies of the differential voltage vdm the output voltage vo1 remains unaffected. On the

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Figure 12: The measured THD of the proposed differential filter.

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contrary, the output voltage vo2 below and above the polefrequency is significantly attenuated and at pole-frequency it reaches its maximum value, which corresponds to the pass-band behavior (7). In Fig. 14, for the input signals of the filter selected as vdm : 1 kHz, 200 mVpp, vcm : 10 kHz, 200 mVpp, the output voltage vo , generally corresponding to the differential output voltage vdm , is shown (Trace 3). Also here the filter shows proper behavior, even for common-mode signal with high amplitude. 7. Conclusion In this paper, new pseudo-differential voltage-mode bandreject frequency filter has been presented. The proposed circuit uses two differential difference current conveyors (DDCCs) and one second-generation current conveyor (CCII) and four passive elements - two resistors and two capacitors, all grounded and without any matching condition. The frequency filter features high input impedance, high 7

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Figure 14: The measured time-domain responses at the input and output of the proposed filter, vdm : 1 kHz, 200 mVpp, vcm : 10 kHz, 200 mVpp, Trace 1: vi1 , Trace 2: vi2 , Trace 3: vo .

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more than 43 dB and hence, the pseudo-differential filters can generally be considered as useful function blocks for analog signal processing. Acknowledgments Research described in this paper was financed by the National Sustainability Program under grant LO1401. For the research, infrastructure of the SIX Center was used.

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References

Figure 13: The measured time-domain responses at the input and output of the proposed filter, (a) vdm : 10 kHz, 200 mVpp, vcm : 100 kHz, 50 mVpp, (b) vdm : 100 kHz, 200 mVpp, vcm : 1 MHz, 50 mVpp, (c) vdm : 1 MHz, 200 mVpp, vcm : 10 MHz, 50 mVpp, Trace 1: vi1 , Trace 2: vi2 , Trace 3: vo1 , Trace 4: vo2 .

common-mode rejection ratio, and low active and passive sensitivities. The influence of the non-ideal parameters of the active elements used has been also evaluated, whereas both the non-ideal voltage and current gains and parasitic impedances were taken into account. Based on the nonideal analysis results and recommendations, the frequency filter has been simulated and furthermore, using readily available active elements, the performance of the filter has also been verified by the experimental measurements. Both the simulation and experimental measurements agree well with the theoretical analyses. The common-mode rejection ratio reached by experimental measurements is

[1] B. Pankiewicz, M. Solecki, and S. Szczepanski, A fully differential CMOS OTA for continuous-time filter applications, Proc. IEEE Int. Conf. Circuits Systems Communications (ICCSC), 2002, pp. 42–45. [2] R. Thirugnanam, D. S. Ha, B. H. Park, and S. S. Choi, Design of a tunable fully differential GHz range Gm-C lowpass filter in 0.18 µm CMOS for DS-CDMA UWB transceivers, IEEE Int. Symposium on Circuits and Systems (ISCAS), May 2006, pp. 2377–2380. [3] Y.-S. Hwang, J.-J. Chen, and J.H. Lai, A fully differential thirdorder VHF Gm − C filter based on linear transformation techniques, J. of Circuits, Systems, and Computers, 16 (2007) 221– 231. [4] J. M. Carrillo, M. A. Dominguez, J. F. Duque-Carrillo, and G. Torelli, 1.2-V fully differential OTA-C lowpass filter based on bulk-driven MOS transistors, Proc. European Conf. Circuits Theory Design (ECCTD), Aug. 2011, pp. 178–181. [5] P. Beg, I. A. Khan, S. Maheshwari, and M. A. Siddiqui, Digitally programmable fully differential filter, Radioengineering, 20 (2011) 917–925. [6] C. Toumazou, F. J. Lidgey, and D. G. Haigh, Analogue IC design: the current-mode approach, (Peter Peregrinus Ltd., London, 1990), p. 646. [7] H. Alzaher, H. Elwan, and M. Ismail, CMOS baseband filter for WCDMA integrated wireless receivers, El. Letters, 36 (2000) 1515–1516. [8] S. M. Al-Shahrani, Fully differential second-order filter, Proc. 47th Midwest Symposium on Circuits and Systems (MWSCAS), July 2004, pp. 299–301. [9] M. A. Ibrahim and H. Kuntman, A novel high CMRR high input impedance differential voltage-mode KHN-biquad employing DO-DDCCs, Int. J. Electron. Commun. - AEU, 58 (2004) 429–433.

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[33]

[34] [35] [36] [37]

Ac ce

pt

ed

M

an

Authors

ip t

[32]

cr

[31]

pass filter canonical in number of resistor and capacitors employing a single DDCC, Circuits, Systems and Signal Processing, 22 (2003) 525–536. A. S. Sedra, G. W. Roberts, and F. Gohh, The current conveyor: history, progress and new results, IEE Proceedings, 137 (1990) 78–87. S. B. Salem, M. Fakhfakh, D. S. Masmoudi, M. Loulou, P. Loumeau, and N. Masmoudi, A high performances CMOS CCII and high frequency applications, Analog Integr Circ Sig Process, 46 (2006) 71–78. Datasheet UCC-N1B - Universal Current Conveyor (UCC) and Second-Generation Current Conveyor (CCII+/-), Brno University of Technolohy, On Semiconductor Ltd., Rev. 1, 2012. Datasheet AD 8476 - Low Power, Unity Gain, Fully Differential Amplifier and ADC Driver, Analog Devices, Rev. B., 2012. Datasheet AD 8271 - Programmable Gain Precision Difference Amplifier, Analog Devices, Rev. √ 0, 2009. Datasheet AD 8429 - 1 nV/ Hz Low Noise Instrumentation Amplifier, Analog Devices, Rev. 0, 2011. R. Sponar, K. Vrba, Measurements and behavioral modeling of modern conveyors, Int. J. Comp. Sci. Net. Sec. - IJCSNS, 6 (2006) 57–65.

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[10] P. Beg, S. Maheshwari, and M. A. Siddiqi, Digitally controlled fully differential voltage- and transadmittance-mode biquadratic filter, IET Circuits, Devices & Systems, 7 (2013) pp. 193–203. [11] A. K. Singh and P. Kumar, A novel fully differential current mode universal filter, Proc. of 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2014, pp. 579–582. [12] M. A. Ibrahim, S. Minaei, and H. Kuntman, DVCC based differential-mode all-pass and notch filters with high CMRR, Int. J. Electronics, 93 (2006) 231–240. [13] I. A. Khan, M. I. Masud, and S. A. Moiz, Reconfigurable fully differential first order all pass filter using digitally controlled CMOS DVCC, Proc. 8th IEEE GCC Conference and Exhibition (GCCCE), February 2015, pp. 1–5. [14] M. S. Ansari and G. S. Soni, Digitally-programmable fullydifferential current-mode first-order LP, HP and AP filter sections, Proc. of 2014 International Conference on Signal Propagation and Computer Technology (ICSPCT), July 2014, pp. 524–528. [15] J. W. Horng, C. M. Wu, and N. Herencsar, Fully differential first-order allpass filters using a DDCC, Indian J. Engineering and Materials Sciences, 21 (2014) 345–350. [16] J. Koton, N. Herencsar, K. Vrba, and J. Jerabek, Digitally adjustable current amplifier and its application in fully differential current-mode band-pass filter design, Elektrorevue - Internet Journal, 1 (2010) 47–52. [17] J. Jerabek, J. Koton, R. Sotner, and K. Vrba, Adjustable bandpass filter with current active elements: two fully-differential and single-ended solutions, Analog Integr Circ Sig Process, 74 (2013) 129–139. [18] N. Herencsar, J. Jerabek, J. Koton, K. Vrba, S. Minaei, I. C. Goknar, Pole frequency and pass-band gain tunable novel fullydifferential current-mode all-pass filter, IEEE Int. Symposium on Circuits and Systems (ISCAS), May 2015, pp. 2668-2671. [19] W.-K. Chen, The circuits and filters handbook, (3rd edition, CRC Press, 2003), p. 2961. [20] S. Minaei, E. Yuce, and O. Cicekoglu, ICCII-based voltagemode filter with single input and six outputs employing grounded capacitors, Circuits, Systems and Signal Processing, 25 (2006), 559–566. [21] S. Minaei and E. Yuce, All grounded passive elements currentmode all-pass filter, J. of Circuits, Systems and Computers, 18 (2009) 31–43. [22] F. Yucel and E. Yuce, A New CCII based voltage-mode multifunctional filter with reduced number of active and passive elements, J. of Circuits, Systems and Computers, 24 (2015) 1550047. [23] F. Yucel and E. Yuce, A new voltage-mode multifunctional filter using only two voltage followers and a minimum number of passive elements, J. of Circuits, Systems, and Computers, 24 (2015) 1550085. [24] E. Yuce, Voltage-mode multifunction filters employing a single DVCC and grounded capacitors, IEEE Trans. on Instrumentation and Measurement, 58 (2009) 2216–2221. [25] H. A. Alzaher, N. Tasadduq, and Y. Mahnashi, A highly linear fully integrated powerline filter for biopotential acquisition systems, IEEE Trans. on Biomedical Circuits and Systems, 7 (2013) pp. 703–712. [26] U. Tietze, Ch. Schenk, and E. Gamm, Electronic Circuits: Handbook for Design and Application, (Springer, Berlin, 2008), p. 1543. [27] R. Raut and M. N. S. Swamy, Modern Analog Filter Analysis and Design, (WILEY-VCH, Weinheim, 2010), p. 355. [28] A. M. Soliman, The inverting second generation current conveyors as universal building blocks, Int. J. Electron. Commun. - AEU, 62 (2008) 114–121. [29] M. A. Ibrahim and H. Kuntman, High linearity CMOS differential difference current conveyor (DDCC), Proc. Int. Conf. on Microelectronics - ICM, Dec. 2002, pp. 6-9. [30] M. A. Ibrahim, H. Kuntman, and O. Cicekoglu, First-order all-

Jaroslav Koton was born in Hustopece, Czech Republic, in 1981. He received the M.Sc. and Ph.D. degrees in Electrical Engineering from Brno University of Technology in 2005 and 2009, respectively. At Brno University of Technology, he is currently an Associate Professor at the Dept. of Telecommunications, where is also serves as deputy vice-head for research and development and international relation. As a senior researcher he also works for the SIX Research Centre and is the vice-head of the Converged Systems group. His research and development activities are focused on integer and fractionalorder liner- and non-linear circuit design methods with current or voltage conveyors, and current active elements. He is an author or co-author of more than 150 research articles published in international journals or conference proceedings. Since 2012, he is Editor-in-Chief of the International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems. He also serves as a reviewer of numerous international journals. Assoc. prof. Jaroslav Koton is Senior Member of IEEE and IACSIT, and member of the Czech Science Foundation Panel Committee. Norbert Herencsar was born in Slovak Republic, in 1982. He received the M.Sc. and Ph.D. degrees in Electronics & Communication and Teleinformatics from Brno University of Technology, Czech Republic, in 2006 and 2010, respectively. Since December 2015, he is an Associate Professor at the Department of Telecommunications of Brno University of Technology, Brno, Czech Republic. During September 2009-February 2010 and

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Yuan Christian University, Chung-Li, Taiwan. He is now a Professor. Dr. Horng joins the Editorial Board of Active and Passive Electronic Components from 2010. He joins the Editorial Board of Journal of Engineering from 2012. He joins the Editorial Board of Radioengineering from 2011 to 2012. He joins the Editorial Board of Indian Journal of Pure & Applied Physics from 2015. His teaching and research interests are in the areas of Circuits and Systems, Analog Electronics, Active Filter Design and Current-Mode Signal Processing.

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February 2013-May 2013 he was an Erasmus Exchange Student and Visiting Researcher, respectively, with the Department of Electrical and Electronic Engineering, Bogazici University, Istanbul, Turkey. During January 2014-April 2014 he was a Visiting Researcher with the Department of Electronics and Communications Engineering, Dogus University, Istanbul, Turkey. His research interests include analog filters, current, voltage- and mixed-mode circuits, new active elements and their circuit applications, low transistor count circuits, MOSonly circuits, oscillators, and inductor simulators. He is an author or co-author of 56 research articles published in SCI-E peer-reviewed international journals, 24 articles published in other journals, and 89 papers published in proceedings of international conferences. Since 2010, Dr. Herencsar is DeputyChair of the International Conference on Telecommunications and Signal Processing (TSP). Since 2012, he is Co-Editor of the International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems. Since 2014, he is Associate Editor of the Journal of Circuits, Systems and Computers (JCSC). Dr. Herencsar is Senior Member of the IEEE, IACSIT, and IRED, and Member of the IAENG, ACEEE, and RS. Since 2015, he serves as IEEE Czechoslovakia Section SP/CAS/COM Joint Chapter Chair as well as Membership Development Officer.

Ondrej Sladok was born in Czech Republic, in 1991. He received the B.S. degree in Electronic Engineering from Brno University of Technology, Brno, Czech Republic in 2014 and currently he is studying towards the master degree at the same university. Jiun-Wei Horng was born in Tainan, Taiwan, Republic of China, in 1971. He received the B.S. degree in Electronic Engineering from Chung Yuan Christian University, Chung-Li, Taiwan, in 1993, and the Ph.D. degree from National Taiwan University, Taipei, Taiwan, in 1997. From 1997 to 1999, he served as a Second-Lieutenant in China Army Force. From 1999 to 2000, he joined CHROMA ATE INC. where he worked in the area of video pattern generator technologies. Since 2000, he was with the Department of Electronic Engineering, Chung

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