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Quality solder paste systems for use in microelectronic applications
This capacitor is located just under the device, but not under the conductor I/O to avoid a parasitic capacitive coupling. With the coming of leadless and leaded full array chip carriers such as pin grid array, we applied the same concept with a capacitor inside the cap. The results with different current-pulse signals show the effects of the capacitor's inductance, resistance, and capacitance. The main specifications of this new chip carrier will be presented. In addition to improving speed and electrical performances, the IDCCC allows an increase in density and in reliability level.
3. Materials Precision fineness of grind measurement - techniques and instrumentation - for thick film pastes. ROLAND P. ANJARD, SR. Aficroelectron Reliab. 23 (2), 319 (1983) Fineness of Grind, more commonly termed F.O.G., is an important guide to the suitability of completed thick film pastes. F.O.G. provides a measure of the particle size distribution. It is important for several reasons. For normal printing of microelectronic circuits as well as multilayer capacitors, large particulates or flakes can literally plug the screen and thus cause incomplete printed patterns. These particles can cause outright opens or deceptively thin areas which cause subtle rejects on field failures. F.O.G. is even more critical for printing the internal electrodes used in multilayer capacitors, which are extensively incorporated in microelectronic devices and circuits. Very low F.O.G. is preferable, to avoid localized concentration of metallic constituents. For example, an area rich in one metallic such as silver, will have different melting and diffusion characteristics during processing and can cause localized energy concentration during capacitor operation. Thus, F.O.G. is an important tool for hybrid users. A low-leakage VLSI CMOS/SOS process with thin epilayers
J. Y. LEE, D. C. MAYER and P. K. VASUDEV Aficroelectron J. 14 (6), 5 (1983) A new VLSI process was successfully developed for short-channel CMOS/SOS circuits on thin 0.3/~m epi layers. Two kinds of thin epi material were used. The first was grown by a standard CVD process, while the second was prepared by a double solid phase epitaxial regrowth (DSPE) technique. CMOS/SOS ring oscillators with effective channel lengths ranging from 0.7 to 1.3 # m were fabricated. Leakage currents below 3.0pA/ # m were achieved on both n-channel and p-channel devices. The DSPE material showed improvement in both mobility and speed. Step coverage by vapour deposited thin aluminum films
I. A. BLECH Solid St. TechnoL 123 (December 1983) Thin aluminum films used as electrical conductors for microelectronie applications are frequently deposited over substrates containing steps. As device geometries are reduced, the step-by-step spacing is often equal to or
even smaller than its height, and it becomes difficult to obtain a good conformal coverage of closely spaced steps. The origin of the features seen in aluminum profiles over steps for both point source planetary and sputtering deposition systems are reviewed. An optimum vapour distribution function for a sputtering source is calculated for best coverage of narrow lines. Designing solder paste materials to attach surface mounted devices
B A R B A R A ROOS-KOZEL SolidSt. Technol. 173 (October 1983) Thick film solder pastes have become increasingly sophisticated in their ability to meet stringent reliability and performance criteria. To design solder paste for attaching surface mounted devices, the fluxing agents, vehicle system, solder powder alloy, particle size and morphological characteristics, and metal loading must be consistent with the user's processing conditions and the desired product. The properties desired in the solder paste and each of its components are discussed, as are common engineering concerns such as achieving the desired fillet dimensions, ease of cleaning, and the elimination of solder balls and bridging.
A process for two-layer gold IC metalization D O U G SUMMERS SolidSt. Technol. 137 (December 1983) A two-layer gold metalization process is being developed for bipolar VLSI circuits. Interconnect lines on first and second levels are formed by selective electrochemical plating within the openings of a patterned photoresist layer. Metal pitch on both levels is 4/.tm (2 /.tm space, 2/.tm fine). Excellent metal step coverage is provided by the plating method. The interlayer dielectric consists of two films: plasma-deposited silicon nitride and plasma oxide. The nitride layer is thin (250 to 300 A); its purpose is to promote good adhesion between the gold and the plasma oxide. Minimum via size is 2.5 • 2.5 #m. The vias are formed by anisotropic etching in a commercially built single-wafer-per-cycle system. Examples are given of the special advantages and unique problems of this dual-layer process.
Quality solder paste systems for use in microclectronic applications RONALD P. ANJARD, St. Solid St. Techno1183 (October 1983) Solder paste is a critical material for the attachment of active and passive components in high technology and high reliability microelectronics and PCB applications (SMD and Capacitors). A broad understanding of the basic ingredients and the quality factors affecting the choice of the metallurgies available, methods of solder paste deposition, reflow techniques, from the most basic to the current state-of-the-art methods - and essential cleaning approaches are discussed. This paper serves as both a primer and an intermediate guide for understanding and using solder pastes.
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3. Materials Precision fineness of grind measurement - techniques and instrumentation - for thick film pastes. ROLAND P. ANJARD, SR. Aficroelectron Reliab. 23 (2), 319 (1983) Fineness of Grind, more commonly termed F.O.G., is an important guide to the suitability of completed thick film pastes. F.O.G. provides a measure of the particle size distribution. It is important for several reasons. For normal printing of microelectronic circuits as well as multilayer capacitors, large particulates or flakes can literally plug the screen and thus cause incomplete printed patterns. These particles can cause outright opens or deceptively thin areas which cause subtle rejects on field failures. F.O.G. is even more critical for printing the internal electrodes used in multilayer capacitors, which are extensively incorporated in microelectronic devices and circuits. Very low F.O.G. is preferable, to avoid localized concentration of metallic constituents. For example, an area rich in one metallic such as silver, will have different melting and diffusion characteristics during processing and can cause localized energy concentration during capacitor operation. Thus, F.O.G. is an important tool for hybrid users. A low-leakage VLSI CMOS/SOS process with thin epilayers
J. Y. LEE, D. C. MAYER and P. K. VASUDEV Aficroelectron J. 14 (6), 5 (1983) A new VLSI process was successfully developed for short-channel CMOS/SOS circuits on thin 0.3/~m epi layers. Two kinds of thin epi material were used. The first was grown by a standard CVD process, while the second was prepared by a double solid phase epitaxial regrowth (DSPE) technique. CMOS/SOS ring oscillators with effective channel lengths ranging from 0.7 to 1.3 # m were fabricated. Leakage currents below 3.0pA/ # m were achieved on both n-channel and p-channel devices. The DSPE material showed improvement in both mobility and speed. Step coverage by vapour deposited thin aluminum films
I. A. BLECH Solid St. TechnoL 123 (December 1983) Thin aluminum films used as electrical conductors for microelectronie applications are frequently deposited over substrates containing steps. As device geometries are reduced, the step-by-step spacing is often equal to or
even smaller than its height, and it becomes difficult to obtain a good conformal coverage of closely spaced steps. The origin of the features seen in aluminum profiles over steps for both point source planetary and sputtering deposition systems are reviewed. An optimum vapour distribution function for a sputtering source is calculated for best coverage of narrow lines. Designing solder paste materials to attach surface mounted devices
B A R B A R A ROOS-KOZEL SolidSt. Technol. 173 (October 1983) Thick film solder pastes have become increasingly sophisticated in their ability to meet stringent reliability and performance criteria. To design solder paste for attaching surface mounted devices, the fluxing agents, vehicle system, solder powder alloy, particle size and morphological characteristics, and metal loading must be consistent with the user's processing conditions and the desired product. The properties desired in the solder paste and each of its components are discussed, as are common engineering concerns such as achieving the desired fillet dimensions, ease of cleaning, and the elimination of solder balls and bridging.
A process for two-layer gold IC metalization D O U G SUMMERS SolidSt. Technol. 137 (December 1983) A two-layer gold metalization process is being developed for bipolar VLSI circuits. Interconnect lines on first and second levels are formed by selective electrochemical plating within the openings of a patterned photoresist layer. Metal pitch on both levels is 4/.tm (2 /.tm space, 2/.tm fine). Excellent metal step coverage is provided by the plating method. The interlayer dielectric consists of two films: plasma-deposited silicon nitride and plasma oxide. The nitride layer is thin (250 to 300 A); its purpose is to promote good adhesion between the gold and the plasma oxide. Minimum via size is 2.5 • 2.5 #m. The vias are formed by anisotropic etching in a commercially built single-wafer-per-cycle system. Examples are given of the special advantages and unique problems of this dual-layer process.
Quality solder paste systems for use in microclectronic applications RONALD P. ANJARD, St. Solid St. Techno1183 (October 1983) Solder paste is a critical material for the attachment of active and passive components in high technology and high reliability microelectronics and PCB applications (SMD and Capacitors). A broad understanding of the basic ingredients and the quality factors affecting the choice of the metallurgies available, methods of solder paste deposition, reflow techniques, from the most basic to the current state-of-the-art methods - and essential cleaning approaches are discussed. This paper serves as both a primer and an intermediate guide for understanding and using solder pastes.
47