Readout electronics for the ATLAS semiconductor tracker

Nuclear

Instruments

and Methods

in Physics

Research

A 386 (1997)

117-121

&METHODS

IN PHYSICS RyeFn

ELSEYIER

Readout electronics

for the ATLAS semiconductor

tracker

W.Dabrowski* CERN, Faculty

Geneva.

of Physics and Nuclear

Switzerland Techniques,

Cracow.

Poland

Abstract The binary readout architecture as a base-line and the analogue one as a fall-forward option have been adopted recently by the ATLAS SemiConductor Tracker (SCT) group for the readout of silicon strip detectors. A brief overview of different architectures considered before as well as the status of the binary readout development will be presented. A new idea of the binary readout architecture employing a dual threshold scheme will be discussed and new results obtained for the full analogue readout chip reahsed in the DMILL technology will be reported. PACS: 29.40.G~; 29.40.Wk. Keywords: Silicon tracking detectors;

Front-end

electronics

1. Introduction The requirements for the front-end electronics for silicon strip detectors in the ATLAS Semiconductor Tracker are far more advanced compared to any other presently running experiment. Three different readout architectures: binary, digital and analogue had been proposed for the readout of silicon strip detectors in the ATLAS SemiConductor Tracker in the past. The development along all these three lines had been carried out by the SDC, RD2 and RD20 collaborations [l-3]. The main features of these three different architectures have been discussed elsewhere [4] so here they will be reviewed only very briefly. The binary system which has been originally proposed for the SCT by the former SDC collaboration [5] employs a preamplifier-shaper circuit followed by a discriminator providing only binary yes/no information from the strips. The binary data is stored in a digital pipeline for the first trigger latency. For the data transmission off the detector a standard digital optical link can be used at a relatively moderate speed. This solution requires a front-end circuit of very high quality in terms of pedestals and gain matching. It should be stressed that the binary architecture must provide a good signal-to-noise ratio otherwise a high noise hit rate will force us to increase the discrimination threshold and so to cut the efficiency. A new idea of employing a dual threshold scheme has been proposed recently and will be discussed later on in this paper.

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In the digital scheme the digitisation is performed in the front-end chip and only digital data is transmitted off the detector. If one wants to keep a low number of optical links per module, only sparsified data can be sent off the detector. In addition to the front-end circuit and the analogue pipeline a fast low-power analogue-to-digital converter and a sparsification circuit should be integrated on the readout chip. In the AROW chip [6] developed recently the concept of the SVX development [7] has been employed. The Wilkinson type ADC allows digitisation of signals from all channels in parallel. Every channel is provided with an individual counter while the rest of ADC circuitry is common for all 128 channels in one chip. The zero suppression is performed on the digitised data. In the analogue architecture each channel of the frontend module contains a preamplifier-shaper circuitry followed by an analogue pipeline and an analogue multiplexer. The analogue data is transmitted from the detector via an analogue optical link and digitised in an ADC off the detector. In this scheme two important functions, i.e. sparsitication and digitisation, are moved off the detector but two other requirements are added: (a) to implement a fast analogue multiplexer running at 40 MHz on the frontend chip and (b) to use an analogue optical link of a very high bandwidth and a very big volume of data to be digitised. An advantage of this solution is a relatively simple front-end chip and a direct access to pulse height information. This in principle allows for more flexibility in data processing, in particular for corrections of the gain and pedestals variation. Therefore it is the safest system with respect to all possible problems which can occur while running the experiment. Presently the SCT32A chip

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developed along the development of the DMILL technology is the one following the line of full analogue architecture. Recently ATLAS SCT has adopted the binary readout architecture of silicon strip detectors as a baseline option and the analogue readout architecture as a possible faliforward solution. It should be mentioned that this choice was driven significantly by the cost issue since the binary architecture is expected to result in a lower cost compared to the digital and the analogue ones.

2. Front-end Given the SCT requirements concerning the detector capacitance and the peaking time as well as the constraint for the total power, the signal-to-noise ratio is a critical parameter for any of the readout architecture. There are three basic points which define the front-end, i.e. the type of the preamplifier together with the shaping method and the technology used. Several circuits have been proposed in the past, including the CMOS ones like ICON [8] or FELIX [9]. Recently, however, a transresistance bipolar preamplifier followed by an integrator has been adopted by all three readout architectures. This solution has been proved to be superior as far as the noise vs. power figure of merit is concerned. Several front-end chips with performance very close to those required for the ATLAS SCT have been developed in different bipolar technologies [IO- 131. Using a bipolar transistor as the input device one has to take into account a limitation due to shot noise of the base current. In principle a high collector current is required to obtain a large transconductance and to reduce the series voltage noise but there are two other effects which must be taken into account, namely: (a) a high collector current means a high base current and so high parallel current noise, (b) the series voltage noise is determined by two equivalent noise resistances; OS/g, which is inversely proportional to the collector current, and the base spread resistance rbbr depending on the transistor geometry. Typically, for the detector capacitances and the shaping time constant required for the SCT, the optimum collector current is in the range 100-200 PA which by the way suits well to the SCT preferences for a low power design.

3. Binary readout architecture As today, the binary readout architecture is adopted by the ATLAS SCT as a baseline and the project enters a phase of detailed engineering. The development is going along with two possible technological choices. One line following the original SDC project employs two different technologies, bipolar for the front-end chip and rad-hard

CMOS for the digital pipeline. Another line is based on the DMILL BiCMOS process developed recently which combines both, the radiation-hard CMOS devices and the high performance bipolar devices. This process offers a unique possibility of integrating the whole front-end circuitry in a single chip. For both technological options the same principle of the front-end circuit is used, however, the implementations are technology specific. For the pipeline two different concepts are explored: a pipeline based on the static RAM principle proposed by the former SDC collaboration and, a pipeline based on the multiplexed FIFO principle using the dynamic memory cells. The later one which has been developed in the DMILL process offers a higher density and lower power dissipation. There is a common effort to keep both developments fully compatible as far as the functionality and parameters are concerned so eventually any of these two options could work with the same readout system. The work on the final binary readout chip (ABC) is going on. The ABC chip, in addition to the main function which is the data storage for the first level trigger latency, will have implemented several other functions like additional derandomising buffer, data compression before transmission off the chip, providing the calibration pulses for the front-end circuit, providing the threshold for the discriminator, reporting on the transmission errors. Four modes of data read out will be possible: level mode, edge mode, hit mode in which supposed to be used in the beam test and diagnostic and the test mode for electrical testing of the chip.

3.1. Binary architecture

with dual threshold

As mentioned before, the performance of binary architecture relies very strongly on a good signal-to-noise ratio. On the other hand an increase of noise due to radiation damage to detectors and electronics is expected to occur during the experiment lifetime which may lead to a situation when discrimination threshold has to be increased to keep the noise occupancy at an acceptable level and this may result in losing the efficiency. An option of binary readout with dual threshold has been proposed in order to introduce an additional safety margin. This option offers also some improvements of spatial resolution and occupancy vs. efficiency figure of merit for the nominal signal-to-noise ratio as expected at the beginning of the experiment. The schematic diagram of the binary readout architecture with dual threshold is shown in Fig. 1. Each front-end channel contains two discriminators providing the HIGH and the LOW threshold respectively. The interstrip logic is composed of the AND gates providing the coincidences of the LOW outputs of neighbouring channels and the OR gates providing either the HIGH output or the coincidence

W. Dahrmvski

I Nucl. Insfr.

and Mcrh.

in Phys. Rus. A 386 ( 19971 I I7-

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Fig. 2. Comparison of the efficiency (top) and spatial resolution (bottom) for the binary readout with single and dual threshold. Signal-to-noise ratio of 1 I and a ratio of the two threshold settings HIGH/LOW of 1.5 are assumed.

Fig. 1. Schematic dual threshold.

diagram

output from two logic allows to pipeline the same One can consider

of the binary readout architecture

with

neighbouring channels. The interstrip keep the number channels of binary as the number of front-end amplifiers. several different scenarios for setting the HIGH and the LOW threshold. Since the threshold setting for the binary readout is driven primarily by a requirement of low noise occupancy one can use the same criteria for the LOW threshold so the rate of noise coincidences from the LOW outputs does not exceed the noise hit rate at the HIGH output. The measurements of noise coincidences in a binary readout system [ 141 show that in order to fultil the above criteria it would be required to keep the ratio HIGH/LOW at about 1.5. The effects of having the arm LOW threshold will be: (a) larger acceptance of lowest signals which mostly come from the hits with the charge shared equally between two neighbouring strips, (b) improved spatial resolution due to improved ratio of single strip to double strip hits. The expectation based on a qualitative analysis has been confirmed by the full simulation. The efficiency and spatial resolution obtained from full simulation of the SCT baseline strip detectors and readout electronics with single and with dual threshold are shown in Fig. 2. These results confirm a possible improvement of spatial resolution and a gain in terms of additional safety margin for the efficiency in the system with dual threshold. Similar results and conclusions have been obtained from the beam test data taken with an analogue readout electronics and analysed

according to the two binary algorithms. with dual threshold [ 151.

with single and

4. Analogue readout architecture The development of analogue readout architecture is focused recently on the option employing a fast transresistante bipolar preamplifier. This concept has been realised in the SCT32A demonstrator chip developed in the DMILL technology [16]. The primary goal of this work was to demonstrate the feasibility of building a radiation hard chip suitable for the analogue readout architecture for the SCT. The overall architecture employs a very straight forward concept of analogue readout based on a fast front-end amplifier followed by an integrator, providing a fast semigaussian shaping with the peaking time of 25 ns, and an output buffer. The peak values are sampled at 40 MHz rate and stored in the 112-cell deep analogue pipeline clocked with the same rate of 40 MHz as the analogue signal is sampled. This allows for a Tl trigger latency as big as 2.5 ps. The analogue values are stored in the cells pointed by the write pointer. The delay between the write pointer and trigger pointer is tuneable between 2 ~,s and 2.5 t.~s. The derandomising function is provided by an additional FIFO block in which up to 16 addresses of write pointers corresponding to 16 consecutive trigger signals can be stored. Once the trigger signal arrives the analogue values from the indicated 32-channel memory column are read out via the output multiplexer. In the present chip the output multiplexer has been designed to test the performance of the front-end and the analogue pipeline and it

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works up to 10 MHz. For the final design we aim for a 40 MHz multiplexing rate. The front-end circuit is based on a transresistance amplifier with a bipolar input transistor since for large detector capacitances and short shaping time constants bipolar devices offer a superior noise vs. power figure of merit. There are two critical issues concerning bipolar transistors which determine their low-noise and radiation hardness performance, i.e. the base spread resistance and the degradation of current gain factor p due to radiation damage. Based on the radiation test results of individual transistors we have chosen a geometry for the input device which provides a relatively low value (below 100 R) of the base spread resistance. The mean amplitude obtained for an 1 MIP input signal is of about 100 mVand is sufficiently high so that the noise figure obtained for the front-end amplifier will not be degraded by the contribution from other blocks. The storage capacitor of 310 tF for a single cell has been chosen. The output buffer of the front-end amplifier has a sufficient driving capability, so no additional write amplifier is needed. The read amplifier is based on a CMOS transconductance amplifier. The noise measurements performed on the front-end channels which were not connected to the pipeline gave the noise figure of ENC = 620 e- + 33 e- /pF for a collector current of 220 FA in the input transistor. For the above value of current in the input stage total power dissipation of the front-end amplifier, including the preamplifier, the integrator and the output buffer, is below 1.2 mW/channel. When performing the same measurements while reading the signal and noise via the complete readout chain, including the pipeline clocked at 40MHz and the multiplexer, a noise figure of 720 e- was obtained for zero input capacitance. The noise (without signal) was measured reading randomly the cells of the pipeline so the measured value includes fluctuations introduced by cell-to-cell variation of the storage capacitors. The obtained results indicate that additional sources of fluctuations, i.e. the pick-up of digital noise and the mismatching of pipeline storage cells, add only a marginal contribution to the noise of front-end amplifier. For the input capacitances of the order of 15 pF, as foreseen for the ATLAS SCT detectors, we do not expect any significant contribution from these additional noise sources. The testing of radiation hardness of the SCT32A chip is on the way. The chip was exposed to doses of 3 Mrad and IOMrad of ionising radiation in a “Co source. During irradiation the chip was biased as in nominal operational conditions. After gamma irradiation up to 10Mrad we have observed an increase of parallel noise due to decrease of the current gain p of the input transistor, as expected, and no changes in the noise slope. For front-end amplifier channels which are not connected to the pipeline we have obtained a noise figure of ENC = 840 e- + 33 e- IpF after 10 Mrad. This increase of the parallel noise is caused by an

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increase of the base current due to degradation of the current gain /I of the input transistor. For the input transistors at a collector current of 220 pA a degradation of fi from 120 to 80 was observed after IO Mrad of ionising radiation. No changes has been observed after 10Mrad in the operation of CMOS blocks, i.e. analogue pipeline, control logic and multiplexer. For irradiated chips a noise figure of 840e- for zero input capacitance has been measured via the complete readout chain while the chip was operating at nominal speed of 40MHz. The summary of different noise measurements for the SCT32A chip is shown in Fig. 3. The noise obtained with a 6 cm long strip detector connected to the chip shown on the plot is consistent with the other measurements. The results obtained so far indicate that the SCT32A chip meets all the basic requirements of the ATLAS SCT readout and offers appropriate radiation resistance with respect to ionising radiation. Neutron irradiation test will be performed soon since we expect an additional bulk damage effect in bipolar transistors which affect the current gain /3 due to minority carrier life time decrease caused by displacement damages.

5. Conclusions

The binary readout architecture has been adopted for the ATLAS SemiConductor Tracker as a baseline mostly on the basis of a possibly lowest cost. Analogue readout architecture is believed to be the safest one as far as aspects like robustness and performance monitoring are concerned, however, it may result in a higher cost of the

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overall readout system. presently this option is considered as a fall-forward solution. For both options, the binary and the analogue, all key blocks as well as semi-final chips have been successfully manufactured and tested. Preliminary radiation tests are quite promising, however, radiation hardness of fully engineered chips still has to be demonstrated.

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[7] T. Zimmerman et al.. IEEE Nuclear Science Record,Vol. 1, October 1994. p, 483.

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[8] S. Gadomski and P. Weilhammer, Nucl. Instr. and Meth. A 351 (1994) 201. [9] F. Anghinolfi et al., Trans. Nucl. Sci. NS-40(3) (1993) 271. [lo] W. Dabrowski et al., Nucl. Instr. and Meth. A 350 (1994) 548. E. Spencer et al., IEEE Trans. Nucl. Sci. NS-4?( I) (1995) 796. [12] 1. Kippnis et al., IEEE Trans. Nucl. Sci. NS-41(4) (1994) 1095. [ll]

[13] W. Dabrowski, J. Kaplon and P. Jarron, Proc. 1st Workshop on Electronics for LHC Experiments, CERN/LHCC/95-56, 1 October 1995. p. 47. [14] T. Dubbs, W. Kroeger and H.F.-W. Sadrozinski, Noise Occupancy in Single Channels and Adjacent Channel Coincidences in the Binary Readout Systems for Silicon Detectors, SCIPP Report, SCIPP 96/01, January 1996. [15] P. Allport et al., Studies of Resolution, Efficiency and Noise for Different Front End Threshold Algorithms using ATLAS-A Silicon Detector Test Beam Data. ATLAS Internal Note, INDET-NO-131, 24 April 1996. [I61 M. Dentan et al, Proc.

1st Workshop on Electronics for LHC 1 October 1995, p. 41.

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