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Real-time measurements on a four stage RSFQ-counter with Nb–Al2O3–Nb Josephson junctions
PII:
Applied Superconductivity Vol. 6, Nos 10±12, pp. 553±557, 1998 # 1999 Elsevier Science Ltd. All rights reserved Printed in Great Britain S0964-1807(99)00011-3 0964-1807/99 $ - see front matter
REAL-TIME MEASUREMENTS ON A FOUR STAGE RSFQCOUNTER WITH Nb±Al2O3±Nb JOSEPHSON JUNCTIONS W. BENZING*, M. BIEHL, E. CROCOLL, R. KOCH, M. NEUHAUS, T. SCHERER and W. JUTZI Institut fuÈr Elektrotechnische Grundlagen der Informatik, University of Karlsruhe, D-76187 Karlsruhe, Germany AbstractÐRSFQ-toggle-¯ip¯ops with a SFQ-trigger circuit a Josephson transmission line at the input and a SFQ/dc-circuit at the output of each stage are implemented in the Nb±Al2O3±Nb Josephson junction technology on a single chip having coplanar wave guides at input and output. The counter is tested successfully at 4.2 K via coplanar/coaxial transitions using a bit pattern generator and a digital oscilloscope at room temperature up to fI 12 GHz pulse repetition frequency at the input. The highest test frequency fI is limited by the available pattern generator. # 1999 Elsevier Science Ltd. All rights reserved
INTRODUCTION
Single ¯ux quantum circuits may be operated at low power dissipation of 1 mW per gate and high clock frequencies in the microwave and mm frequency range [1, 2] up to about one third of the plasma frequency [3]. Testing and interfacing of RSFQ-circuits with room temperature electronics at high speed is essential for many applications. Unfortunately, high speed test equipment with clock frequencies in the 20 GHz range is very expensive and available in only a few laboratories. Therefore, basic interface properties at input and output, such as coplanar interconnections between chip and test jig board, coplanar to coaxial transitions, line matching, ground noise are investigated up to about 2 GHz with toggle-¯ip¯ops in the Nb technology. CIRCUIT AND TEST JIG TECHNOLOGY
The test vehicle is a four stage RSFQ-toggle-¯ip¯op counter with the equivalent circuit of Fig. 1, where the parasitic inductances have been omitted. At the input there is an integrated 50 O resistor (1) to match the long incoming line, a Josephson transmission line (2), a ®rst RSFQ-toggle-¯ip¯op with SFQ/dc output U1 (3), a Josephson transmission line (4), the second RSFQ-toggle-¯ip¯op (5), etc. The numbers in the brackets of the schematic in Fig. 1(a) and in the micrograph of Fig. 1(b) correspond to each other. The circuit is fabricated in the Nb technology with Nb±Al2O3±Nb Josephson junctions and PdAu resistors on a silicon wafer [4]. The Josephson current density is jmax = 1 kA/cm2 and the minimum line width Lmin = 3.5 mm. The layout has Josephson junctions of dierent areas. Margins of the subcircuit comprising a toggle-¯ip¯op, a Josephson transmission line and a trigger circuit including their parasitics have been optimised [5]. The simulated global margins are 220%. The circuit on a 6 6 mm2 chip has a matched 50 O symmetrical coplanar input line (UG) and one symmetrical coplanar output line (U1) [6]. The lower frequency outputs U2, U3 and U4 have asymmetrical coplanar lines with only two strips to reduce the number of required pads with areas 200 300 mm. The chip is inserted into an accurately cut hole of the board with coplanar wave guides (CPW) as shown in the micrograph of Fig. 2. The gap between chip and board should be as small as possible to achieve a small re¯ection factor at the bonding wires. Five ultrasonically placed aluminum bond wires (25 mm) interconnect a symmetrical CPW between chip and board. Transitions between CPW and ¯exible coaxial cables are arranged on *Corresponding author. 553
554
W. BENZING et al.
Fig. 1. Four-stage RSFQ toggle ¯ip¯op counter with a trigger circuit at the input and SFQ/dc circuits at each stage output: (a) equivalent circuit without parasitics and with the input at the right. (b) Micrograph of the chip without bonding wires
the board. SMA-coaxial connectors allow for an easy removing of the test jig. The maximum re¯ection factor on the way from room temperature to the 50 O input resistor on the chip is below 7%. PULSE MEASUREMENTS AT 4.2 K
Low frequency measurements, e.g. at 0.5 MHz are useful to adjust the dc bias currents and to check the expected logic functions. A periodic input pulse train in the return to zero (RZ) mode at a rate rI = 0.5 Mbit/s with an amplitude UG = 20 mV is shown in Fig. 3. The input voltage UG must be large to get trigger currents of 400 mA in the order of the junction maximum
Fig. 2. Micrograph of the RSFQ-counter chip with aluminum wires between coplanar lines on the chip and the test jig board
Four stage RSFQ-counter
555
Fig. 3. Measurements with a 1 MHz low-pass bandwidth at the four stage circuit of Fig. 1 as a frequency divider: (a) periodic input pulses UG with return to zero (RZ) at fI = 0.5 MHz. (b) Output U3. (c) Output U4
Josephson current. Since it is 100 larger than the standard output voltage of 200 mV, input to output interference may occur, especially at high clock frequencies. The output pulse rate at the fourth stage in Fig. 3 is 16 smaller than the input rate, as wanted. Owing to an ampli®er 3 dB bandwidth of only 1 MHz disturbing high frequency components are not displayed. To reduce disturb signals at microwave clock frequencies the voltage UD versus ground of a dummy ¯ip¯op without bias currents is applied to input B and the disturbed signal U1 versus ground to input A of the oscilloscope where the dierence A minus B is displayed. Ampli®cation versus frequency and delay for both channels A and B must be carefully adjusted. In this way the measured results without averaging in Fig. 4 are obtained. The almost sinusoidal input signal at fI = 0.9 GHz is correctly divided by 23 at output U3 as shown in Fig. 4(a). Output U4 is not displayed as its frequency is below the lower limit frequency of the ampli®er, fAL = 100 MHz. With an input frequency fI = 1.8 GHz the output frequency at U4 is f4 = 112.5 MHz just on top of fAL. The input voltage amplitude is as large as in Fig. 4(a), but only appears to be smaller on the screen owing to the ®nite number of displayed points. Toggle-¯ip¯ops operate as frequency dividers in a larger frequency range than as a digital counter with aperiodic arrival of zeros and ones. Although the simulated maximum frequency for digital operation fD 1 60 GHz for jmax = 1 kA/cm2 [3] is suciently larger than the presently tested frequency range, measurements near the maximum clock rate rI = 0.9 Gbit/s in the return to zero mode (RZ) with a 16-bit word generator of HP 8133 are performed. The input pulse sequence is shown in Fig. 5(a). The output U2 is averaged 32 and happened to be delayed with respect to the input train. The traces in Fig. 5(b±d) are in phase. To ease up the interpretation at the output of the SFQ/dc-converter the schematics at the ®rst and second output U1S and U2S are represented in Fig. 5(b) and (d). The wanted logic function can clearly be detected in the trace of U2. However, the shape (roof) of the longest output pulses is deformed because the lowest frequency of the input and output signal given by the word length in the RZ mode: 900 MHz/16 = 56 MHz is already below the lower 3 dB limit frequency of the used ampli®er fAL = 100 MHz. Expensive microwave bandwidth ampli®ers with fAL = 10 MHz have not yet been available. BIT ERROR RATE ESTIMATION
Bit error rate measurements, e.g. of glass ®bre communication links, are usually performed in the non return to zero mode (NRZ) up to about 20 Gbit/s with semiconductor equipment at
556
W. BENZING et al.
Fig. 4. Measurements without averaging at the four-stage circuit of Fig. 1 as a frequency divider: (a) periodic input UG (with RZ) at fI = 900 MHz and output U3 of the third stage at f3 = 112.5 MHz slightly on top of the ampli®er lower cut-o frequency. (b) Periodic input UG at fI = 1.8 GHz and output U4 of the fourth stage at f3 = 112.5 MHz
room temperature [7, 8] where the length of the pseudo random bit sequence (PRBS) input pattern may be as large as 231ÿ11 2 109. Since this very expensive equipment has not yet been available, a simpli®ed experiment has been performed with the 32 bit NRZ word: 11010101010100011000111010111000 at a rate rI = 1.8 GHz. The oscilloscope triggered bitwise
Fig. 5. Measurements after averaging 32 at the circuit of Fig. 1 as a four stage binary counter: (a) RZ input pulse word UG with zeros and ones at rI = 0.9 Gbit/s. (b) Schematic of the ®rst stage output U1S delayed with respect to the ®rst trace. (c) Measured output of the second stage. (d) Schematic of the second stage output U2S
Four stage RSFQ-counter
557
Fig. 6. Eye-diagram of the output U1 of the ®rst stage at the circuit of Fig. 1
yields the eye-diagram at the output of the ®rst stage in Fig. 6(a) at a reduced bandwidth of 2 GHz after 100 s. The same experiment has been repeated with all bias currents of the RSFQcircuit switched-o. The result is displayed in Fig. 6(b) with a 32 NRZ input word corresponding to a bitwise triggering at rI = 1.8 Gbit/s after a measurement duration of 100 s. The standard deviation of the total noise at room temperature s 1 83 mV/6 114 mV includes the noise of the oscilloscope, ampli®er, 50 O transmission line and of the RSFQ-circuit. It would correspond to three times the white noise of a 50 O resistor with a bandwidth B = 2 GHz at 4.2 K. A ®rst approximation of the bit error rate (BER) is found with Q = (m1ÿm0)/(s1 + s2) p and BER 1 1/Q 2p exp(ÿQ2/2), where are the average values of the ones and zeros: m1, m0 and the corresponding standard deviations: s1, s2 [9]. A factor Q 17 would yield BER 1 1 10ÿ12. Larger BER are expected for longer PRBS. CONCLUSION
Real-time measurements of RSFQ-circuits at microwave clock frequencies require a careful design of input and output interfaces. The deduced BER 1 10ÿ12 at rI = 1.8 GHz is promising, but must be checked by more accurate measurements and at higher rates [8]. AcknowledgementsÐThis work was supported in part by the German BMBF under Grant No. 13 N 6324 2.
REFERENCES 1. K. Likharev, Recent progress and prospects of superconductor digital technology, FEB report, January, 1997. 2. M. Feldman, Digital applications of Josephson junctions, Progress of Theoretical Physics, supplement (Japan) `Physics and Applications of Mesoscopic Josephson junctions', 1998. 3. W. Benzing and W. Jutzi, Digital operation range of RSFQ toggle-¯ip¯op, Cryogenics, 37(8), 453±460, (1997). 4. R. Dolata, M. Neuhaus and W. Jutzi, Tunnel barrier growth dynamics of Nb/AlOx±Al/Nb Nb/AlNx±Al/Nb Josephson junctions, Physica C 241, 25±29 (1995). 5. R. Koch and W. Benzing, Multidimensional parameter optimisation of SFQ-circuits, ISEC `97, Berlin. 6. M. Biehl, E. Crocoll, M. Neuhaus, T. Scherer and W. Jutzi, A superconducting 4 bit instantaneous frequency meter at 10 GHz with integrated resistors and bridges, ISEC `97, Berlin. 7. O. A. Mukhanov, S. V. Rylov, D. V. Gaidarenko, N. Dubash and V. V. Borzenets, Josephson output interfaces for RSFQ circuits, EHA-5 Appl. Supercond. Conf. Pittsburgh `96. 8. BER systems: Hewlett Packard 71600, Anritsu MP 1755/6 A. 9. G. Grau, Optische Nachrichtentechnik. Springer-Verlag 1981, p. 523.
Applied Superconductivity Vol. 6, Nos 10±12, pp. 553±557, 1998 # 1999 Elsevier Science Ltd. All rights reserved Printed in Great Britain S0964-1807(99)00011-3 0964-1807/99 $ - see front matter
REAL-TIME MEASUREMENTS ON A FOUR STAGE RSFQCOUNTER WITH Nb±Al2O3±Nb JOSEPHSON JUNCTIONS W. BENZING*, M. BIEHL, E. CROCOLL, R. KOCH, M. NEUHAUS, T. SCHERER and W. JUTZI Institut fuÈr Elektrotechnische Grundlagen der Informatik, University of Karlsruhe, D-76187 Karlsruhe, Germany AbstractÐRSFQ-toggle-¯ip¯ops with a SFQ-trigger circuit a Josephson transmission line at the input and a SFQ/dc-circuit at the output of each stage are implemented in the Nb±Al2O3±Nb Josephson junction technology on a single chip having coplanar wave guides at input and output. The counter is tested successfully at 4.2 K via coplanar/coaxial transitions using a bit pattern generator and a digital oscilloscope at room temperature up to fI 12 GHz pulse repetition frequency at the input. The highest test frequency fI is limited by the available pattern generator. # 1999 Elsevier Science Ltd. All rights reserved
INTRODUCTION
Single ¯ux quantum circuits may be operated at low power dissipation of 1 mW per gate and high clock frequencies in the microwave and mm frequency range [1, 2] up to about one third of the plasma frequency [3]. Testing and interfacing of RSFQ-circuits with room temperature electronics at high speed is essential for many applications. Unfortunately, high speed test equipment with clock frequencies in the 20 GHz range is very expensive and available in only a few laboratories. Therefore, basic interface properties at input and output, such as coplanar interconnections between chip and test jig board, coplanar to coaxial transitions, line matching, ground noise are investigated up to about 2 GHz with toggle-¯ip¯ops in the Nb technology. CIRCUIT AND TEST JIG TECHNOLOGY
The test vehicle is a four stage RSFQ-toggle-¯ip¯op counter with the equivalent circuit of Fig. 1, where the parasitic inductances have been omitted. At the input there is an integrated 50 O resistor (1) to match the long incoming line, a Josephson transmission line (2), a ®rst RSFQ-toggle-¯ip¯op with SFQ/dc output U1 (3), a Josephson transmission line (4), the second RSFQ-toggle-¯ip¯op (5), etc. The numbers in the brackets of the schematic in Fig. 1(a) and in the micrograph of Fig. 1(b) correspond to each other. The circuit is fabricated in the Nb technology with Nb±Al2O3±Nb Josephson junctions and PdAu resistors on a silicon wafer [4]. The Josephson current density is jmax = 1 kA/cm2 and the minimum line width Lmin = 3.5 mm. The layout has Josephson junctions of dierent areas. Margins of the subcircuit comprising a toggle-¯ip¯op, a Josephson transmission line and a trigger circuit including their parasitics have been optimised [5]. The simulated global margins are 220%. The circuit on a 6 6 mm2 chip has a matched 50 O symmetrical coplanar input line (UG) and one symmetrical coplanar output line (U1) [6]. The lower frequency outputs U2, U3 and U4 have asymmetrical coplanar lines with only two strips to reduce the number of required pads with areas 200 300 mm. The chip is inserted into an accurately cut hole of the board with coplanar wave guides (CPW) as shown in the micrograph of Fig. 2. The gap between chip and board should be as small as possible to achieve a small re¯ection factor at the bonding wires. Five ultrasonically placed aluminum bond wires (25 mm) interconnect a symmetrical CPW between chip and board. Transitions between CPW and ¯exible coaxial cables are arranged on *Corresponding author. 553
554
W. BENZING et al.
Fig. 1. Four-stage RSFQ toggle ¯ip¯op counter with a trigger circuit at the input and SFQ/dc circuits at each stage output: (a) equivalent circuit without parasitics and with the input at the right. (b) Micrograph of the chip without bonding wires
the board. SMA-coaxial connectors allow for an easy removing of the test jig. The maximum re¯ection factor on the way from room temperature to the 50 O input resistor on the chip is below 7%. PULSE MEASUREMENTS AT 4.2 K
Low frequency measurements, e.g. at 0.5 MHz are useful to adjust the dc bias currents and to check the expected logic functions. A periodic input pulse train in the return to zero (RZ) mode at a rate rI = 0.5 Mbit/s with an amplitude UG = 20 mV is shown in Fig. 3. The input voltage UG must be large to get trigger currents of 400 mA in the order of the junction maximum
Fig. 2. Micrograph of the RSFQ-counter chip with aluminum wires between coplanar lines on the chip and the test jig board
Four stage RSFQ-counter
555
Fig. 3. Measurements with a 1 MHz low-pass bandwidth at the four stage circuit of Fig. 1 as a frequency divider: (a) periodic input pulses UG with return to zero (RZ) at fI = 0.5 MHz. (b) Output U3. (c) Output U4
Josephson current. Since it is 100 larger than the standard output voltage of 200 mV, input to output interference may occur, especially at high clock frequencies. The output pulse rate at the fourth stage in Fig. 3 is 16 smaller than the input rate, as wanted. Owing to an ampli®er 3 dB bandwidth of only 1 MHz disturbing high frequency components are not displayed. To reduce disturb signals at microwave clock frequencies the voltage UD versus ground of a dummy ¯ip¯op without bias currents is applied to input B and the disturbed signal U1 versus ground to input A of the oscilloscope where the dierence A minus B is displayed. Ampli®cation versus frequency and delay for both channels A and B must be carefully adjusted. In this way the measured results without averaging in Fig. 4 are obtained. The almost sinusoidal input signal at fI = 0.9 GHz is correctly divided by 23 at output U3 as shown in Fig. 4(a). Output U4 is not displayed as its frequency is below the lower limit frequency of the ampli®er, fAL = 100 MHz. With an input frequency fI = 1.8 GHz the output frequency at U4 is f4 = 112.5 MHz just on top of fAL. The input voltage amplitude is as large as in Fig. 4(a), but only appears to be smaller on the screen owing to the ®nite number of displayed points. Toggle-¯ip¯ops operate as frequency dividers in a larger frequency range than as a digital counter with aperiodic arrival of zeros and ones. Although the simulated maximum frequency for digital operation fD 1 60 GHz for jmax = 1 kA/cm2 [3] is suciently larger than the presently tested frequency range, measurements near the maximum clock rate rI = 0.9 Gbit/s in the return to zero mode (RZ) with a 16-bit word generator of HP 8133 are performed. The input pulse sequence is shown in Fig. 5(a). The output U2 is averaged 32 and happened to be delayed with respect to the input train. The traces in Fig. 5(b±d) are in phase. To ease up the interpretation at the output of the SFQ/dc-converter the schematics at the ®rst and second output U1S and U2S are represented in Fig. 5(b) and (d). The wanted logic function can clearly be detected in the trace of U2. However, the shape (roof) of the longest output pulses is deformed because the lowest frequency of the input and output signal given by the word length in the RZ mode: 900 MHz/16 = 56 MHz is already below the lower 3 dB limit frequency of the used ampli®er fAL = 100 MHz. Expensive microwave bandwidth ampli®ers with fAL = 10 MHz have not yet been available. BIT ERROR RATE ESTIMATION
Bit error rate measurements, e.g. of glass ®bre communication links, are usually performed in the non return to zero mode (NRZ) up to about 20 Gbit/s with semiconductor equipment at
556
W. BENZING et al.
Fig. 4. Measurements without averaging at the four-stage circuit of Fig. 1 as a frequency divider: (a) periodic input UG (with RZ) at fI = 900 MHz and output U3 of the third stage at f3 = 112.5 MHz slightly on top of the ampli®er lower cut-o frequency. (b) Periodic input UG at fI = 1.8 GHz and output U4 of the fourth stage at f3 = 112.5 MHz
room temperature [7, 8] where the length of the pseudo random bit sequence (PRBS) input pattern may be as large as 231ÿ11 2 109. Since this very expensive equipment has not yet been available, a simpli®ed experiment has been performed with the 32 bit NRZ word: 11010101010100011000111010111000 at a rate rI = 1.8 GHz. The oscilloscope triggered bitwise
Fig. 5. Measurements after averaging 32 at the circuit of Fig. 1 as a four stage binary counter: (a) RZ input pulse word UG with zeros and ones at rI = 0.9 Gbit/s. (b) Schematic of the ®rst stage output U1S delayed with respect to the ®rst trace. (c) Measured output of the second stage. (d) Schematic of the second stage output U2S
Four stage RSFQ-counter
557
Fig. 6. Eye-diagram of the output U1 of the ®rst stage at the circuit of Fig. 1
yields the eye-diagram at the output of the ®rst stage in Fig. 6(a) at a reduced bandwidth of 2 GHz after 100 s. The same experiment has been repeated with all bias currents of the RSFQcircuit switched-o. The result is displayed in Fig. 6(b) with a 32 NRZ input word corresponding to a bitwise triggering at rI = 1.8 Gbit/s after a measurement duration of 100 s. The standard deviation of the total noise at room temperature s 1 83 mV/6 114 mV includes the noise of the oscilloscope, ampli®er, 50 O transmission line and of the RSFQ-circuit. It would correspond to three times the white noise of a 50 O resistor with a bandwidth B = 2 GHz at 4.2 K. A ®rst approximation of the bit error rate (BER) is found with Q = (m1ÿm0)/(s1 + s2) p and BER 1 1/Q 2p exp(ÿQ2/2), where are the average values of the ones and zeros: m1, m0 and the corresponding standard deviations: s1, s2 [9]. A factor Q 17 would yield BER 1 1 10ÿ12. Larger BER are expected for longer PRBS. CONCLUSION
Real-time measurements of RSFQ-circuits at microwave clock frequencies require a careful design of input and output interfaces. The deduced BER 1 10ÿ12 at rI = 1.8 GHz is promising, but must be checked by more accurate measurements and at higher rates [8]. AcknowledgementsÐThis work was supported in part by the German BMBF under Grant No. 13 N 6324 2.
REFERENCES 1. K. Likharev, Recent progress and prospects of superconductor digital technology, FEB report, January, 1997. 2. M. Feldman, Digital applications of Josephson junctions, Progress of Theoretical Physics, supplement (Japan) `Physics and Applications of Mesoscopic Josephson junctions', 1998. 3. W. Benzing and W. Jutzi, Digital operation range of RSFQ toggle-¯ip¯op, Cryogenics, 37(8), 453±460, (1997). 4. R. Dolata, M. Neuhaus and W. Jutzi, Tunnel barrier growth dynamics of Nb/AlOx±Al/Nb Nb/AlNx±Al/Nb Josephson junctions, Physica C 241, 25±29 (1995). 5. R. Koch and W. Benzing, Multidimensional parameter optimisation of SFQ-circuits, ISEC `97, Berlin. 6. M. Biehl, E. Crocoll, M. Neuhaus, T. Scherer and W. Jutzi, A superconducting 4 bit instantaneous frequency meter at 10 GHz with integrated resistors and bridges, ISEC `97, Berlin. 7. O. A. Mukhanov, S. V. Rylov, D. V. Gaidarenko, N. Dubash and V. V. Borzenets, Josephson output interfaces for RSFQ circuits, EHA-5 Appl. Supercond. Conf. Pittsburgh `96. 8. BER systems: Hewlett Packard 71600, Anritsu MP 1755/6 A. 9. G. Grau, Optische Nachrichtentechnik. Springer-Verlag 1981, p. 523.