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Realization of two-dimensional optical devices using photonic band gap structures on silicon-on-insulator
Microelectronic Engineering 61–62 (2002) 545–548 www.elsevier.com / locate / mee
Realization of two-dimensional optical devices using photonic band gap structures on silicon-on-insulator T. Charvolin a , *, E. Hadji a , E. Picard a , M. Zelsman a , M. Assous b , B. Dalzotto b , ´ c , C. Seassal c M.E. Nier b , S. Tedesco b , X. Letartre c , P. Rojo-Romeo a
´ ` Condensee ´ , CEA-Grenoble, Departement de Recherche Fondamentale sur la Matiere F-38054 Grenoble Cedex 9, France b ´ des Technologies du Silicium, CEA-Grenoble, F-38054 Grenoble Cedex 9, France LETI, Departement c Ecole Centrale de Lyon, LEOM, BP 163, F-69131 Ecully, France
Abstract We present results on the fabrication of optical devices based on photonic crystals on silicon-on insulator substrates. Guides, microcavities, add-drop filters have been obtained with process compatible with CMOS technologies. 2002 Elsevier Science B.V. All rights reserved. Keywords: Silicon-on-insulator; CMOS technology; Optical device; Photonic crystal
As processors density increases, intra- and inter-chip electrical connections are going to face limitations in term of miniaturization, dissipated energy and frequency bandwidth. Optics could be an alternative if we realize light emitters, guides and receptors using CMOS compatible technologies by taking advantage of photonic crystal (PC) structures and silicon-on-insulator (SOI) substrates. The photonic crystal is made of periodic variations of optical index which act on photons as electrical potential variations act on electrons in semiconductors and create forbidden band for photon propagation within the structure [1]. Benefit is the capability to confine or guide light; in particular PCs are expected to guide light following sharper curvatures than refractive optics could do and thus to allow a stronger miniaturization. Concerning SOI, it presents several advantages: respective indexes of Si and SiO 2 allow planar light confinement; Si is transparent at telecom wavelengths; SiO 2 is an efficient barrier against diffusion of carriers which are injected or photogenerated in the Si layer. We confine photons in SOI horizontal plan and guide or confine them within this plan using PC structures. For example, concerning microsources, an objective is to combine 2D confinement of SOI substrates with 1D confinement of photonic crystals based planar microcavities in order to realize a quasi 3D * Corresponding author. E-mail address: [email protected] (T. Charvolin). 0167-9317 / 02 / $ – see front matter 2002 Elsevier Science B.V. All rights reserved. PII: S0167-9317( 02 )00480-X
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T. Charvolin et al. / Microelectronic Engineering 61 – 62 (2002) 545 – 548
Fig. 1. Cavity in a 8-mm wide guide. The two mirrors are defined by photonic crystals (250-nm holes and 400-nm period).
confinement. Those so-called optical boxes are expected to enhance light emission according to the Purcell effect [2,3]. From practical point of view, considering wavelengths and optical indexes of used materials, the characteristic dimensions of PC, holes diameter and period, are of the order of a few hundreds of nanometers, that means fully achievable by CMOS technology. Devices as guides, linear microcavities and add-drop filters have been designed for 1.3-mm wavelength (Figs. 1–3). PC used in that case are made of 0.25-mm holes with a period of 0.4 mm. Three kinds of optical boxes prefiguring microsources have been designed for three different wavelengths, 1.14, 1.32 and 1.54 mm (Fig. 4). The first one corresponds to the emission at the band gap of silicon; the following two are the Telecom wavelengths, 1.54 mm also corresponding to the transition of erbium–oxygen complexes in silicon. PC characteristic dimensions are, respectively, 0.27 and 0.37 mm (diameter and period) for l 5 1.14 mm, 0.33 and 0.45-mm for l 5 1.32 mm and 0.39 and
Fig. 2. Linear cavity: 100-nm holes in a 300-nm wide guide.
T. Charvolin et al. / Microelectronic Engineering 61 – 62 (2002) 545 – 548
547
Fig. 3. Add-drop device defined by a photonic crystal (300-nm wide guide, 250-nm holes, 400-nm period).
0.52 mm for l 5 1.54 mm. Planar cavities are made by defects in periodical array of PC, those defects being missing holes. Two types of cavities have been designed in that way, a single missing hole cavity (H1) and a larger one, where missing holes describe a hexagon whose side is ten periods long (H10). In order to increase the emitted signal, the sample is covered by a periodic array (inside PC array) of those H1 or H10 cavities. Concerning PC based devices, the fabrication process is as follows (Fig. 5): patterns were realized on 8-inch SOI substrates by conventional CMOS technologies, mainly e-beam lithography and plasma etching. We used SOITEC’s standard SOI substrates: 200-nm monocrystalline silicon film on 400-nm buried oxide film. First, a 30-nm thick thermal oxide is grown. This oxide film is important in term of interface quality and will also be used as a hard mask for silicon etching. For both resolution and writing time consideration patterns are transfered into the oxide film within a 2-step e-beam lithography plus oxide etching. The first one concerns the lines and the areas where are located the photonic crystals. It is performed using a negative resist. The second one is dedicated to the photonic crystals holes and is performed using a positive resist. Those two levels are aligned on alignment marks previously etched. The oxide etching plasma is a C 4 F 8 1CO1O 2 mixture. Once patterns have
Fig. 4. H10 planar cavity designed for l 5 1.54 mm: 390-nm diameter and 520-nm period.
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T. Charvolin et al. / Microelectronic Engineering 61 – 62 (2002) 545 – 548
Fig. 5. Process diagram. 1, SOI substrate; 2, thermal oxidation; 3, lithography plus oxide etching: lines; 4, lithography plus oxide etching: holes; 5, silicon etching.
been transfered into the oxide, silicon is etched using a Cl 2 1HBr plasma. A 5-nm thermal oxide and an annealing under N 2 H 2 atmosphere are performed for passivation. The process is similar for optical boxes, although only photonic crystal holes are needed, which means only one lithography plus oxide etching level is performed. In conclusion, we have demonstrated the fabrication of photonic crystal based devices, using CMOS technology. Devices such as guides, cavities, add-drop filters and so-called optical boxes have been obtained.
References [1] E. Yablonovitch, Phys. Rev. Lett. 58 (1987) 2059. [2] E.M. Purcell, Phys. Rev. 69 (1946) 681. [3] M. Boroditsky et al., J. Lightwave Technol. 17 (1999) 2096.
Realization of two-dimensional optical devices using photonic band gap structures on silicon-on-insulator T. Charvolin a , *, E. Hadji a , E. Picard a , M. Zelsman a , M. Assous b , B. Dalzotto b , ´ c , C. Seassal c M.E. Nier b , S. Tedesco b , X. Letartre c , P. Rojo-Romeo a
´ ` Condensee ´ , CEA-Grenoble, Departement de Recherche Fondamentale sur la Matiere F-38054 Grenoble Cedex 9, France b ´ des Technologies du Silicium, CEA-Grenoble, F-38054 Grenoble Cedex 9, France LETI, Departement c Ecole Centrale de Lyon, LEOM, BP 163, F-69131 Ecully, France
Abstract We present results on the fabrication of optical devices based on photonic crystals on silicon-on insulator substrates. Guides, microcavities, add-drop filters have been obtained with process compatible with CMOS technologies. 2002 Elsevier Science B.V. All rights reserved. Keywords: Silicon-on-insulator; CMOS technology; Optical device; Photonic crystal
As processors density increases, intra- and inter-chip electrical connections are going to face limitations in term of miniaturization, dissipated energy and frequency bandwidth. Optics could be an alternative if we realize light emitters, guides and receptors using CMOS compatible technologies by taking advantage of photonic crystal (PC) structures and silicon-on-insulator (SOI) substrates. The photonic crystal is made of periodic variations of optical index which act on photons as electrical potential variations act on electrons in semiconductors and create forbidden band for photon propagation within the structure [1]. Benefit is the capability to confine or guide light; in particular PCs are expected to guide light following sharper curvatures than refractive optics could do and thus to allow a stronger miniaturization. Concerning SOI, it presents several advantages: respective indexes of Si and SiO 2 allow planar light confinement; Si is transparent at telecom wavelengths; SiO 2 is an efficient barrier against diffusion of carriers which are injected or photogenerated in the Si layer. We confine photons in SOI horizontal plan and guide or confine them within this plan using PC structures. For example, concerning microsources, an objective is to combine 2D confinement of SOI substrates with 1D confinement of photonic crystals based planar microcavities in order to realize a quasi 3D * Corresponding author. E-mail address: [email protected] (T. Charvolin). 0167-9317 / 02 / $ – see front matter 2002 Elsevier Science B.V. All rights reserved. PII: S0167-9317( 02 )00480-X
546
T. Charvolin et al. / Microelectronic Engineering 61 – 62 (2002) 545 – 548
Fig. 1. Cavity in a 8-mm wide guide. The two mirrors are defined by photonic crystals (250-nm holes and 400-nm period).
confinement. Those so-called optical boxes are expected to enhance light emission according to the Purcell effect [2,3]. From practical point of view, considering wavelengths and optical indexes of used materials, the characteristic dimensions of PC, holes diameter and period, are of the order of a few hundreds of nanometers, that means fully achievable by CMOS technology. Devices as guides, linear microcavities and add-drop filters have been designed for 1.3-mm wavelength (Figs. 1–3). PC used in that case are made of 0.25-mm holes with a period of 0.4 mm. Three kinds of optical boxes prefiguring microsources have been designed for three different wavelengths, 1.14, 1.32 and 1.54 mm (Fig. 4). The first one corresponds to the emission at the band gap of silicon; the following two are the Telecom wavelengths, 1.54 mm also corresponding to the transition of erbium–oxygen complexes in silicon. PC characteristic dimensions are, respectively, 0.27 and 0.37 mm (diameter and period) for l 5 1.14 mm, 0.33 and 0.45-mm for l 5 1.32 mm and 0.39 and
Fig. 2. Linear cavity: 100-nm holes in a 300-nm wide guide.
T. Charvolin et al. / Microelectronic Engineering 61 – 62 (2002) 545 – 548
547
Fig. 3. Add-drop device defined by a photonic crystal (300-nm wide guide, 250-nm holes, 400-nm period).
0.52 mm for l 5 1.54 mm. Planar cavities are made by defects in periodical array of PC, those defects being missing holes. Two types of cavities have been designed in that way, a single missing hole cavity (H1) and a larger one, where missing holes describe a hexagon whose side is ten periods long (H10). In order to increase the emitted signal, the sample is covered by a periodic array (inside PC array) of those H1 or H10 cavities. Concerning PC based devices, the fabrication process is as follows (Fig. 5): patterns were realized on 8-inch SOI substrates by conventional CMOS technologies, mainly e-beam lithography and plasma etching. We used SOITEC’s standard SOI substrates: 200-nm monocrystalline silicon film on 400-nm buried oxide film. First, a 30-nm thick thermal oxide is grown. This oxide film is important in term of interface quality and will also be used as a hard mask for silicon etching. For both resolution and writing time consideration patterns are transfered into the oxide film within a 2-step e-beam lithography plus oxide etching. The first one concerns the lines and the areas where are located the photonic crystals. It is performed using a negative resist. The second one is dedicated to the photonic crystals holes and is performed using a positive resist. Those two levels are aligned on alignment marks previously etched. The oxide etching plasma is a C 4 F 8 1CO1O 2 mixture. Once patterns have
Fig. 4. H10 planar cavity designed for l 5 1.54 mm: 390-nm diameter and 520-nm period.
548
T. Charvolin et al. / Microelectronic Engineering 61 – 62 (2002) 545 – 548
Fig. 5. Process diagram. 1, SOI substrate; 2, thermal oxidation; 3, lithography plus oxide etching: lines; 4, lithography plus oxide etching: holes; 5, silicon etching.
been transfered into the oxide, silicon is etched using a Cl 2 1HBr plasma. A 5-nm thermal oxide and an annealing under N 2 H 2 atmosphere are performed for passivation. The process is similar for optical boxes, although only photonic crystal holes are needed, which means only one lithography plus oxide etching level is performed. In conclusion, we have demonstrated the fabrication of photonic crystal based devices, using CMOS technology. Devices such as guides, cavities, add-drop filters and so-called optical boxes have been obtained.
References [1] E. Yablonovitch, Phys. Rev. Lett. 58 (1987) 2059. [2] E.M. Purcell, Phys. Rev. 69 (1946) 681. [3] M. Boroditsky et al., J. Lightwave Technol. 17 (1999) 2096.