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Recent Advances in GaAs Dynamic Memories
.
ADVANCES IN ELECTRONICS AND ELECTRON PHYSICS VOL . 86
Recent Advances in GaAs Dynamic Memories JAMES A . COOPER. JR . School of Electrical Engineering. Purdue University. West Lafayette. IN
I . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . A . Introduction and Background . . . . . . . . . . . . . . . . . B. Motivations for the Development of DRAM Technology in GaAs . I1. pn-Junction Storage Capacitors . . . . . . . . . . . . . . . . . . . A . General Description . . . . . . . . . . . . . . . . . . . . B. Charge Storage on pn Junctions . . . . . . . . . . . . . . . . C . Theory of pnp Storage Capacitors . . . . . . . . . . . . . . . D . Experimental Results . . . . . . . . . . . . . . . . . . . . . I11. JFET and MESFET DRAM Cells. . . . . . . . . . . . . . . . . A . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . B. Implementations of JFET and MESFET DRAM Cells . . . . . . C . Effect of Transistor Gate Leakage . . . . . . . . . . . . . . . D . A 4-Bit JFET Dynamic Content-Addressable Memory . . . . . . IV . Heterostructure DRAM Cells . . . . . . . . . . . . . . . . . . . . A . Introduction . . . . . . . . . . . . . . . . . . . . . . . . B . Undoped Heterostructure DRAMs . . . . . . . . . . . . . . . C . Quantum-Well Floating-Gate DRAMs . . . . . . . . . . . . . D . Modulation-Doped Heterostructure DRAMs . . . . . . . . . . . V . Bipolar DRAMs . . . . . . . . . . . . . . . . . . . . . . . . A . Introduction . . . . . . . . . . . . . . . . . . . . . . . . B. Concept of the Bipolar DRAM Cell . . . . . . . . . . . . . . . C . Experimental Results . . . . . . . . . . . . . . . . . . . . . VI . Future Directions . . . . . . . . . . . . . . . . . . . . . . . . A . Introduction . . . . . . . . . . . . . . . . . . . . . . . . B. Trench Capacitors and Stacked Capacitors in GaAs . . . . . . . C . Nondestructive Readout Cells . . . . . . . . . . . . . . . . . D . Ultra-Long Storage Times: Quasi-Static and Nonvolatile DRAMs . E . Nonconventional Applications . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . .
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1. INTRODUCTION. MOTIVATION. AND POTENTIAL APPLICATIONS A . Introduction and Background
The evolution of electronic systems inevitably creates demand for integrated circuits with higher integration densities. higher speeds. and lower power consumption. Often the performance of a system is limited by a relatively 1
Copyright 0 1993 by Academic Press. Inc . All rights of reproduction in any form reserved . ISBN 0-12-014728-9
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JAMES A. COOPER, JR.
small number of components in certain critical paths, so that improvements in the speed of these components reflect directly in enhanced performance of the system as a whole. The desire for high-speed integrated circuits for such applications has led to the investigation of GaAs as a host semiconductor for high-performance systems. The trend toward programmable digital systems has intensified the need for large quantities of high-speed digital memory. To date, most of the memory development in GaAs has been based on simple adaptations of existing GaAs circuit technology in the form of six-transistor static storage cells (Fiedler, Chun, and Kang, 1988; Makino et al., 1988, 1990; Vogelsang et al., 1988; Terrell, Ho, and Hinds, 1988; Maysue et al., 1989; Nakano et al., 1990), as shown in Fig. l(a). These cells are organized in a two-dimensional array to form a random-access memory (RAM). Circuits of up to 16 kilobit complexity have been demonstrated, with access times in the 3-7 nsec range. While straightforward to design and build, these static RAM (SRAM) cells are inefficient in two respects: they occupy considerable chip area, and they dissipate static power in the storage state. In silicon integrated circuit technology, the majority of large-scale RAM circuits are one-transistor dynamic RAMS (DRAMs) of the type shown in Fig. l(b). The one-transistor DRAM cell is much smaller than the six-transistor SRAM cell and dissipates negligible standby power, thus permitting large arrays to be incorporated on a single chip. The one-transistor cell consists of a storage capacitor and a single access transistor. In operation, the access transistor is turned on by the word line, electrically connecting the storage capacitor to the bit line. The storage capacitor is then charged to the potential of the bit line, representing either a logic 0 or a logic 1. When the access transistor is turned off by the word line, the storage capacitor is isolated from the bit line and remains charged to the former bit-line potential until leakage currents eventually destroy the stored information. This gradual degradation of the stored potential requires that the storage cell be periodically read and refreshed. The refreshing period must be substantially shorter than the storage time of the weakest cell in the array at the highest operating temperature. In silicon DRAM systems, refresh rates in the neighborhood of 1 kHz are commonly used, and therefore the weakest DRAM cell must have a storage time greater than about 20msec at the highest temperature. The storage capacitor in most silicon DRAMs is a metal-oxide-semiconductor (MOS) capacitor, made possible by the high-quality SiO, insulator formed by thermal oxidation of silicon. One of the obstacles to the development of DRAM cells in GaAs has been the lack of a high-quality native oxide. However, it has been found that charge storage in GaAs can be successfully accomplished using the capacitance of properly designed reversebiased p n junctions. As evidence of progress in this area, Fig. 2 shows the
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES Bit Line
VDD
VDD
3
Bit Line
+ Bit Line
Word Line
(b) FIGURE 1. Six-transistor static RAM cell (a), and one-transistor dynamic RAM cell (b). Static RAM cells in GaAs usually use MESFETs or JFETs.
evolution in room temperature storage time of GaAs homojunction capacitors over the past four years. Note that storage times have increased about one order-of-magnitude every two years and are now over 10 hours at room temperature. These results are far superior to those observed in silicon MOS capacitors. Several types of access transistors are possible in GaAs. These include metal-semiconductor field-effect transistors (MESFETs), junction field-effect transistors (JFETs), modulation-doped field-effect transistors (MODFETs), and heterojunction bipolar transistors (HBTs). All have been investigated
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JAMES A. COOPER, JR.
loo I
,
1986
,
'
'
' ' ' ,
1987
'
1988
' ' ,
'
1989
' ' '
'
'
1990
' ' '
'
, ' ' ,
1991
I
1992
Year FIGURE 2. Room temperature storage time of GaAspn homojunction storage capacitors as a function of year since development began in 1987. The trend line indicates one order-ofmagnitude increase every two years.
and will be discussed and compared in Sections 111-V. At this point, however, it is appropriate to consider possible applications for GaAs DRAMS. B. Motivations for the Development of DRAM Technology in GaAs As mentioned previously, digital systems in GaAs will require digital memory, and in order to preserve the speed advantage of GaAs systems, this memory must be fast. As a specific example, consider a GaAs microprocessor operating at a clock rate of 200MHz (5nsec cycle time). Such a processor would be similar to the 32-bit GaAs RISC microprocessor designed by Texas Instruments as part of the VSHIC program (Whitmire, Garcia, and Evans, 1988). A typical instruction requires several accesses to external memory. The simple instruction shown in Fig. 3(a) consists of four cycles: fetch instruction, decode instruction, fetch data, operate on data. Each cycle requires 5 nsec, for a total of 20 nsec for the entire instruction. However, if the program and data are stored off-chip in a silicon memory, operation is slowed considerably. For example, assume a 20nsec silicon SRAM is used. Then each external memory access requires the insertion of three "wait states," bringing the total instruction time to 50 nsec, as shown in the bottom half of Fig. 3(a). Now suppose instead we place a high-speed GaAs cache memory on the same chip as the microprocessor. Assuming a good ratio of cache "hits," the wait states can be eliminated and the instruction execution time decreases by a factor of 2.5. Figure 3(b) shows system throughput as a function of CPU cycle time for two cases: (i) when each memory access must be directed to a 20 ns off-chip RAM, and (ii) when each access can be handled by a 0.5 ns
RECENT ADVANCES I N GaAs DYNAMIC MEMORIES
5
Simple 4-Cycle Instruction Format
-
Decode
Fetch Instruction
I Instruction 1 I
+t
Fetch Data
Operate on Data
I
I
I
cycle
Introduction of Wait States to Accomodate Slow Memory (5 ns cycle time, 20 ns memory access time)
Fetch
I
Wait Wait Wait
I
I
I
Decode Fetch Data
I
I
Operate
Wait Wait Wait
I
D~~
I
CPU Clock Rate (MHz) 1oooo
1000
1000
100
1
10
100
10
0.1
Cycle Time (ns)
FIGURE 3. Part (a) shows a basic four-cycle CPU instruction. Assuming a 5 nsec CPU cycle time, each access to a 20 nsec external memory would require the introduction of four wait states, increasing the execution time to 10 CPU cycles. In part (b) we illustrate the impact that a 0.5 nsec on-chip cache memory would have on system performance as a function of cycle time, assuming a unity cache hit ratio.
on-chip cache memory. It is apparent that the benefits of cache memory increase significantly as the CPU cycle time decreases. In order to be useful, a cache memory must be sufficiently large to ensure a good ratio of cache “hits.” A typical size would be 16 kilobytes (131,072
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JAMES A. COOPER, JR.
bits). If such a memory were constructed with six-transistor static RAM cells, it would probably be too large to be included on a GaAs microprocessor chip. However, such a cache memory could be implemented using one-transistor dynamic RAM cells without excessive area penalty. There are other motivations for the development of dynamic memory technology in GaAs. A dynamic memory is inherently an analog device, and several specialized applications exist for analog storage. Examples include switched capacitor filters and electronic neural networks (see Section VI). In addition, the basic information obtained in the course of DRAM development is applicable to any device or circuit that requires low leakage, such as GaAs dynamic logic or low-dark-current imagers. As an example, GaAs DRAM research has led to a technique for reducing the subthreshold current in GaAs MESFETs by three orders of magnitude (see Section 111). In the sections that follow we will consider the factors limiting long-term charge storage on pn junctions in GaAs. We will then describe several types of one-transistor DRAM cells, including JFET, MESFET, MODFET, heterojunction, quantum well, and bipolar cells. We will conclude with a discussion of future directions, applications, and opportunities. 11. PN-Junction Storage Capacitors
A . General Description
Dynamic charge storage in GaAs can be accomplished quite efficiently using the capacitance of a properly designed reverse-biased p n junction. In this section we will first discuss the operating principles and design considerations for pn junction storage capacitors. We will then present experimental data on the performance of GaAs p n junction capacitors as a function of doping, geometry, and temperature. To begin, let us consider the pnp test structure shown in Fig. 4. Here the central n-layer is floating, and forms two back-to-back pn junctions with the surrounding p-type layers. The storage time of these back-to-back p n junctions is tested as follows: A bias Vpof either polarity is applied across the structure. This forward biases one p n junction and reverse biases the other. In the process, electrons are removed from the floating n-region across the forward-biased junction, leaving the n-layer at a positive potential. In steady state, the potential of the n-layer is essentially equal to V,, since the steady-state current will be negligible unless the reverse-biased junction is driven into breakdown. When the applied bias is returned to 0, the charge on the n-region redistributes between the two junctions in such a way that both are reverse biased. The n-region is now floating at a positive potential
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
P GaAs Substrate
FIGURE 4. Schematic of a pnp charge storage capacitor, with junction voltages defined for further analysis. Note that the voltage polarities are chosen so that positive values indicate reverse bias.
somewhat less than V,, as determined by the capacitance divider formed by the two junctions. The storage capacitor will gradually discharge as thermal generation supplies electrons to the positive n-region. This discharge can be monitored by observing the capacitance of the two back-to-back junctions, as illustrated in Fig. 5. Immediately following the bias pulse, this capacitance is small due to the large depletion regions of the reverse-biased junctions. As thermal generation returns the structure to equilibrium, the capacitance gradually rises to the value determined by the zero-bias depletion widths of the two junctions. For discussion purposes, we define the storage time as the time required for the capacitance to return to within l/e (36.8%) of its equilibrium value. In designingpn junction storage capacitors, two objectives must be kept in mind. First, we wish to maximize the charge storage density at a given voltage; i.e., the capacitance per unit area of the junction. Second, we wish to minimize the generation current that discharges the capacitor. Up to a certain point, both these objectives may be met by increasing the doping on both sides of the junction. There is, however, a limit beyond which increasing the doping will actually increase the generation current per unit area and reduce the storage time. These effects will be discussed later in this section. Before moving to a more detailed discussion of charge storage in the pn junction capacitor, however, we will anticipate the final results of this chapter by
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JAMES A. COOPER, JR.
FIGURE 5 . Capacitance transient observed on a symmetrically-doped pnp storage capacitor. For t < 0 the bias is 0 and the structure is in equilibrium. A bias pulse V, is applied at I = 0 and removed at I = to. During the bias pulse, one junction is forward biased while the other is reverse biased. Electrons are removed from the n-region by the forward-biased junction, leaving that region positive charged. The capacitance decreases due to the increased depletion width of the reverse-biased junction. At t = to the bias is returned to 0. The n-region remains positively charged and both junctions are now reverse biased. Thermal generation gradually returns the structure to equilibrium. The capacitance recovery is approximately exponential in time, with time constant T ~ .
revealing that, by proper design, it has proven possible to achieve both high-charge storage densities (1.85 fC/pm2for a single junction or 3.7 fC/pm2 for a pnp structure at 1 V reverse bias [Dungan, 1989; Dungan et al., 19901) and long storage times ( 2 10 hours at room temperature [Stellwag, Melloch, and Cooper, 1991b]) using pn-junction storage capacitors. B. Charge Storage on pn Junctions 1. Steady-State Relationships
In order to examine the most important features of charge storage on p n junctions, we will make a number of simplifying assumptions. We assume an abrupt (step) junction having uniform nondegenerate doping on each side, as shown in Fig. 6 . We also assume that all dopant atoms are ionized at the temperatures of interest. Employing the depletion approximation, it is easy to show that the maximum electric field, which occurs at the metallurgical
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
9
Mx -X
0
FIGURE 6 . Cross section of an abrupt pn junction. The voltage polarity is defined so that a positive value represents a reverse bias.
junction, is given by
where E, is the semiconductor permittivity, NA and No are the doping on the p and n sides, respectively, and xp and x, are the depletion widths on thep and n sides. These depletion widths can be expressed in terms of the total potential drop across the junction as
Here VAis the applied voltage, taken to be positive under reverse bias, and V,, is the built-in potential of the junction, given by (4)
where q is the electronic charge, k is Boltzmann’s constant, T is absolute temperature, and niis the intrinsic carrier concentration at temperature T. The capacitance of the junction serves as a useful indicator of the electrostatic state at any given time and is given by
where A is the junction area. Finally, we will calculate the charge storage density of a pn junction. The charge per unit area removed from the junction under reverse bias VAis given
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JAMES A. COOPER, JR.
where xpoand xn0are the equilibrium values of xpand x,. Making use of either (2) or (3), the charge stored per unit area at reverse voltage V, is
Here we see that the charge storage density increases as the square root of doping and also as the square root of (VB,+ 5 ) .The maximum charge storage density is limited by junction breakdown. In GaAs, to achieve breakdown fields requires charge densities in excess of 5 fC/pm2.However, a more reasonable value for maximum charge storage density is in the range of 1-2 fC/pmz. This is comparable to the planar charge storage densities presently achieved in silicon dynamic RAMS. 2 . Generation Mechanisms In describing the operation of a pnp storage capacitor, we indicated that if the voltage is quickly swept back toward 0, the charge removed from the n-region will not change appreciably. The rate at which charge “leaks back” onto the n-region is a central issue in DRAM cell operation. Working toward an understanding of the charge recovery transient in a pnp structure, we first need to consider the generation mechanisms responsible for leakage in reverse-biased pn junctions. Electron-hole pairs can be created by thermal generation, photogeneration, or impact ionization. Assuming the capacitor is kept in the dark and that internal fields are low enough that impact ionization can be neglected, the primary leakage mechanism is thermal generation (Dungan, 1989). Thermal generation can occur within the depletion region itself or in the neutral bulk within a diffusion length of the depletion region. We will show that generation in the neutral bulk can be neglected compared to generation in the depletion region. Finally, thermal generation may occur along the periphery of the device, where thepn junction is exposed by a mesa etch. This “edge” generation will prove to be important and must be included in calculation of the charge recovery transient. Thermal generation may involve either direct band-to-band transitions or transitions through defect centers in the forbidden band-gap (ShockleyRead-Hall generation). Because of the greater energy required for each transition, band-to-band generation is much less likely than generation by means of defect centers (SRH generation). Therefore, we will neglect bandto-band generation in the discussions which follow.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
11
a. Generation in the Depletion Region. The bulk generation rate per unit volume due to a single-level defect center at energy ETis given by (Shockley and Read, 1952)
n: - np (8) zp(n + n1) + TAP +PI) Here n and p are the electron and hole densities, z, and 7p are electron and hole lifetimes, and n, and p , are constants that depend on the energy E T of the defect center. Since we have assumed nondegenerate material, the carrier densities can be written
G=
n = niexp( F,, T - Ei
)
(9)
where F, and Fp are the quasi-Fermi levels for electrons and holes, and E, is the intrinsic Fermi level, usually taken to lie approximately at midgap. The constants n, and p, are the carrier densities that would be present if the respective Fermi levels lay at the energy ET. Therefore, we can write
PI =.PI(
T)
- ET
The np product in the numerator of (8) can be obtained by multiplying (9) and (10): np = n:exp( F" -7;T-) -Fp It is commonly assumed that the quasi-Fermi levels can be extended across the depletion region of a pn junction with essentially zero slope. Under this assumption, the splitting of the quasi-Fermi levels within the depletion region is equal to the applied voltage, and (13) may be written np
= n:exp(
%)
Combining (8)-(12) and (14), we can write
Equation (15) gives the generation rate per unit volume at any point within
12 1.5
,
JAMES A. COOPER, JR.
,
,
,
,
,
,
,
,
N A = N D = l x l O ” cmm3
-
. c
V*=5V 1.0
-
0.5
-
i
1
0 b‘
u
,
0.0
I
,
t i , ;
FIGURE 7. Generation rate per unit volume as a function of position in the depletion region, calculated using (15). Here we have assumed a symmetrical junction with midgap generation centers.
the depletion region. To calculate the total leakage current per unit area arising from generation within the depletion region, we need to integrate (15) with respect to position from one edge of the depletion region to the other: + XP
Jdepl
=4
G ( 4&
(16)
The integration in (16) is complicated by the fact that the terms (F, - E,) and ( E , - F,) in (15) are strong functions of position. The simplest way to evaluate the integral in (16) is to recognize that the integrand is very nearly a rectangular function of position. Figure 7 shows the generation rate given by (15) as a function of position for a typicalpnjunction. Note that G(x) goes exponentially to 0 wherever either (F,, - E T ) or ( E , - 4 ) is positive. When both (F,, - E T ) and (ET - F,) are negative, the exponential terms may be
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
13
neglected and (15 ) reduces to G=“[l %
-exp(s)]
where z, is a generation lifetime given by %=
p
e(E~-EOIkT
+
n
e(E,--Er)IkT
(18)
In the typical case, V, 9 kT/q, so that (17) becomes simply G = ni/zc.The leakage current can then be expressed as
where W, is the generation width, defined as the region within which (Fn- E,) and (E, - F,) are negative; i.e., the region where F, < E, < Fp.
b. Generation in the Neutral Regions. Hole-electron pairs that are thermally generated withln one diffusion length of the edge of the depletion region can also contribute a leakage current that will discharge the capacitor. This diffusion current is described by the Shockley diode equation:
where D,and Dpare diffusion coefficients, L, and Lpare diffusion lengths, and npo and pnoare equilibrium minority carrier concentrations for electrons and holes, respectively. This diffusion current arises as a result of the concentration gradient of minority carriers in the neutral regions adjacent to the edge of the depletion region. Under sufficiently large reverse bias (V, > 0), the minority carrier concentrations at the edge of the depletion regions are essentially 0, while deep within the neutral regions they are at their equilibrium values: npo= n f / N Aand pno= $IND. This concentration gradient gives rise to a steady diffusion current in the reverse direction. In GaAs pn junction storage capacitors, however, this diffusion current is negligible compared to generation within the depletion region (Dungan, 1989). This can be seen by the following calculation: At room temperature, n: in GaAs is approximately 4 x 10l2cm-6 while the doping densities N, and ND for typical storage capacitors are in the range lO”-lO’*~m-~.Thus the equilibrium minority concentrations npoand p,,,, are typically on the order of lo-’ ~ r n at - ~room temperature. Assuming reasonable values for diffusion coefficients and diffusion lengths, we estimate a total diffusion current of about 2000 carriers/(cm2s). If the capacitor has an area of 10 x 10 pm’, the Carrie&, or total diffusion current discharging the capacitor is only 2 x one carrier returned to the storage capacitor every eight minutes. Since the
14
JAMES A. COOPER, JR.
minimum charge stored on the capacitor is at least lo6 carriers, this leakage rate is totally negligible. c. Generation at the Junction Perimeter. Leakage current arising from generation at the perimeter of the storage capacitor must also be considered. Experimental measurements on real storage capacitors indicate that a substantial portion of the leakage current is due to such generation. At etched surfaces the termination of the crystal lattice gives rise to a continuum of generation-recombination centers distributed across the bandgap in energy. The total generation rate per unit area at the perimeter can be calculated by summing the contributions from generation centers at various energy levels across the band-gap. Thus, in analogy to (8), we may write (Schroder, 1987)
where n, and p , are the carrier densities at the surface, ,c, and c,, are capture coefficients of surface centers for holes and electrons, and D,T(E) is the density of surface centers at energy E measured per unit area per eV. The terms nls and pisare functions of energy E and are analogous to the n, and p i terms defined for bulk centers in (11) and (12) earlier. As in the case of bulk generation, we regard (21) as representing the surface generation rate at one point within the depletion region and integrate (21) with respect to position within the depletion region. Thus, by analogy to (16), the surface generation contribution to current in the depletion region is given by
j
+X P
J W P
=4
GP(x)dx
(22)
- Xn
In order to calculate this integral, we recognize that n, and p s are functions of x,and that the G, in the integrand will be negligible except in the region WGpwhere both n, and p s are small compared to ni. Since n, and p , are negligible within W,,, the integrand GPis independent of position and can be taken outside the integral in (22). Thus, combining (21) and (22) using these considerations leads to
where s, is identified as the surface generation velocity. Equation (24) for surface generation in the depletion region is the direct counterpart to (19) for bulk generation in the depletion region.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
15
3. Charge Recovery Transient
Combining (19) and (24) and taking into account the area and perimeter of the junction leads to an expression for the total generation current discharging the p n junction storage capacitor
z = ( ~ c e p )l A +
( ~ d e p 1 . P )= ~
qni
[(3) + w,,s)P] 7,
A
(
(25)
Using (6), the total charge stored on the capacitor can be written
Q = qNA(xp - x p ~ ) A (26) where xp is the depletion width on the p side of the junction and x is the 40 value of xp in equilibrium. To maintain charge neutrality, we require that NA ( x p - x p O ) = ND ( x n - xnO) (27) where x, and xd are the actual and equilibrium values of depletion width on the n-side of the junction. Denoting (x, + x , ) by Wand (xpO xd) by Wo,we can write
+
In order to write the differential equation governing charge decay in a p n junction charge storage capacitor, we must obtain expressions for the effective generation widths W, and W, in (25). The generation width W, was introduced in (19) and defined as the width of the region where F, < E, < F,. For the most general situation where NA # No and E , # E,, the expressions for W, as a function of bias are cumbersome (Dungan, 1989). However, if the generation centers lie very close to midgap ( E , x E,) and the junction is symmetrically doped (NA= ND = NB),then the expression for the generation width W, is simplified considerably. Under these assumptions, one can show that W,
(W - W,). . .if NA = ND and E,
= E,
(29) where W is the depletion width at reverse bias and W, is the equilibrium depletion width ( VA= 0). If we further assume that the generation width at the perimeter is the same as the generation width in the bulk, we can write (Dungan, 1989) that -+
w,=
W,,=(W-
Inserting (30) into (25) yields
W,)=- 2Q qAN,
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JAMES A . COOPER. JR
Equation (31) has the solution
Q(r)
=
Q(0)eKf’7s
where tS is the storage time constant defined by
Equation (33) is extremely important to understanding the capabilities of pn junction storage capacitors in GaAs. As will be confirmed by experimental measurements in Section II.C, (33) tells us that the storage time should be a strong function of temperature, since the intrinsic carrier concentration ni increases exponentially with temperature according to
where N, and Nvare the effective density of states in the conduction band and valence band, respectively, and EGis the band-gap energy. Although N,, N,, and E G are weak functions of temperature, the dominant temperature dependence arises because of the kT factor in the exponent. Thus, if (34) is inserted into (33), one expects that a plot of In (tS)versus l/Twould be linear with a slope approximately equal to EG/(2k).In other words, the storage time of a pn junction storage capacitor decreases exponentially with temperature. A second point that is apparent from an examination of (33) is that a plot of 1 / t S versus ( P / A ) should be linear, with slope 2nis,/NB and intercept 2n,/NBt,. From such a plot, it should be possible to estimate both the surface generation velocity and the generation lifetime at a given temperature. A final point should be made with regard to (30)-(33). In developing these equations we have assumed a symmetrically doped junction with generation centers at midgap. If either of these assumptions fail, our equations have to be modified. In the general case where ND# NAor E , # E,, WGis larger than ( W - W,) and the ratio of WG/( W - W,) is bias dependent (Dungan, 1989). As a result, the charge recovery transient in (32) is no longer exactly exponential, and the storage time in (33) loses its special significance. A recovery time can still be defined, however, but it becomes bias dependent. We will touch on this matter again in Section II.C.2. C. Theory of pnp Storage Capacitors Having considered the generation mechanisms and charge recovery transient in pn junctions, we now return to the pnp storage capacitor structure shown
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
17
in Fig. 4. The behaviour of this structure was described qualitatively in Section 1I.A. 1. Steady-State Capacitance- Voltage Relationship At this point we wish to calculate the capacitance-voltage relation of the pnp structure shown in Fig. 4.We assume that, in general, the two pn junctions are not doped symmetrically, and we designate the doping of the top layer NAl and the bottom layer NA2.When a bias is applied across the pnp structure, negligible current will flow in steady state, since one of the pn junctions is reverse biased. Consequently, the voltage drop across the forward-biased junction is also negligible, and virtually all the applied voltage develops across the reverse-biased junction. Thus, the total capacitance of the structure is that of two capacitors in series, one at essentially zero bias and the other reverse biased by an amount V,. Assume that V, > 0, so that the top junction is forward biased and the bottom junction is reverse biased. Under these conditions (and assuming the dopings NAIand NA2are within about two orders of magnitude of each other) the capacitance of the top junction CJ,(0) will be larger than the capacitance of the bottom junction cJ2( V,). Equation ( 5 ) can be used to calculate both these capacitances. The total capacitance of the pnp structure measured in steady state is then
The total charge stored is given by (7) evaluated for the reverse-biased junction (junction 2):
The steady-state capacitance-voltage relationship (V, swept away from 0 ) is illustrated for two values of NA2in Fig. 8. Note that if the doping is not symmetrical (i.e., NA2# NAI), the capacitance-voltage relationship will not be symmetrical about VA= 0. Figure 8 shows a decreasing capacitance when the voltage is swept away from 0 in either direction (assuming quasi-steady-state conditions), and a different, almost flat, capacitance if the voltage is swept rapidly back toward 0. The capacitance remains nearly constant when the voltage is swept toward 0 because the charge Qlotal removed from the n-region during the outward sweep cannot be quickly restored when the voltage is reduced. Again, assume that V, > 0, so that the top junction is forward biased and the bottom junction is reverse biased. When the applied bias is swept toward 0, the charge Q,,,,, , which originally resided entirely on the bottom junction, must
18
JAMES A. COOPER, JR. 4.0 10
3.5 10
. E
N -
3.0 10
8 .-0
c)
p
0
2.510 2.0 10
-5
-4
-3 -2
-1
0
1
2
3
4
5
Applied Voltage (V)
FIGURE8. Capacitance-voltage curves of a pnp storage capacitor for two different values of doping in the second pf region.
now redistribute between the two junctions in such a manner that the total voltage drop across both junctions adds up to V, . Thus, the voltages V, and V, must satisfy
where Qto,,, is given by (36) when V, reaches its maximum value on the outward sweep. At the same time, we can write
-v,+v,=V,
(38)
Substituting ( 3 8 ) into (37) yields
Equation (39) can be solved for V, as a function of VA.The capacitance of the pnp structure as VAis swept back toward 0 is then given by
where V, is obtained from the solution of (39). Depending on the relative dopings N,, and N A 2 ,the capacitance may increase or decrease as VAis swept toward 0. An example of C-V relationships for both symmetrical and asymmetrical doping is shown in Fig. 8. The value of V, that satisfies (39) when V, = 0 is of particular importance, since this is the voltage across each of thepn junctions at the end of the "write pulse." It is this voltage that determines the generation widths W, and W,, at the start of the charge recovery transient.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
19
2. Capacitance Recovery Transient (Dungan, 1989) Assume that the pnp structure has been ,pulsed to a specific voltage V, = Vp, resulting in a stored charge QtOmi, where Qtotai is given by (36).If the structure is symmetrically doped ( N A i= NA2),the charge Qtota, divides equally between junctions 1 and 2. If we further assume that each junction individually is symmetrically doped (N,, = NA2= N,, call this value of doping NB)and that the dominant generation centers lie at midgap (E, = Ei),the charge recovery transient of each junction is given by (32), with Q(0) set equal to Qtota,/2.The instantaneous charge on each junction given by (32) can be related to an instantaneous value of depletion width using (28). Thus, combining (32) and (28), we can write for each junction that Q(t)
Qtotai
= -exp 2
(- t/z,)
=qANB 2 ( W ( t )-
6)
(41)
Solving for W(t), W ( t ) = W,+-exp(-t/z,) Qtotai qANB Since the capacitance of the pnp structure is that of two junctions in series, we can write
As can be seen from (43), the capacitance transient that occurs due to generation within the pn junction is not exponential, but rather the reciprocal of a constant plus an exponential. Plots of (43) for NB = 5 x 10’7cmp3and pulse voltages of 1,2, and 5 V are shown in Fig. 9 as symbols. One is tempted to view the curves in Fig. 9, as truely exponential; i.e., as represented by an equation of the form C(t) = C,, - [C,,- C(O)]exp ( - t / z c )
(44)
In fact, the lines in the figure (barely visible beneath the symbols) are least-squares fits of (44)to the “data” represented by the symbols. The agreement would appear to be excellent, but the time constants zc obtained by the fit are approximately 9, 16, and 32% longer than z, for the 1, 2, and 5 V curves, respectively. Under the assumed conditions of symmetrical doping and midgap generation centers, we can derive an expression relating the measured capacitance recovery time constant zc to the actual charge recovery time constant z, by
20
JAMES A. COOPER, JR.
h
2
8 a C .-8
c)
P 0
610.’
510-8
4 10 -
1
0
1
2
3
4
5
t l zs
FIGURE 9. Capacitance recovery transients (symbols) calculated from (43) for a symmetricalpnp storage capacitor with NA = ND = 5 x lO”cm-’ and pulse voltages of 1,2, and 5 V. The solid lines (almost obscured by the symbols) are least-squares fits to (44).Although the fits appear to be quite good, the time constants T~ obtained by the fitting are longer than T~ by 9, 16, and 32%, as shown on the figure.
equating (43)and (44).As shown by Dungan (1989), this ratio can be written
Here e is the base of natural logarithms (e = 2.7182). The time constant ratio in (45)is typically between 1 and 2. In particular, since Qtota, increases as the square root of pulse voltage V, through (36), the capacitance recovery times observed in experiments will be voltage dependent, increasing as pulse voltage is increased. This is consistent with the trends in Fig. 9. As stated, such variations are typically less than a factor of 2 over the normal range of pulse voltages used (1 V < I V,l < 5 V). Note that the charge recovery time constant ss is not voltage dependent (see eq. 33) - rather it is our approximation of zs by zc that is voltage dependent. The preceding discussion required the rather restrictive assumptions that both junctions are symmetrically doped ( N A ,= ND = N A 2 ) and that the dominant generation centers lie at midgap (ET = Ei). These restrictions may be removed through a more careful calculation of the generation volume, the region where FN < ET < F,. The mathematics involved are straightforward but tedious (Dungan, 1989) and will not be reproduced here. However, an example of such a calculation is shown in Fig. 10. Here we plot the normalized capacitance recovery transient for two pulse voltages and three generation center positions. All six curves are calculated assuming that the effective generation current per unit volume in the depletion region, Jeff (A/ cm’), is equal to unity. The “time” axis actually represents the time integral of the charge density generated per unit volume in the depletion region during
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
21
1.o
0.8 0.6 0.4
0.2 0.0 0.00
0.01
0.02
0.04
0.03
JEFFt (C/cm
0.05
3,
FIGURE10. Normalized capacitance recovery transients for a nonsymmetrical pnp capacitor ( N A ,= NA2= 1 x 10’8cm-3,ND = 1 x l O ” ~ m - ~for ) two pulse voltages and three generation center energies. The horizontal axis is “time” multiplied by the effective generation current per unit volume Jeff= qn,(l/s, + s,P/A).
the recovery. Actual times can be computed by dividing the normalized “time” axis by Jeff = qn,(l/tG s G P / A ) . One observes that the capacitance recovery time constants in Fig. 10 (the point where the normalized capacitance is 0.632) are dependent both on initial bias and on the energy of the generation center. Again, higher pulse voltages lead to longer capacitance recovery times. However, as stated earlier, the variations are typically less than a factor of 2. We shall see that these corrections are small compared to the range of storage times that arise due to variations in the design of the storage capacitors and the procedures used to fabricate them. In the sections that follow, we will make no particular distinction between the capacitance recovery time constant tC and the charge recovery time constant tS and will simply refer to the measured capacitance recovery time constant as the “storage time” ts.
+
3 . Charge Removal Transient
In the development in Section II.C.1, we made the tacit assumption that charge is removed instantaneously from the n-region whenever a bias V, is applied across the pnp structure. This is not the case, and in fact the charge removal transient that occurs on the application of bias can be extremely slow in a higher band-gap semiconductor material such as AlGaAs or Sic. To obtain closed-form expressions for the charge removal transient, we will consider the simple circuit consisting of a forward-biased diode charging a capacitor, as shown in Fig. 11. For this development, we assume the capacitor has a fixed value independent of voltage. The capacitor is initially at zero voltage, and a bias 6 is applied across the diode-capacitor combination at t = 0. We wish to obtain an expression for the voltage V , across the
22
JAMES A. COOPER. JR
I +
t=O
-
T
VA
7i7T FIGURE11. Simple circuit model for visualizing the charge removal transient in a pnp capacitor structure.
capacitor as a function of time. The current flowing through the forwardbiased diode may be written 1 = lo ( e q ' ~ ' ~ ' - 1) = C dQ
dt
(46)
where Qc is the charge on the capacitor and I, is the saturation current density of the diode given by I,
=
ya.i(0" + L~NA
--)
0,
LpND
(47)
It is significant to note that I, varies as the square of n,. Since n, decreases exponentially with band-gap energy, as shown by (34), I, may be extremely small in high-band-gap semiconductors at room temperature. The charge on the capacitor can be written Qc = cvc = C ( ~-A VD)
(48)
and its derivative is
Combining (46) and (49) gives a differential equation that may be solved for Vo(t).After algebra, we find that
where
T,,
given by
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
10.1510-1310-11
l o - O 10-7 .,0-5
23
lo-3
t IT,
FIGURE 12. Diode voltage drop as a function of time for several values of applied voltage
6 during the charge removal transient. The write time can be made arbitrarily short if the write
process is terminated before the diode voltage reaches 0. For example, if we are willing to provide a write voltage V, that is 0.25 V greater than the final value of capacitor voltage (allowing VD to be 0.25V % 10kT/q at the end of the write process), then the write time can be reduced to 10-~~,.
is the time for a steady current I, to charge the capacitor C to a potential kT/q. Equation (50) is plotted for several values of V, in Fig. 12. If V, b kT/q and t -g q,, (50) can be simplified to
This relationship explains the linear dependence of the V, = co curve in Fig. 12. It is perhaps more enlightening to plot the capacitor voltage as a function of time, as shown in Fig. 13. The point to note from both figures is that the capacitor charges to within VD(t)of the pulse voltage V, in a specific time t , regardless of the value of VA. Therefore, if we wish to charge the capacitor to a voltage V,, in time t , , this can be accomplished by applying a pulse voltage V, given by V, = V,, + V D ( t l )where , V D ( t lis ) obtained from (50) or Fig. 12. These arguments can be refined by including the specific voltage dependence of the capacitance using (5). This is left as an exercise for the reader.
D . Experimental Results 1. Eflect of Temperature
Consider a large-area storage capacitor in which bulk generation dominates
24
JAMES A. COOPER, JR.
lo-’
10.5
10’
t IT,
FIGURE13 Capacitor voltage as a function of time for several values of applied voltage VA the capacitor dunng the charge removal transient. Note that at a specific time, say t/ro = voltage falls short of the applied voltage VAby the same amount, regardless of the value of VA. This “shortfall” is, of course, the diode voltage drop.
(A/PS
sGtG) so
that the storage time constant given by (33) can be written
Inserting (18) and (34) into (53) and assuming that (i) the dominant generation center is above midgap (this assumption is arbitrary, and equally valid equations would result if the opposite assumption were made), and (ii) z, is of the same order of magnitude as r P ,leads to
where AET = IE, - E l / .Equation (54) suggests that the storage time will be thermally activated with an activation energy EAgreater than or equal to half the band-gap. (Note that we would have reached the same conclusion if we had assumed the generation center to be below midgap, except that t pwould be replaced by 7,). To further appreciate the temperature dependence of (54), note that N , and N y are proportional to T3I2and that T~ is inversely proportional to the thermal velocity vth, which increases as TIi2.Thus, the prefactor is proportional to (1 / T)’. This dependence, however, is overshadowed by the temperature dependence of the exponential factor. In the exponent, the band-gap energy EG is a weak function of temperature and can be approximated by a firstorder Taylor expansion as EG(T) % E G O
-
UT
(55)
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
25
Temperature ("C) 181
144
111
2.4
2.6
84
60
40
21
3.0
3.2
3.4
F8
d
I"
2.2
2.8
1000/T
(1IK)
FIGURE14. Measured capacitance recovery time constants as a function of temperature for pnp capacitors in GaAs and Al,Ga,_,As (x x 0.2). The recovery process is thermally activated, with activation energies very close to half the band-gap.
where EGO is the extrapolated zero-temperature band-gap and ci is a parameter. For GaAs in the neighborhood of room temperature (Thurmond, 1975), EGO z 1.56eV and ci = 4.17 x 10-4eV/K. Inserting (55) into (54) yields
The first exponential term is now explicitly temperature independent. From the second exponential term, we see that the activation energy should be greater than or equal to half the extrapolated zero-temperature band-gap, which for GaAs is about 0.78 eV. Figure 14 shows measured storage times (Dungan, 1989) forpnp capacitors fabricated in GaAs and Al,Ga,-,As (x z 0.2). These capacitors were grown by molecular beam epitaxy (MBE) and were mesa isolated by chemical etching. The doping and thickness of the layers are the same. The storage times in Fig. 14 are indeed thermally activated, as required by (56), and the activation energies are consistent with generation sites at or very close to midgap (AETz 0). In considering the magnitudes of the storage times, we note that dynamic memories in silicon are typically refreshed at a 1 kHz rate, so that the storage times of individual cells must be longer than the refresh period of 1 msec. To take a conservative view, we shall require a storage time of at least 100msec
26
JAMES A. COOPER, JR Temperature (“C) 182 l0000
144
111
2.4
2.6
84
60
40
21
5
2.8
3.0
3.2
3.4
3.6
1000 100 10 1 0.1 0.01 2.2
lOOO/T(1/K)
FIGUREIS. Capacitance recovery time constants for three GaAs pnp capacitors having different doping concentrations. The doping on the lightly doped side is given in the legend. The ~ ~ Note the reduction longest storage times are obtained for dopings in the low l O ’ ’ ~ n -range. in activation energy for the most highly doped sample (0 1990 IEEE).
for GaAs-based memories. By this criterion, Fig. 14 indicates that both these (unoptimized) pnp storage capacitors would be capable of satisfactory operation to over 100°C. 2. Effect of Doping
Equation (33) indicates that the charge storage time constant T~ is expected to scale directly with doping. This is because higher dopings result in smaller depletion regions, and generation within the depletion region determines the storage time. Also, (7) tells us that the charge storage density, i.e., the charge stored per unit area at a given voltage, increases as the square root of doping. Since long storage times and high-charge storage densities are both desirable, it would appear that high doping levels on both sides of the junction are called for. Figure 15 shows measured time constants for three pnp storage capacitors grown by MBE and mesa isolated by chemical etching (Dungan, 1989; Dungan ef al., 1990). All growth and processing conditions were the same except for the doping of the layers. In all three structures the n-layer is doped 1 x l O ” ~ m - ~The . p-layer dopings are 7 x 1015cm-3,1 x 1017cm-3,and 1 x 1019cm-3.All three capacitors are effectively one-sided step junctions, with the generation occurring primarily on the lightly doped side. The doping of the lightly doped side is shown in the figure. (Note that for the sample with NA = 10’9cm-3,the lightly doped side is the n-region, ND = l O ” ~ m - ~ ) . Equation ( 3 3 ) suggests that the charge recovery time constant should scale linearly with the doping of the lightly doped side. Figure 15 shows that
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
27
recovery time indeed increases with doping up to about 1 x 1017cm-3. However, the sample with dopings of 1 x 1018cm-3exhibits a reduced time constant at all temperatures and a reduced activation energy. Thus it appears that there is a practical limit above which further increases in doping actually reduce the storage time. The reduced storage time of the most highly doped sample can be explained by the phenomenon of field-induced barrier lowering. This effect occurs when electric fields within the depletion region become high enough to modify the escape energy of carriers confined on a generation center. This can occur when the potential drop over a distance comparable to the radius of the electron orbit is significant compared to the ground-state energy of the center. Frenkel(l938) showed that the change in escape energy AEA is given by -
AEA = 2q/$
(57)
where F is the electric field in V/cm. Thus, AEA calculated by (57) can be viewed as the reduction in activation energy resulting from field-induced barrier lowering. Applying this correction to the data of Fig. 15, we obtain AE, values of 90, 180, and 330meV, respectively, for the three curves of increasing doping density. These values correspond approximately to the differences between activation energies seen in the figure. It has been found experimentally (Dungan, 1989; Dungan et al., 1990) that higher doping levels can be used successfully if a small undoped (or lightly doped) i layer is inserted between the p and n-type regions in each junction, resulting in a p-i-n-i-p structure such as shown in Fig. 16. The i layer has the effect of reducing the maximum electric field in the depletion region, thereby avoiding the barrier lowering phenomenon, while maintaining a very highcharge storage density (high capacitance per unit area). The storage times of two p-i-n-i-p storage capacitors are compared to a pnp storage capacitor of similar doping in Fig. 17. 3. Eflect of Device Area and Device Scaling In order to construct a high-density memory array using p n junction storage capacitors, it is important that the size of the capacitor be reduced as much as possible. Two issues arise immediately: (i) charge storage capacity and (ii) storage time. Clearly, as the area of the capacitor is reduced, the amount of stored charge is reduced proportionally. What is perhaps not immediately apparent is that the storage time is also reduced. We shall consider both of these limitations in this section. First, we consider the charge storage capacity. To permit reliable detection
28
JAMES A. COOPER. JR.
i (undoped) 30nm
N+ 10’’ cmJ i (undoped) 30nm
FIGURE16. Storage capacitor having p-i-n-i-p structure. The presence of the undoped i layers reduces the maximum electric field in the junction, minimizing field-induced barrier lowering, while still providing a high capacitance per unit area.
of the signal charge during readout and to minimize soft errors due to alpha particle strikes, a dynamic memory must store a certain minimum charge in each cell. In silicon dynamic memories, this minimum is typically on the order of lo6 electrons. To understand how this restriction affects the GaAs storage cell, let us consider the p-i-n-i-p capacitor of Fig. 16. For this capacitor, the Temperature (“C) 182 10000
144
111
84
60
40
21
5
2.4
2.6
2.8
3.0
3.2
3.4
3.6
1000
100
sE H
10 1
0.1 0.01 2.2
10001T(IIK)
FIGURE17. Capacitance recovery times for pnp and p-i-n-i-p storage capacitors. By introducing an i layer, we are able to avoid the reduction in room temperature storage time caused by field-enhanced generation.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
29
Square Edge Length (pm) 198
98
78
62
5.0
.-cE
6.25
0.16
a,
0.12
8.33
8
0.08
12.5
0.04
25.0
P
f
-
3 v
$
C
0
0 100 200 300 400 500 600 700 800
Perimeter / Area (Ilcm)
FIGURE18. Inverse storage time of square pnp capacitors as a function of P / A ratio at several temperatures. At each temperature, the generation lifetime T~ is calculated from the intercept and the surface generation velocity sc from the slope.
charge storage density of each junction is about 1.85fC/pm2 at a reverse voltage of 1V. Accounting for both junctions, the area required to store lo6 electrons would be 43 pm2 or 6.6pm on a side. This area would be reduced if a higher signal voltage were used. A reasonable lower limit would appear to be around 25 pm2 or 5 pm per side.’ Next we consider the effect of scaling on storage time. One obvious geometrical consequence of reducing the capacitor area is the fact that the perimeter-to-area ratio P / A increases. Taking the inverse of (33),
(-+
1 =2ni 1 TS
NB
sG;)
TG
This implies that a plot of inverse time constant versus P / A should produce a straight line whose slope is determined by the surface generation velocity and whose intercept is determined by the bulk generation lifetime. This is illustrated by the data (Sheppard, 1991) in Fig. 18 for four different temperatures. The inverse storage time increases linearly with P / A , in good agreement with (58). From the slopes and intercepts, we can calculate values of T~ and sG at each temperature using (58). These data are shown in Fig. 19. Here we see that both T~ and sG are relatively weak functions of temperature I As an aside, we note that one wishes to retain lo6 electrons at the end of one refreshing period. We have defined storage time as the time for the electron density to be reduced to l/e of its initial value. Thus, we should store 2.7 x lo6 charges at the beginning of the transient, requiring 2.7 times the quoted area. However, in practice one never allows the charge to decay to lie of its initial value before refreshing. In fact, if we require the storage time to be at least IOOmsec, but refresh at a 1 kHz rate, the initial charge will only decay to 0.99 of its initial value at the end of one refreshing period.
30
JAMES A. COOPER, JR
-
Temperature (“C) 111
104
97
91
84
-‘E In
78
In
Y
r”
C
.-0
e
c)
al c
8 0 Q
lo4 3 2.60
2.65
2.70
2.75
2.80
2.85
h
lOOO/l(lIK)
FIGURE19. Bulk lifetime tG and surface generation velocity sG deduced from the plot of Fig. 18.
(at least compared to the temperature dependence of n,). This slight temperature dependence indicates that the dominant generation centers are not precisely at midgap. The generation lifetime is in the vicinity of 200 ns, which is an excellent value for GaAs. We note that the precise values of T~ are somewhat uncertain, since the intercepts in Fig. 18 are estimated by extrapolation and are sensitive to small errors in fitting the data. Of more practical interest is the time constant to be expected if the area of the storage capacitor is reduced below the 62pm per side of the smallest capacitor shown. If we extrapolate the data in Fig. 18 to a side length of 5 pm, we find a storage time of 1.5 sec at 101OC. This is still comfortably above our criterion of 100msec. Therefore it appears that adequate charge storage densities and acceptable storage times can be achieved with storage capacitors down to 5pm on a side.
4. Metal Evaporation Technique Since storage time is determined by extremely small generation currents, it is to be expected that it should be sensitive to certain details of the processing. One of the most important aspects of the processing in this regard is the method of metal deposition. In fact, the storage time of well-made identically prepared samples is reduced by about three orders of magnitude if the ohmic metal is deposited in an electron-beam evaporator as compared to a thermally heated evaporator (Stellwag et al., 1992a). Figure 20 shows storage time versus temperature for four 100 x 100pm2 p-i-n-i-p storage capacitors (Stellwag et al., 1992a). These capacitors are taken from two wafers whose epitaxial layers were grown by MBE using As, and As, flux, respectively. Both p+ layers are doped 1 x 1019cm-3,the n-layer is
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
/
lo5
5
Thermally
lo3
Evaporated
i!
i=
$
10'
z
d
/
// / AS2
lo-'
10"
E-Beam Evaporated
,
1
I
,
1
,
1
,
1
,
1
1
,
I
,
31
32
JAMES A. COOPER, JR
on the flux conditions during MBE growth. This suggests that, rather than creating new centers, the electron-beam environment is simply activating preexisting centers present in the As-grown film, the density of which depends on the growth conditions. 111. JFET
AND
MESFET DRAM CELLS
A . Introduction
In Section I1 we considered the design and performance of pn junction storage capacitors in some detail. However, the storage capacitor is only half the story. In order to construct a complete DRAM cell, it is necessary to provide an access transistor that will connect the storage capacitor to the bit line for reading and writing and isolate the storage capacitor from the bit line during storage. In this section we will consider two means of implementing this access transistor in GaAs: (i) using junction field-effect transistors (JFETs), and (ii) using metal-semiconductor field-effect transistors (MESFETs). Figure 21 shows how one might implement a one-transistor DRAM cell utilizing a JFET access transistor and a MESFET access transistor. In the following sections we will present experimental results on early versions of both JFET and MESFET DRAM cells, with special attention to the effects of transistor leakage on storage time.
B. Implementations of JFET and MESFET DRAM Cells The first demonstration of a complete JFET-accessed GaAs DRAM cell was reported by Neudeck et al. (1989). The structure, shown in Fig. 22, consists of two large-area p + n storage capacitors surrounded by a ring-gate JFET. Two storage capacitors are used in this implementation so that the charge can be monitored by observing the capacitance between the two p+ plates. This is necessary since the structure is fabricated on a 1 pm undoped buffer layer. The layers are grown by MBE, and the p + gates are patterned by wet etch. The 50nm p-type GaAs layer under the channel is included to improve subthreshold performance of the access transistor, and it is fully depleted during normal operation (Yamasaki, Kato, and Hirayama, 1985). Figure 23 shows waveforms obtained during electrical writing of the cell. The top waveform is the capacitance between the twop+ capacitor plates, the middle waveform is the bit line voltage applied to the source of the JFET, and the lower waveform is a series of 1 msec write pulses applied to the gate of the access transistor (the word line). The word line is held at a negative
33
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES Bit Line
Word Line
PorS.1. GaAs
JFET DRAM Cell
Bit Line
Word Line
ohmic contac
PorS.1. GaAs I
I
MESFET DRAM Cell
FIGURE21. Two examples of FET-accessed DRAM cells in GaAs. Each cell consists of a pn junction storage capacitor and an access transistor. The top drawing depicts a JFET DRAM cell, while the bottom drawing illustrates a MESFET DRAM cell.
potential to keep the JFET biased off. When the word line is pulsed to 0, the JFET is turned on and the potential of the bit line is connected to the storage capacitor. During the first pulse the bit line is positive, and electrons are removed from the n-side of the p n junction storage capacitors. This reverse biases the p n junctions, widening the depletion regions and reducing the capacitance signal. When the second word line pulse occurs, the bit line has returned to 0. This allows electrons from the bit line to flow to the storage capacitors, returning them to their equilibrium conditions. The capacitance is thus increased. One notes that the capacitance signal changes only when the word line is pulsed to 0. This proves that the storage capacitor is effectively isolated by the access transistor: changes in bit line potential have no effect on capacitance while the access transistor is off. The high-capacitance condition occurs when the storage capacitors are in equilibrium, so this state will not decay
34
JAMES A. COOPER, JR. JFET Source (Bit Line)
JFET Drain
JFET Ring Gate (Word Line)
PN Junction Charge Storage Capacitors
50 nm P+ GaAs
FIGURE 22. A prototype JFET DRAM cell implemented in GaAs by Neudeck et al. The cell consists of two storage capacitors surrounded by a ring-gate JFET. Two storage capacitors are used to allow the charge recovery to be monitored by observing the capacitance between the storage gates. A second JFET is included for evaluation purposes (01990 IEEE).
with time. The low-capacitance state represents a reverse bias on the storage capacitor. This is a temporary condition, and the capacitance will gradually return to its equilibrium value as thermal generation discharges the storage capacitor. This can be seen in the waveforms of Fig. 23, where the storage
r
-
1 -
0
L
-2 -
A
4
wPiue I
4 WPite 0
Bit Line Voltage
1 msec Write pulse
--)-
-1
CPII
Capacitance Signal
4 wuiue I
Word Line Voltage
Time (s)
FIGURE23. Writing waveforms for the JFET DRAM cell of Fig. 22. The upper trace is the cell capacitance, the middle trace is the bit line voltage, and the lower trace is the write pulse train applied to the word line. Note that the cell capacitance changes only at the moments when write pulses are applied to the word line. The stored 1 state gradually decays due to gate leakage in 1990 IEEE). the JFET access transistor and generation in the substrate depletion region (0
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
-
-
Storage Node Write Pulse
0
>
35
-1 -
r
;
:
?
,
:
:
;
:
-
;
;
Word Line Voltage
time is estimated to be on the order of 1 s. This low storage time is due to two factors. First, the gate-to-drain leakage current in the access transistor flows directly to the storage capacitor. In this prototype geometry, the access transistor is a ring-gate configuration that actually maximizes the leakage current supplied to the storage capacitor. Second, the large undoped buffer layer below the storage capacitor provides a large generation volume for leakage currents discharging the storage capacitor. During normal operation of a GaAs DRAM cell, the cell capacitance would not be monitored. Instead, the charge state of the cell would be detected by a change in potential of the bit line when the access transistor is turned on. This mode of operation is demonstrated in Fig. 24. Here the bit line is connected directly to a high-impedance active oscilloscope probe. The top waveform in the figure is the potential of the probe, the middle waveform is a write pulse applied to the p + terminal of the storage capacitor, and the bottom waveform is the pulse train applied to the word line. The write pulse (middle waveform) momentarily forward biases the pn junction storage capacitor, removing electrons from the n-region. During the first word line pulse, the JFET is turned on and electrons flow from the bit line to the storage capacitor to restore the missing electrons. This causes the bit line to jump to a positive potential. The rapid decay of the bit line signal is caused by the RC time constant of the active probe. By the end of the first word line pulse, the bit line potential has essentially returned to ground, and as a result the storage capacitor is also essentially at ground, The second word line pulse produces almost no response on the bit line, since the storage capacitor is
36
JAMES A. COOPER, JR.
Alloyed Ohm (Bit Line) Contact
E,
i 0
10pm x 200 p n Au MESFET Ga (Word Line)
0
Storage Node Connection
50 nm
P-
NA = 1 x 10" cm-3
Undoped GaAs
FIGURE25. Top view and cross section of a MESFET DRAM cell implemented by Neudeck et al. This cell employs a linear gate rather than a ring gate, in order to minimize gate leakage current discharging the storage capacitor.
now at ground potential. Thus the charge state of the cell can be determined by detecting the bit line potential when the access transistor is turned on. Similar results have also been achieved using MESFET access transistors (Dungan et al., 1990). Figure 25 shows the top view and cross section of an experimental MESFET DRAM cell (Neudeck, 1991). Notice that in this structure the ring gate has been replaced by a linear gate. Writing waveforms for the MESFET cell are shown in Fig. 26. These waveforms are very similar to those of the JFET DRAM cell in Fig. 23. In order to eliminate the need for a negative supply voltage, the cell is operated with bit line potentials that vary from 1.3V for a logic 0 to 2.45 V for a logic 1. (A thorough discussion of operating voltage considerations for FET-accessed GaAs DRAM cells can be found in Dungan, 1989, and in Dungan et al., 1990). As expected, the cell capacitance changes only when the access transistor is turned on. In spite of the reduced gate width exposed to the storage capacitors, the storage time for this cell is only about 25 msec at room temperature. The drastic reduction in storage time is the result of increased gate leakage in the MESFET as compared to JFET. This effect will be discussed next.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES L
P5
-
3-5
-0
2 -
Q
s”
,
Cell Capacitance Signal
4 :
1
-
5 c
’
37
r
Bit Line Voltage
-_
-
1 -
1 psec Pulse
*-Write
MESFET Gate (Word Line) Voltage
0 I
I
I
I
I
I
I
I
FIGURE 26. Writing waveforms for the MESFET DRAM cell of Fig. 25. The top trace is the cell capacitance, the middle trace is the bit line voltage, and the lower trace is the write pulse train applied to the word line. The access transistor threshold voltage is + 0.8 V, and positively 1990 IEEE). shifted logic levels are employed (0
C . Eflect of Transistor Gate Leakage When an access transistor is connected to the storage capacitor, additional leakage mechanisms are introduced that reduce the storage time of the cell, even when the access transistor is deliberately biased into the off state. These leakage mechanisms are illustrated in Fig. 27. The primary leakage mechanisms are subthreshold leakage of electrons from the source to the drain and leakage of electrons from the gate (or gate depletion region) to the drain. Since the drain is connected directly to the storage capacitor, these leakage paths tend to prematurely discharge the capacitor. Subthreshold leakage from the source can be described by (Conger, (Word Line)
t
4 -
Source
(Bit Line)
ov
IDG
Drain
(Storage Node)
++I++
4
IDS
--r-
FIGURE 27. Drain current components in a GaAs field-effect access transistor. The primary mechanisms affecting DRAM storage time are drain-to-source current I,,, and drain-to-gate current I,.
38
JAMES A. COOPER, JR. 10
10 -5 0..
- VDs = + 0.5V
Transistor
ON
c p! L
a /,
10 -10
-1 .o
-0.5
\
0.0
. 0.5
Gate Voltage (V)
FIGURE28. Drain current as a function of gate voltage in a GaAs field-effect transistor. I,, is the drain-to-source current and IDG is the drain-to-gate current. I,, decreases exponentially with gate voltage below threshold, but eventually I,, dominates. This gate current is not present in silicon MOS transistors, but it is the dominant leakage mechanism in most FET-accessed GaAs DRAM cells.
Peezalski, and Shur, 1988)
Here ZDs, is the current measured at threshold (VGs= VT), V,, is gate-tosource voltage, VTis the threshold voltage, VDs is drain-to-source voltage, and n is a subthreshold ideality factor. If V,, is greater than a few kT, the term in square brackets approaches unity. In any event, the last factor shows that the current decreases exponentially as V,, is reduced below threshold. Unfortunately, one encounters a fundamental difficulty in taking advantage of this exponential reduction in subthreshold current. This is because GaAs, unlike silicon, does not possess a true insulator that can be placed between the gate and channel. As a result, a significant gate-to-drain current can flow whenever the gate becomes too strongly reverse biased with respect to the channel. This is illustrated in Fig. 28, where we show the measured drain current for a GaAs MESFET as a function of gate voltage (Neudeck, 1991). As gate voltage is reduced below threshold, the drain current in Fig. 28 drops exponentially with gate voltage, in agreement with (59). However, a minimum is reached at a gate voltage of about -0.2V; below - 0.2 V the drain current increases. This increase is due to electrons flowing from gate to drain, and the I-V characteristic in this region is that of the reverse-biased gate-to-channel junction. If the transistor of Fig. 28 were used in a p n junction DRAM cell, the storage time would be reduced to a few hundred milliseconds at room temperature. Obviously, there is considerable motivation for minimizing this effect.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
39
o3
1
10-4
*
=: 3
j
105
104 107
lo4 lov 10-10 10 -11
-2.0
-1.o
-1.5
-0.5
0.0
Gate Voltage (V)
FIGURE29. Drain current vs. gate voltage for a 5 x 350pm ring-gate JFET.
For comparable devices, gate leakage is considerably lower in a JFET than a MESFET (Dungan et al., 1990; Neudeck, 1991). Figure 29 shows drain current versus gate voltage for a 5 x 350pm ring-gate JFET, while Fig. 30 shows drain current in a 10 x 350pm ring-gate MESFET. At room temperature, the gate-to-drain leakage in the JFET is more than two orders of magnitude smaller than in the MESFET. Thus, one expects superior storage time performance from a JFET-based memory. It has been found that the gate-to-drain leakage of MESFETs can be reduced significantly by treating the GaAs surface with ammonium sulfide (NH,),S just prior to thermal evaporation of Schottky metal (Neudeck et al., 1991a). (It is important in this procedure that the metal not be deposited in an electron-beam evaporator). Figure 31 shows drain and gate currents at room temperature for treated and untreated 10 x 350pm ring-gate
10.~ 10’~ 10.~
10.’
10.’ 10.10
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
Gate Voltage (V)
FIGURE30. Drain current vs. gate voltage for a 10 x 350 pm ring-gate MESFET. Note that at room temperature the gate-to-drain leakage in the MESFET is more than two orders of magnitude higher than in the JFET of Fig. 29.
40
JAMES A. COOPER, JR
10.~ 10.6 10” 10-8
10.”
lo-’*
-1.o
-0.5
0.0
0.5
Gate Voltage (V)
FIGURE31. Drain and gate currents for a 10 x 350pn ring-gate MESFET with and without (NH,),S surface treatment prior to gate metal deposition. In the treated device the gate current exceeds the drain current for Vc < - 0.3 V because the gate depletion region is punching through to the substrate, causing substrate holes to flow to the gate. This phenomenon has no effect on DRAM storage (01991 IEEE).
MESFETs. The drain current in the treated device is reduced by about three orders of magnitude compared to the untreated device. (In the treated device, the gate current exceeds the drain current below about - 0.3 eV. This excess gate current is due to gate-to-substrate punchthrough, and has no effect on the storage time of the DRAM cell, since it does not flow to the storage capacitor .) The reduction in gate-to-drain current in the treated devices is attributed to an increase in Schottky barrier height that results from an unpinning of the Fermi level (Carpenter, Melloch, and Dungan, 1988). The (NH,)2S layer is thought to passivate most of the surface states that otherwise would exist at the metal-semiconductor interface. Although (NH,),S-treated surfaces degrade within a few hours if exposed to air, the presence of the metal gate protects the (NH,),S layer in these MESFETs. No changes in I-V characteristics could be detected after over a year of undessicated storage at room temperature.
D. A 4-Bit JFET Dynamic Content-Addressable Memory As a final example of demonstration circuits involving GaAs DRAM technology, we consider the four-bit dynamic content addressable memory (DCAM) constructed by Neudeck and coworkers (Neudeck, 1991). In a content-addressable memory, each storage cell contains logic to compare the bit of information stored in the cell with a binary signal presented on the bit line. The organization of a typical content addressable memory is depicted in Fig. 32. Each word in the memory array contains many bits of data stored
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES Bit Line
41
Bit Line
Word Line
Match Line
Word Line
Match Line
FIGURE 32. Schematic diagram of a content-addressable memory. Each memory cell contains logic elements that compare the contents of the cell to the information on the bit lines. If a bit fails to match, the cell pulls its match line to ground. Only if all cells in a word match the input pattern will the match line for that word remain high.
in individual cells connected to a common word line. In addition, the storage cells in each word of a content addressable memory are also connected to a second horizontal line called the match line. To select a stored word based on content, a binary pattern is impressed on the bit lines. Each cell in the memory compares its stored bit to the bit on its bit line. If any cell finds a mismatch, it pulls its associated match line to ground. Only if every bit in a word matches the input pattern will the associated match line remain high. Content addressable memories are useful in situations where large data bases are to be searched rapidly for specific patterns. The GaAs DCAM cell (Neudeck, 1991) is shown in Fig. 33. This cell consists of two JFET DRAM cells and four additional n-channel JFETs used to implement an exclusive-nor (XNOR) function. A unique feature of this design is the fact that an ohmic contact is established to the n-type region of the storage capacitor in each DRAM cell. This contact is connected to the gate of an n-channel JFET in the XNOR logic so that the contents of the cell can be compared with the new data on the bit lines. Altogether, six transistors and two storage capacitors are required per cell. The cell of Fig. 33 is implemented in a 2 x 2 DCAM array, complete with peripheral circuitry to load the memory with initial data, read the stored data using the bit lines, select the word lines, and read the match lines. In all, 40 JFETs and 8 storage capacitors are involved. Figure 34 shows operating waveforms of the 2 x 2 DCAM array. During the first six cycles a distinctive binary pattern (all 0s) is loaded into the
42
JAMES A. COOPER, JR. Word Line I
-
. Bit
Bit Line
Line
Match Line
5 0,
m
L
B L
Storage Node Contact
Storage Capicitor (Gate Metal)
v)
>m
‘DRAM Access JFET
FIGURE33. Schematic of one cell of the JFET DCAM cell (top) and layout of the cell (bottom). Each cell consists of two one-transistor DRAM cells and four n-channel JFET XNOR transistors. A two-level metal process is employed, with the top interconnect metal placed on polyimide for isolation.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
43
Keyword Input (81 & 82) and Match Line Output (M1 & M2)
MI M2
81
881
82
882
Stored Memory Contents
FIGURE 34. Operating waveforms of the 2 x 2 JFET DCAM array. The two match line and four bit line waveforms are shown for six cycles. During each cycle, the memory is loaded with a four-bit data pattern and then presented with nine interrogation patterns. The boxes at the bottom indicate the data pattern written into each word of the memory. The boxes at the top indicate the nine interrogation patterns and the match line responses. A d represents a “don’t care” condition, implemented by taking both bit and bit-bar lines low; d bits always match the stored bit.
memory. In the next nine cycles, all possible binary input patterns (including “don’t care” inputs) are presented and the match line outputs tabulated at the top of the figure. Beginning with the sixteenth cycle, a new data pattern (all 1s) is loaded into the memory and the interrogation pattern repeated. This cycle continues until all stored data patterns are verified with all possible input combinations. In all cases, the DCAM produced the correct outputs. The array was also tested as an eight-bit DRAM. In this mode, the match lines are ignored and the individual DRAM cells in each DCAM cell are written and read out using the bit lines. The array was fully functional in this mode as well.
44
JAMES A. COOPER, JR.
This DCAM array is far too small to be useful, it does not contain all the necessary peripheral logic such as sense amplifiers and address decoders, and it has not been optimized for minimum cell size or maximum speed of operation. Nevertheless, it does demonstrate that GaAs JFET DRAM cells can be combined into a working memory array, that they can be read and written electrically without interference between adjacent cells or excessive cross talk, and that they can be combined with logic within each cell to operate as a content-addressable memory.
IV. HETEROSTRUCTURE DRAM CELLS A . Introduction
Heterostructure DRAM cells have been investigated by several groups. These cells can be classified into two types: (i) generation-limited cells, similar to the pn junction JFET and MESFET DRAM cells already discussed, in which the nonequilibrium state is a deficit of carriers and the cell returns to equilibrium by thermal generation, and (ii) leakage-limited cells, in which the nonequilibrium state is an excess of carriers and the cell returns to equilibrium by leakage of excess carriers over a potential barrier. As we shall see, the generation-limited DRAM designs have been more successful, since generation is characterized by activation energies of at least half the semiconductor band-gap. To create a comparable leakage-limited memory would require a heterojunction band discontinuity of comparable magnitude. Such band discontinuities are difficult to achieve in 111-V material systems. In the following sections we shall first review the results obtained with leakage-limited devices (undoped heterojunction cells and quantum-well floating-gate cells). We will conclude with a discussion of generation-limited devices (modulation-doped heterojunction cells). B. Undoped Heterostructure DRAMS
A storage capacitor employing an undoped heterojunction (Cooper, Qian, and Melloch, 1986) is shown in Fig. 35(a). The barrier layer is undoped Al,Ga,-.As (x = 0.38), and excess electrons are confined in a two-dimensional electron gas (2DEG) in the GaAs adjacent to the heterojunction, as shown in part (b). Figure 36 shows C-V and I-V characteristics of the structure at 77 K in the dark and under white light (Kleine et al., 1989b). In the dark no measurable current flows, and the capacitance is that of an MOS structure in deep
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
45
FIGURE 35. A leakage-limited heterojunction storage capacitor formed by undoped AlGaAs on GaAs. A cross section of the structure is shown in (a) and the band diagram for the interface region is shown in (b). The top Al,Ga,-,As layer has a mole fraction x of 0.38, while the Al,Ga,_,As layers in the five-period superlattice have a mole fraction of 0.30. The superlattice buffer layer is included to improve material quality of the subsequently grown layers. Electrons in the 2DEG tend to escape. over the heterojunction to the GaAs gate. This leakage process limits the storage time of this capacitor.
46
JAMES A. COOPER, JR.
-
I . r L , , , , I , , , ,
I
,
,
, ,
,,
, , ,
,
, , ,
,
,
, , , ,,
1n-‘
10-7
Gate Voltage [V]
FIGURE36. Capacitance- and current-voltage characteristics of the heterojunction storage capacitor of Fig. 35 at 77 K. The current and the upper capacitance curves were taken under white light illumination, and the lower capacitance curve was taken in the dark. The dark current was too small to be measured. The ledge in the light-on capacitance curve indicates that electrons 1989 IEEE). are being stored in the 2DEG (0
depletion - the capacitance decreases as voltage is swept positive due to the expanding depletion region in the p-type GaAs. Under illumination, photogeneration occurs in the depletion region. Holes are swept into the substrate, while electrons drift to the GaAs/AIGaAs interface, where they are trapped in the potential well. As voltage is swept positive under illumination, a capacitance ledge is observed. This ledge is caused by the screening effect of electrons in the 2DEG at the GaAs/AlGaAs interface. The leakage current also increases. This can be explained as follows: At any bias, a steady state exists between electrons supplied to the 2DEG by photogeneration and electrons escaping the 2DEG to the gate or to the substrate. In the ledge region, not all of the photogenerated electrons flow from the 2DEG to the gate. Some are injected to the substrate, where they recombine with holes, producing no current. As the gate voltage increases, field emission and thermionic field emission of electrons from the 2DEG to the gate increase, and an increasing fraction of photogenerated electrons flow to the gate. The capacitance remains almost constant for a range of gate voltages (the “ledge”) because additional charges added to the gate by the increasing gate voltage are imaged by additional electrons in the 2DEG; the depletion region is shielded from the additional charges and does not expand. Eventually, the 2DEG contains the maximum electron density that can be contained behind the finite potential barrier (AEc = 0.3eV). Beyond this point no more electrons can be added to the 2DEG, and the depletion region is no longer shielded from increases in the gate charge. As a result, the capacitance again
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
-1 .o
0.0
47
1.0
Voltage (Volts)
FIGURE37. Transient capacitance decay at several gate voltages at 55K.When light is extinguished, electrons in the 2DEG leak over the heterojunction barrier to the gate, and the capacitance decreases to the dark value. The lack of hysteresis in the C-V curves in depletion (V, < - 0.4V) proves that all the stored electrons have been expelled from the ZDEG, and none 1989 IEEE). are held in traps (0
decreases with gate voltage. The gate current saturates, since now essentially all of the photogenerated electrons are flowing from the 2DEG to the gate. The various processes by which electrons escape the 2DEG are illustrated in part (b) of Fig. 35. These include thermionic emission over the potential barrier to the gate, thermionic-field emission through the top of the barrier, tunneling from quantized energy levels at E, and E , , diffusion into the substrate, and black-body photoemission over the barrier to the gate (Kleine et al., 198913). The rate at which electrons escape determines the storage time. This escape rate can be determined from a capacitance-time (C-t) transient at any voltage in the capacitance ledge region. An example of a series of such C-t transients is shown in Fig. 37. By a careful analysis of the rate of change of capacitance during each transient, the leakage current can be determined as a function of electric field in the AlGaAs and the quasi-Fermi level splitting in the 2DEG. From these analyses it is possible to distinguish which of the several leakage mechanisms in Fig. 35(b) is dominant in each bias region and to determine relevant constants in the mathematical expressions for each leakage mechanism. We shall not go into such detail here; the interested reader is referred to the literature (Kleine et al., 1989b). The major conclusion to be drawn from the work on leakage-limited undoped heterostructure DRAM cells is that storage times are too short to be useful except at cryogenic temperatures. This is illustrated by Fig. 38, where electron density in the 2DEG is plotted as a function of time following extinction of the light (Kleine et al., 1989b). Symbols represent experimental data obtained from capacitance transients, and lines are theoretical predictions based on the known emission mechanisms. One observes that storage
48
I
10'
10'
102
Time [s]
FIGURE38. Stored electron density as a function of time at 50 and 80K. The points represent experimental data at several values of gate voltage, while the lines are predictions of the emission theory of Kleine et al. (1989b). Storage times are on the order of a few seconds at 80 K (0 1989 IEEE).
times of around 1000 seconds are obtained at 50K. However, at 80K the storage times have dropped to the order of a few seconds. Measurements at higher temperatures are not practical due to the short time constant of the C-t transient. Figure 39 shows the heterojunction barriers in the GaAs/AlGaAs system as a function of AlAs mole fraction (Batey and Wright, 1986). The largest conduction band discontinuity, about 0.35 eV, occurs around x = 0.4, where the AlGaAs bandgap becomes indirect. This is very close to the mole fraction of the samples presented in Figs. 35-38. However the valence band discon0.6 0.5
I5 '0
w" U
0.4
0.3 0.2 0.1
0 0.0
0.2
0.4
0.6
0.8
1.0
AlAs Mole Fraction
FIGURE39. Conduction and valence band discontinuities in the AlGaAs ternary system as a function of AlAs mole fraction. The largest discontinuity in the conduction band occurs around x = 0.4,where the AlGaAs becomes indirect. In the valence band, however, the discontinuity increases monotonically as x approaches unity.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
0
I
Barrier Potential Well
-
f
49
AuZn
\
3 N GaAs 1 ~ 1 0 cm3 '~
N+ GaAs Substrate
FIGURE 40. A heterojunctioncapacitor for storing holes at the interface between undoped AlAs and n-type GaAs. The valence band discontinuity at this interface is about 0.55 eV.
tinuity increases monotonically, reaching a maximum value of about 0.55 eV at x = 1. Perhaps an advantage can be gained by storing holes in a twodimensional gas at the GaAs/AlAs interface! Figure 40 shows a heterostructure storage capacitor formed by undoped AlAs and n-type GaAs. This capacitor was also studied by the method of C-t transients (Qian, Melloch, and Cooper, 1986, 1989), and the results for a gate voltage of - 3 V are shown in Fig. 41. Here we see that storage times of tens of seconds are obtained at 100 K, and measurable charge storage persists to almost 200 K. Again, however, room temperature operation is not feasible. In addition to questions of storage time, we must also consider the charge storage density of heterojunction DRAM cells. The hole memory capacitor of Fig. 41 can retain about 8 x 10" holes per cm2at 150 K, while the electron capacitor of Fig. 38 retains only about 1 x 10" electrons per cm2at 80 K. In order to store lo6 carriers, the hole capacitor would need to be at least 1 1 x 11pm2, while the electron capacitor would need to be at least 32 x 32 pm2. In Section I1 we found that pnp homojunction capacitors could be made as small as 5 x 5pmZ. C. Quantum- Well Floating-Gate DRAMS
Two groups have investigated charge storage in quantum wells formed by heterojunctions. The first such structure was reported by Capasso and co-workers (Capasso et al., 1988; Beltram et al., 1988), and is shown in Fig. 42. In this structure a GaAs quantum well, formed between two AlAs barriers, serves as a floating gate for an underlying field-effect transistor. Electrons are injected into the quantum well from the gate by a negative pulse. This injection is aided by grading the band-gap of the barrier layer between the gate and the quantum well. Once stored, the electrons cause a positive shift in the threshold voltage of the underlying transistor. This
50
JAMES A. COOPER, JR. 90 K
vg = -3.0 v
10
.---.
3
N
I
b!
E
L
rl
0
4
x
5
h
Y
v
a
..
A
0
lo-'
I
10"
I
10'
I
102
lo3
t [sec]
FIGURE 41. Hole density in the capacitor of Fig. 40 as a function of time at several temperatures. Hole densities in the low 10" cm-' range can be retained for several seconds at temperatures up to 190K, but room temperature operation is not feasible.
threshold shift can be detected by observing the current in the transistor, providing a form of nondestructive readout. In the GaAs/AlAs version, the room temperature storage time was about 2 sec, increasing to about 4 hr at 77 K. Figure 43 shows drain current transients at 140 K and at room temperature following filling pulses from the gate. From measurements of effective threshold voltage shift, a sheet charge density of about 10l2cm-2 was inferred for the quantum well. A similar structure was investigated by Lott, Klein, and Weaver (1989b). This structure differed from the structure of Fig. 42 in that a variable-period superlattice was used to produce the graded-band-gap effect in the injector region. Storage times of around 1 sec were reported at room temperature, with sheet charge densities above 10''cm-2. The latter workers have also reported similar devices using InAs (wells)/ AlAsSb (barriers) on InAs substrates (Lott et al., 1989a), and using InGaAs (wells)/InAlAs (barriers) on InP substrates (Lott et al., 1990). The InAs/ AlAsSb structures exhibited a l / e storage time of only 50 sec at 77 K. Storage time data was not reported at higher temperatures. The InGaAs/InAlAs devices had storage times of around lOsec at 200K, decreasing to less than 1 s at 250 K. In the latter devices, the dominant mechanism of charge loss was
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
N+Gah 500nm
graded undoped
"raped
AlGaAs 180 nm
1
200 nm
U AlAs 100
nm
51
N SI GaAs OeAS 75 Substrate nm
Equlllbrlum
Du~Ing WRITE phase
FIGURE 42. A floating-gate DRAM cell in which electrons are stored in a GaAs quantum well between two AlAs barrier regions. Electrons are injected from the top gate over a compositionally graded AlGaAs barrier. The presence of electrons on the floating gate modulates the current in the GaAs channel below, providing nondestructive readout (0 1988 IEEE).
identified as horizontal leakage over a lateral potential barrier, rather than vertical emission over the heterojunction discontinuity. The quantum-well DRAM structures described previously are qualitatively similar to the single-heterojunction storage capacitors discussed in Section 1V.B. In both cases electrons are retained behind the potential barrier created by the conduction band discontinuity at a heterojunction. The storage time is determined by the rate at which electrons are emitted over the heterojunction. In comparing the storage times reported for these two types of structures, a striking difference in storage time is apparent: The capacitors of Section IV.B, which were based on the heterojunction between GaAs and Al,Ga,_,As
52
JAMES A. COOPER, JR.
-a -E
2 c5-)/-vw (z
atp= loops
Atp=1 ms
(b)
3
za
4T=300K
a
n
3
I
I
9
5-
T= 140K
-
I
WRITE 4-
0
WRITE
ERASE (SHORT LIGHT PULSE)
2
4 TIME
6
(c)
8
10
(5)
FIGURE 43. Channel current in the floating-gate DRAM of Fig. 42 as a function of time at (a) 140K and (b) room temperature. The current transients have time constants of 4 hours at 140 K and 2 seconds at room temperature. Part (c) illustrates the write-erase operation at 140 K (erase is accomplished by shining light on the sample) (01988 IEEE).
(x = 0.38), had measurable storage times only below 100 K. In contrast, the quantum-well capacitors of Section C, based on the heterojunction between GaAs and AlAs, had storage times of 1-2 sec at room temperature and 4 hr at 140K. What can account for such a dramatic difference? One possible explanation is that the GaAs/AlAs and InAs/AlAsSb systems are heterojunctions between direct band-gap and indirect band-gap semiconductors. Thus, electrons residing in the r valley in the quantum well must be emitted into the X valley in the barrier. The thermionic emission rate of
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
53
electrons over a potential barrier decreases exponentially with the barrier height. However, Solomon, Wright, and Lanza (1986) have argued that when the heterojunction is indirect, the prefactor before the exponential term is diminished, owing to reflections caused by wave function mismatch. A similar argument applies to thermionic-field emission (tunneling). Solomon et af. (1986) have calculated these prefactors from measurements of dc current through n+ in- n+ structures, where the i layers were undoped Al,Ga, -,As (0.3 < x < 0.8) and the doped layers were GaAs. They conclude that the prefactor for thermionic emission decreases by about a factor of 200 at x = 0.8 as compared to the value when x < 0.4. For thermionic-field emission, the prefactor decreases by about a factor of 2500 at x = 0.8. However, Kleine, Melloch, and Cooper (1989a) have pointed out that these decreases are insufficient to explain the reported room temperature storage times of the quantum-well storage capacitors. Kleine et al. measured the transient decay of electron density at the heterojunction between GaAs and Al,Ga,-,As at 55K for mole fractions of 0.4, 0.6, 0.8, and 1. The optimum mole fraction for electron storage at this temperature was found to be between 0.4 and 0.6, and the storage time decreased markedly as the mole fraction approached unity (Kleine et al., 1989a). Moreover, they showed that the storage time of a GaAs/AlAs barrier at room temperature, based on the parameters of Solomon et al., would be less than 1psec. Another possible explanation for the long storage times reported for quantum-well capacitors is charge trapping (Kleine et af., 1989a). It is not possible to determine from capacitance or threshold voltage transients whether the stored charges are mobile or confined in deep traps in the material. Certainly, if charges were confined in traps, the storage times would be much greater than predicted by thermionic emission or thermionic field emission theories. If charge trapping were taking place, the cell would also be highly resistant to electrical erasure, and could not function effectively as a random-access (read-write) memory. Indeed, the floating-gate cells of Capasso et al. (1988) and Beltram et af. (1988) could not be electrically erased, and instead were erased with light. Moreover, evidence of charge trapping in the AlAs was specifically mentioned by the groups investigating GaAs/AlAs quantum-well capacitors (Capasso et al., 1988; Beltram et al., 1988; Lott et al., 1989b). In the single-heterojunction results reported in Section B and in the emission study of Kleine et al. (1989a), charge trapping could be ruled out by the fact that no hysteresis was observed when C-V curves were swept rapidly in both directions (electrical removal of stored electrons). To summarize this rather confusing section, quantum-well storage capacitors have exhibited storage times up to 1-2 sec at room temperature, although some controversy exists regarding the explanation for the storage
54
JAMES A. COOPER, JR.
2DEG
I
.................... P+ GaAs
N AlGaAs
I
P GaAs
P+ GaAs Substrate
FIGURE44. Cross-section and band diagram of a modulation-doped heterostructure storage capacitor. Because of the band banding in the AlGaAs layer, the Fermi level at the interface lies above the conduction band in the GaAs. As a result, a 2DEG will be present at the GaAs/AlGaAs interface in equilibrium.
phenomenon. The issue is made moot, to some extent, by the results obtained with simple pn junction storage capacitors in Section I1 and the results to be reported in the next section. D . Modulation-Doped Heterostructure DRAMS
A heterostructure capacitor employing modulation doping is illustrated in Fig. 44. This type of structure has a distinct advantage over both the undoped heterostructure capacitors considered in Section B and the quantum-well capacitors discussed in the last section. This is because the modulation-doped structure of Fig. 44 is generation limited, in the sense that it retains a two-dimensional electron gas as the equilibrium state. The non equilibrium
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
55
Access
P+ substrate
L--
Storage Capacitor
, Word Ly,
FIGURE45. Cross section of a MODFET DRAM cell. This cell consists of a rnodulationdoped heterostructure capacitor and a MODFET access transistor.
state is achieved by removing electrons, and the structure returns to equilibrium by thermal generation, just as the pn homojunction capacitors of Section 11. Thus one expects storage times in modulation-doped heterostructure capacitors to be comparable to those in p n homojunction capacitors. Figure 45 illustrates a complete one-transistor DRAM cell using a modulation-doped heterostructure (Kleine, Cooper, and Melloch, 1991). A p + GaAs layer is used as the gate of the access transistor and the top electrode of the storage capacitor. This p + layer has a higher barrier to the AlGaAs than a metallic gate, thus reducing gate leakage current in the access transistor (Priddy et al., 1987). The AlGaAs layers have an AlAs mole fraction x = 0.3. The storage capacitor is 187 x 190pmZ,while the access transistor has a gate length of 5Spm and width of 54pm. Storage times of an isolated modulation-doped storage capacitor and a complete DRAM cell are shown as a function of temperature in Fig. 46. As was the case with JFET and MESFET DRAM cells, addition of the access transistor reduces storage times by several orders of magnitude. This is due to gate leakage current flowing when the transistor is biased off. At room
56
JAMES A. COOPER, JR. Temperature ("C) 105f,'
144 .
,
'
111
'
84
'
'
'
60
39
,.
21 ,
1OOO/T (1/K)
FIGURE46. Storage times of an isolated modulation-doped storage capacitor and a complete MODFET DRAM cell as a function of temperature. The isolated capacitor has a storage time of 4.3 hr at room temperature. The storage time of the complete cell is reduced to about 2 min at room temperature because of leakage currents in the MODFET access transistor.
temperature, the storage time of an isolated modulation-doped storage capacitor is about 4.3 hr. In the complete DRAM cell, gate leakage in the access transistor reduces the storage time to about 2min at room temperature. The storage capacitor exhibits two activation energies, indicating two independent generation processes are occurring. The fact that both of these activation energies are greater than half-band-gap suggests generation through centers some distance from the middle of the band-gap. The results shown in Fig. 46 were obtained on cells that had thermally evaporated metal. The use of electron-beam metallization reduces the storage time of isolated capacitors to around 15min at room temperature. This is consistent with the results reported for pn junction storage capacitors in Section II.D.4. Figure 47 illustrates electrical writing of the MODFET DRAM cell. The charge state of the storage capacitor is monitored by measuring the capacitance between the storage gate and the substrate. A gate bias of - 2.9 V was applied to the access transistor during storage, and the gate was pulsed to 0 to write information into the cell. The arrows indicate the points where the MODFET access transistor was momentarily pulsed on. Write pulses as short as 20nsec were effective in writing the cell. Shorter pulses were not investigated due to equipment limitations. It can be seen that for this particular device the room temperature l/e capacitance recovery time is about 3 min. The bit line waveforms during reading are shown in Fig. 48. Here the potential of the bit line is monitored by a high-impedance FET probe. The 2DEG in the storage capacitor is first partially removed by pulsing the
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES 11
0.5
10
0.4
9
0.3
a 0 8 c m c
0.2
E: a v
.-O
7
0.1
Q
6
0.0
m
B -
8
-k 0
-
’ 0
=al C
2
-0.1
5
57
-0.2
4
0
200
100
300
500
400
600
Time (s)
FIGURE 47. Writing waveforms for the MODFET DRAM cell of Fig. 45. Note that the cell capacitance changes only at the instants when write pulses are applied to the word line (indicated by arrows). The storage time of this cell can be estimated from the capacitance transient to be about 3 min at room temperature.
storage gate to a negative bias for sufficient time for the electrons to recombine with substrate holes. The pulse voltage magnitude is indicated on the figure. Note that for the largest pulse voltage shown here (- 1.5V), the 2DEG is still not totally removed, since the threshold voltage for this device is - 2.08 V. The access transistor is turned on at t = 0, which is 50 msec after the end of the emptying pulse. For r > 0, charge sharing occurs between the storage capacitor and the combined capacitance of the bit line and FET probe, resulting in a voltage output proportional to the charge required to refill the storage capacitor. The decay of the output signal for r > 0 is due primarily to the conductance of the FET probe. 0.5
E
-.-m
,
,
I
,
,
,
,
,
,
,
,
,
,
,
,
. , ,
,
,
,
,
300 K
0.4
E: 0.3 al w
tc
0
.4
.=
m
0.2 0.1
0 -10
0
20 Time (ps)
10
30
40
FIGURE48. Bit line waveforms during reading of the MODFET DRAM of Fig. 45 as a function of the write pulse voltage used to empty the storage capacitor. The access transistor is turned on at time t = 0, which occurs 50msec after a I is written to the cell. The storage capacitor contains a partial 2DEG even for the - 1.5 V case, since the threshold voltage for total removal of the 2DEG is - 2.08 V.
58
JAMES A. COOPER, JR.
output
Memory Cel I S
F1
MODFET F3
F2
s
F4
D
500 nm undoped AlGaAa
-
950 nm p AlGaAs
-
360 nm p GaAs
seml-InsulatingG a b substrate
FIGURE49. A modulation-doped heterostructure DRAM cell reported by Chen et al. Electrons are stored in the 2DEG under gate F2, while gates F1 and F3 are used for isolation. The transistor formed by gate F4 is used to buffer the output. During testing, gate F3 was left on permanently. In an actual DRAM, transistors FI and F3 would be replaced by a single MODFET (reprinted with permission of Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts).
A similar modulation-doped heterostructure DRAM cell has been reported by Chen, Goodhue, and Mahoney (1991). This cell, shown in Fig. 49, utilizes a 20 nm undoped GaAs quantum-well channel grown on a fourperiod AlGaAs/GaAs superlattice buffer layer. An undoped AlGaAs layer and a p + AlGaAs barrier are placed under the superlattice to prevent electron emission to the semiinsulating substrate, and a modulation-doped barrier is grown on top of the GaAs channel. All AlGaAs layers have mole fraction x = 0.23. The primary storage gate is labeled F2, and two separate transistors, labeled Fl and F3, are used for writing and reading the cell. An output MODFET, F4, is also included to amplify the signal resulting from charge transfer when F3 is turned on. In functionality demonstrations, however, Chen et al. kept F3 biased on to avoid capacitive coupling between the read pulse and the cell and placed a 1 MQ resistor in series with the gate of F2 to minimize coupling of the write pulse applied to F1. The circuit of Fig. 49 has a storage time of only 250msec at room temperature, probably due to leakage through transistor F3, which is always left on. However, large-area isolated storage capacitors exhibit storage times as long as 5.4sec at room temperature and up to 40 sec at 77 K. The charge storage density is 4.5 x 10" electrons per cm'.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
59
V. BIPOLARDRAMs A . Introduction
In Section I1 we found that the storage time ofpn junction storage capacitors is limited by thermal generation of hole-electron pairs. This process is slow in higher band-gap materials such as GaAs, and well-made storage capacitors can have storage times of several hours at room temperature. In Sections I11 and IV we learned that the addition of a field-effect access transistor (either JFET, MESFET, or MODFET) reduced the overall storage time of the complete cell to the order of 0.1-100sec. This drastic reduction in storage time is due to unavoidable gate leakage when the access transistor is in the off state. We note that silicon DRAM cells avoid this problem because MOS transistors have essentially no gate leakage. The most straightforward way to eliminate gate leakage in the access transistor is to eliminate the gate! This can be done if, instead of a field-effect access transistor, we employ a bipolar access transistor. We should point out that bipolar DRAM cells are really not new, since DRAMs based on integrated injection logic were introduced in silicon in the early 1970s (Sander and Early, 1976; Quinn et al., 1978). These cells worked well, but they offered no particular operational advantage over MOS DRAM cells, since MOS cells in silicon are not limited by gate leakage. However, in GaAs the advantage over FET-accessed cells is enormous. In this section we will discuss the operation of a bipolar DRAM cell in GaAs. B. Concept of the Bipolar DRAM Cell A bipolar DRAM cell in GaAs (Stellwag, Cooper, and Melloch, 1991, 1992) is illustrated schematically in Fig. 50. This cell can be recognized as the basic pnp storage capacitor of Fig. 4 with an additional n-type layer on top. This n-type layer, together with the p - and n-type layers immediately beneath it, form an npn bipolar transistor. This bipolar transistor is merged with the pnp storage capacitor, as indicated in the figure. The base of the bipolar transistor is connected to the word line and the emitter to the bit line. The collector is floating and forms a p n junction with the substrate. The capacitance of this latter pn junction, together with the capacitance of the base-collector junction, stores the charge. Operation of the bipolar DRAM cell is illustrated in Fig. 51. In equilibrium, the n-type collector is at ground potential, corresponding to a stored logic 0 (part a). A logic 1 is written by removing electrons from the collector. This is done by taking both bit line and word line positive, thereby forward
60
JAMES A. COOPER. JR
Bit Line NPN Bipolar Access Transistor
Word Line
t
%
...........
.......
P GaAs N GaAs
Floating Collector
PNP
Storage Capacitor
P+ GaAs substrate
*
FIGURE50. Cross section of a bipolar DRAM cell in GaAs. An npn bipolar transistor is merged with a pnp storage capacitor to form the cell. Alternatively, the cell may be viewed as an npn bipolar transistor with a floating collector, with the collector specially constructed to have a large capacitance to ground.
biasing the collector-base junction (part b). Electrons will flow from the collector to the emitter until the collector-base voltage has been reduced to 0. The collector is now at the potential of the word line. If both bit line and word line are returned to ground, part (c), the collector remains positively charged due to the loss of electrons. The structure is now storing a logic 1. Note that all potentials applied to the cell are now at ground. As a result, the only currents that will discharge the collector are those due to generation in the depletion regions of the two reverse biased junctions. This is the same situation as the pnp storage capacitors of Section 11, where storage times of several hours were obtained at room temperature. Also, note that, since storage takes place with all terminals at ground potential, no power is dissipated in the storage state. Indeed, the memory can be considered nonvolatile, in the sense that all external power can be removed without loss of stored data, at least for times short compared to the normal storage time of the cell. The cell can be written to a logic 0 state by keeping the bit line at ground and taking the word line slightly positive, as shown in part (d). Electrons then flow from the emitter to the collector until the collector-toemitter voltage is 0. In examining the sequence of band diagrams in Fig. 5 1, we note a conflict. To empty the cell, the word line and bit line are taken several volts positive. To fill the cell, however, the bit line is kept at ground and the word line is taken only slightly positive. Since we have no way of knowing whether the bit line will be positive or at ground during a particular writing operation, how can we know to what potential to take the word line? The answer is that the writing operation must be a two-step procedure: First all cells in a word
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES Substrate
61
Floating coiiector
%?* \....
0
.
0
....
(a)
Store Zero (Equilibrlurn)
(b) Read -or-
Write One
0
0
0
(c) Store One
FIGURE 51. Band diagrams illustrating the operation of the bipolar DRAM of Fig. 50. Data consists of the presence or absence of electrons in the floating collector. Electrons are removed by taking both the word line and bit line positive, as shown in part (b). Data is stored when both the word line and bit line are at ground potential, as in parts (a) and (c). Electrons are inserted by taking the word line slightly positive while the bit line is held at ground, part (d).
must be emptied (word line and all bit lines taken several volts positive), then the cells must be selectively refilled, based on the bias state of their particular bit lines (word line taken only slightly positive). From the schematic drawing in Fig. 50, two other advantages of the bipolar cell can be seen. First, the cell conserves area, since the access transistor is vertically integrated on top of the storage capacitor. Second, the cell is inherently fast, since charge transport during reading and writing is vertical rather than horizontal. This latter point deserves further explanation. In FET-accessed cells such as shown in Fig. 21, charge transport occurs laterally along the FET channel. During reading and writing, the storage capacitor in these structures functions essentially as a long-channel FET, and the channel can pinch off, limiting current flow. This pinch-off effect is avoided in the bipolar structure.
62
JAMES A. COOPER, JR.
The bipolar DRAM of Fig. 50 can also be realized as a heterojunction bipolar transistor, or HBT. In the HBT the emitter is formed from AlGaAs, and the base and collector from GaAs. HBTs are widely used in GaAs bipolar circuits because the valence band offset at the emitter-base junction drastically reduces hole injection from the base into the emitter, improving the emitter injection efficiency. This improvement is so great that it is no longer necessary to keep the base doping lower than the emitter doping. The increase in base doping has the added advantage of reducing the base spreading resistance. To apply these ideas to the bipolar DRAM cell, we must consider the requirements on the bipolar access transistor. As illustrated in Fig. 51, the operation of the bipolar DRAM dictates that the access transistor operate in both the forward and inverse modes. When electrons are removed from the floating collector (Fig. 51(b)), the transistor is in the inverse mode, with the collector functioning as an emitter and the emitter functioning as a collector. If we construct the cell using HBT technology, it will be desirable to fabricate both the collector and emitter in AlGaAs to enhance both forward and inverse operations. Therefore, we envision a double-heterojunction bipolar transistor in which the n-type emitter and n-type collector are both AIGaAs. The presence of a heterojunction in the reverse-biased collector-base junction would have minimal effect on forward operation. A further extension would be to make all layers (except the base) AlGaAs, since this would reduce generation in the depletion region of the collectorsubstrate junction. C . Experimental Results A prototype homojunction bipolar DRAM cell is shown in cross section in Fig. 52. This cell was grown by MBE, and metalized using a thermal evaporator (Stellwag et al., 1991a, 1992b). The storage time of the cell is measured by observing the transient recovery of the base capacitance following writing a logic 1. The capacitance transient of a 36 x 48 ,urn2cell at room temperature is shown in Fig. 53. The l/e recovery time is 16,200 sec, or 4 . 5 hr. This storage time is of the same magnitude as storage times of isolated pnp capacitors reported in Section 11, indicating that the presence of the bipolar access transistor has no negative effects on storage time. Figure 54 shows storage time as a function of temperature for several bipolar DRAM cells. An activation energy of 0.88 eV is common to all cells, and larger cells have slightly longer storage times, consistent with the scaling arguments presented in Section II.D.3. The cell is electrically written in Fig. 55. The 3 V, 1 msec word line pulses are not shown, but occur at the points indicated by arrows. Note that the capacitance increases when the bit line is at ground (store 0 state), since this
63
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
p+ GaAs I I
1x10 19cm-3
Access Transistor
100 nm
I GaAs
30 nm 5x10 "cni3
p+ GaAs
I I
200 nm
1x10 '9cmi3 1000 nm
p+ GaAs Substrate
FIGURE 52. Cross section of the experimental device used to verify the operation of the 1992 IEEE). bipolar DRAM (0
returns the cell to equilibrium. When the bit line is positive (store I state), the capacitance decreases. This is because electrons have been removed from the floating collector, widening the depletion regions. The capacitance transient in the store 0 state is due to the turn-off time of the forward-biased emitterbase junction, as excess carriers are removed by recombination. This transient has no effect on operation of the memory. We should emphasize that in the high-capacitance store 0 state, the cell is actually in equilibrium, Time (hours) 1.10
G'
e 8c
m
105
0
-
0
2
.
4
,
10,000
mj. I 6
1
0
10
'
20,000
30,000
.
-
40,000
Time (sec) FIGURE 53 Capacitance recovery transient measured at the base contact of the bipolar DRAM cell of Fig 52 at room temperature A recovery time constant of 4 5 hr is observed (01992 IEEE)
64
JAMES A. COOPER, JR. Temperature ( "C ) 144
111
2.4
2.6
84
60
2.8
3.0
40
21
3.2
3.4
105
1000 / T (1/
1
K)
FIGURE54. Storage time as a function of temperature for several bipolar DRAM cells. All cells have an activation energy of about 0.88 eV. Storage time decreases slightly as the cell is 1992 scaled to smaller dimensions, as expected from the scaling discussion in Section I1 (0 IEEE).
and no further decay of capacitance will occur. The nonequilibrium condition actually corresponds to the low-capacitance store 1 state. Thus, the capacitance in the store 1 state will gradually rise (with a time constant of 4.5 hr at room temperature). No such rise is perceptible on the short time scale of this figure.
VI. FUTURE DIRECTIONS A . Introduction
In the five previous sections we have described experimental work that has led to the present state of the art in GaAs one-transistor DRAM cells. Over the past years, storage times in GaAs capacitors have increased dramatically - from about 3 min at room temperature in 1987 to over lOhr in 1991, and the trend seems likely to continue. Moreover, the use of bipolar access transistors, as described in Section V, makes it possible to construct complete DRAM cells having storage times on the same order of magnitude as the capacitors alone. The charge storage density of p n junction capacitors in GaAs is comparable to that achieved in planar storage capacitors in silicon. What next? What directions should GaAs DRAM development take from this point? What applications can be identified that would lead to commercialization of these devices? We will address some of these questions in this final section.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
-
L
c m
65
Equilibrium Capacitance
I
---
m
Store 0
c)
0
8 0
Store 1
m
iL------1
0
200
400
600
800
1000
Time (sec)
FIGURE 55. Electrical writing of the bipolar DRAM cell. For this test, the charge state of the cell is monitored by observing the base capacitance. To write the cell, 3 V, 1msec write pulses are applied to the word line at the times indicated by arrows. The capacitance decay in the store 0 state is due to the turn-off transient of the forward-biased emitter-base junction, and it has no effect on operation. The store-0 state is in fact the equilibrium condition and will never decay. The low-capacitance store 1 state is the nonequilibrium condition. This capacitance will gradually increase with a time constant of 4.5 hr at room temperature. This increase is impercept1992 IEEE). ible on the time scale of this plot (0
B. Trench Capacitors and Stacked Capacitors in GaAs One of the dramatic developments in the evolution of silicon DRAMs was the introduction of vertical structures to increase the effective charge storage density (Sunami, 1985; Lu, 1989; Sunouchi et al., 1990). These vertical structures take the form of trench capacitors and stacked capacitors, as illustrated in Fig. 56. A large number of variations on these basic ideas have been proposed, but we will not attempt to review them here. The main point is that vertical structures have become absolutely necessary in silicon DRAMs at the integration levels prevalent today. On first glance it would appear that GaAs would be unable to emulate these vertical structures, and so would be totally unable to compete for high-density DRAM applications. However, that may not be the case at all. In this section, we will describe early efforts to develop a trench capacitor
66
JAMES A. COOPER, JR. Bit Line
Word
Line
Plate Voltage
SIO,
P Silicon
Trench Capacitor Cell
Bit Line
Word Line
P Silicon
Plate Voltage
P
Stacked Capacitor Cell
FIGURE56. Two types of vertical-geometry DRAM cells in silicon. The trench capacitor cell conserves area by placing the storage capacitor on the sidewalls of a vertical trench. The trench aspect ratio can be as high as 30: 1. The stacked capacitor cell utilizes a multilayer sandwich of insulating and conducting layers formed on top of the semiconductor surface.
technology in GaAs. We will also speculate on the use of stacked capacitors in conjunction with GaAs DRAM cells. Trench capacitors and complete trench DRAM cells can be grown in GaAs using a technique known as atomic layer epitaxy (ALE) (Bedair et al., 1985). ALE is a gas-phase epitaxial growth technique similar to metal-organic chemical vapor deposition (MOCVD) except that special precautions are taken to expose the growth surface to only one species of adatom at a time. Epitaxy is carried out in a temperature range where growth is self-limiting, so that a single monolayer of either Ga or As is formed during one cycle. The growth surface is alternately exposed to ambients containing Ga and As source gases, resulting in layer-by-layer growth. This leads to unprecedented control of the growing film on an atomic level. One very useful property of this growth technique is the ability to grow high-quality layers conformally on vertical sidewalls of etched trenches. This property is exploited to build trench DRAMS in GaAs. Figure 57 is a scanning electron micrograph of four 100 x 100pm’ mesaisolated GaAs p n diodes grown by ALE over a substrate in which several square 2pm deep trenches were etched prior to growth (Neudeck et al.,
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
67
FIGURE 57. SEM photograph of four 100 x 1oOpm2mesa-isolated pn diodes grown by ALE conformally over a substrate in which 2 pm deep trenches were etched prior to growth. Two of the mesas have a single 30 x 30pm2trench each, one mesa has nine 10 x 10pm2trenches. and one is planar (no trenches). The planar mesa is at the upper right. The light-colored square regon near the center of this device is the metal ohmic contact. An SEM cross section of one of the trenches is shown at the bottom.
68
JAMES A. COOPER, JR. Area = 100 x 100 pm
0
-0.5
-1
0.5
Voltage (V)
FIGURE58. Current-voltage characteristics at 1 4 4 O C for three ALE-grown pn diodes (symbols) with and without trenches. The nine-trench diode has 360pm of trench sidewall, while the one-trench diode has 120pm of trench sidewall. The line represents one of the best MBEgrown planar diodes.
1991b). Three types of diodes are shown: the diode on the upper right has no trenches (planar diode), the diodes on the upper left and the lower right each have one 30 x 30pm’ trench, and the diode on the lower left has nine 10 x 10pm2 trenches. The surface morphology is smooth, and conformal growth of epitaxial layers over the trench sidewalls is observed. Figure 58 shows the current-voltage characteristics of these three types of structures at 144OC. Also shown for comparison is one of the best planar diodes grown by MBE. Both forward and reverse currents are larger for the diodes containing trenches, but the reverse characteristics are not significantly degraded. Figure 59 shows the dependence of reverse current on trench perimeter for the three structures at a reverse voltage of 1V. Note that the one-trench and the nine-trench diodes each have the same trench area and same total diode area,
0
100
200
300
400
Trench Perimeter (pm)
FIGURE59. Leakage current at 144°C and 1 V reverse bias for the three ALE diodes of Fig. 5 8 . The reverse leakage increases linearly with trench perimeter.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
69
but the trench perimeter differs by a factor of three. From this plot it is apparent that the reverse leakage scales with trench perimeter. It is not possible to determine from this measurement whether the leakage is due to the sidewalls themselves or to generation at the edges where the vertical sidewalls meet the horizontal top and bottom surfaces. This question can be resolved by a study of the dependence of leakage current on trench depth. Measurements of leakage current as a function of temperature indicate that the leakage is thermally activated. The planar diodes have an activation energy of 0.713 eV while both the trenched samples have an activation energy of 0.844 eV. These samples were metalized by electron-beam evaporation. Further work is needed to determine the dependence of leakage current on trench depth and sidewall orientation. In addition, both pnp storage capacitors and bipolar DRAM cells need to be built using this technique, and storage times need to be measured as a function of trench depth and orientation. Preliminary evidence based on the diode leakage measurements suggests that the degradation of storage time caused by the trenches would be within acceptable limits. The advantages of increased charge storage in the same amount of horizontal chip area would probably far outweigh the negative effects on storage time, particularly when storage times of planar devices are now measured in terms of hours at room temperature. Another approach to achieve higher charge storage densities with nonplanar capacitor structures is the use of stacked capacitors, similar to those illustrated in Fig. 56. In silicon DRAMS these stacked capacitors are formed by alternating layers of polysilicon conductors and SiO, insulators fabricated by a complex and ingenious sequence of deposition and selective etching. There is no fundamental reason why these steps cannot be performed on GaAs substrates. In effect, we are proposing that the storage capacitor need not be integral to the GaAs substrate, but could simply be deposited on the top surface after all the GaAs active devices are fabricated. This would open the possibility for a number of different structures, including metaloxide-metal capacitors, stacked capacitors such as shown in Fig. 56, and capacitors having a ferroelectric material as dielectric. C . Nondestructive Readout Cells
Another direction that shows great promise are GaAs DRAM cells that provide nondestructive readout with internal gain. Two types of structures are known to be under investigation (Cooper, 1989; Hetherington, Klein, and Weaver, 1991). One such structure, the bipolar/field-effect (BiFET) cell (Cooper, 1989), is shown in Fig. 60. Here the basic bipolar cell of Section V has been modified by the addition of a second base contact. This second contact allows the base layer to function as the channel of a lateral JFET,
70
JAMES A. COOPER, JR
-
Gate / Emitter Source / Base
P
I 30 nm undoped
r-
Y
N GaAs P+ GaAs N+ GaAs
Drain / Base
P
I l
FIGURE 60. A proposed bipolar-field-effect (BiFET) DRAM cell. The cell operates as a bipolar storage cell as described in Section V. Once a potential is stored on the floating collector, the depletion region of the collector-base junction modulates the lateral conductivity of the base layer. By establishing two ohmic contacts to the base, it is possible to detect the charge state of the floating collector by measuring the current between the two base contacts. In effect, the base forms a lateral JFET, gated from above by the emitter and from below by the floating collector.
gated from the top by the emitter and from the bottom by the floating collector. As a result, the current in the JFET is controlled by the potential of the floating collector, providing nondestructive readout. Because the cell now has gain, a robust signal can be placed on the bit lines during readout. Data is written to the cell in the conventional way using the bipolar access transistor (see Section V). The additional requirements on the base layer place new constraints on the design of the cell. In particular, the base layer thickness and doping must be adjusted to allow significant modulation by the floating collector. This must be accomplished without sacrificing the operation of the bipolar access transistor, both in the forward and inverse modes. Work is proceeding on these design issues, but no insurmountable problems are foreseen. The design problem is made more tractable by the several degrees of freedom inherent in the structure. Adjustable parameters include the base doping and thickness, the logic voltages on the floating collector, and the bias voltage on the emitter during readout. In addition, the use of heterojunctions at the emitter-base and collector-base junctions would improve bipolar operation, further relaxing the design constraints. In addition to providing nondestructive readout for digital (binary) memories, the BiFET cell can also be used as an analog memory. This mode of operation opens the possibility for several new applications, one of which is in the field of artificial neural networks. This will be discussed in Section
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
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D. Ultra-Long Storage Times: Quasi-Static and Nonvolatile DRAMs As pointed out in the introduction to this section, storage times in GaAs memories have increased dramatically in recent years. In simple GaAs bipolar DRAM cells, storage times in excess of 4 hr at room temperature are now routinely obtained. For many applications such as cache memory, in which paging occurs at predictable intervals, storage times of this magnitude allow the cell to be operated essentially as a static memory, without the need for refreshing of any kind. Moreover, the bipolar DRAM has the unique feature that storage is accomplished with no external bias applied to the cell. This is because the bipolar access transistor is a current-controlled device and is off when the base current is 0. Thus, bipolar DRAMs can be used in applications where data is to be retained during temporary power losses, provided such interruptions are short compared to the normal storage time of the memory. In this mode, the memory is considered “nonvolatile,” at least for limited periods of time. What if the storage time could be extended to the order of days, months, or even years? In a moment, we will show experimental evidence that such storage times may indeed be possible. But first, we should point out the potential advantages that this type of nonvolatile memory would have in comparison to nonvolatile memories available today. In present-day nonvolatile memories in silicon, a charge is injected onto a floating gate by tunneling through a thin tunnel oxide or by avalanche injection over the potential barrier of a thicker oxide (Kahng and Sze, 1967; Frohman-Bentchkowsky, 1974; Nishi and Iizuka, 1981). Storage times are measured in years, but writing operation is quite slow, typically on the order of 100psec per bit, and writing requires pulse voltages much larger than the normal 5 V supply voltage. Therefore, operation is effectively restricted to read-only memory (ROM) applications, and the devices are variously referred to as programmable ROMs (PROMS), electrically alterable ROMs (EA-XOMs or E-PROMS), or “flash” E-PROMS. The bipolar DRAM, on the other hand, achieves nonvolatile storage from its inherently long charge recovery time and does not depend on tunneling or avalanche injection across an oxide barrier. As a result, electrical writing is expected to be very fast, typically on the order of nanoseconds or less per bit, and operation as a high-speed read-write memory is not compromised. Silicon E-PROMS also suffer from a wearout mechanism that limits the number of times the memory can be reprogrammed to around 106-107times. Although this is not a limitation when the memory is used as a ROM, it does preclude use of these devices in RAM applications, where lo6 writing operations can occur in a few seconds of real time. The bipolar DRAM suffers from no comparable wearout mechanism.
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JAMES A. COOPER, JR
As stated earlier, storage times on the order of months to years may be possible using the basic bipolar DRAM structure of Section V, provided a suitable semiconductor material is utilized. One particularly attractive material for such applications is silicon carbide (Sic) (Davis et al., 1988). This is because S i c has a band-gap almost three times as large as silicon and twice as large as GaAs. S i c occurs in both cubic and hexagonal forms. Cubic (“beta”) S i c has a lattice constant of 4.359A and a band-gap of 2.3eV. Hexagonal (“alpha”) S i c occurs in a variety of polytypes, each having a hexagonal basal plane but with different stacking sequences in the vertical direction. The most useful polytype is “6H,” with a band-gap of 2.9 eV. Both beta and 6H material have been used to fabricate electronic devices (Kong et al., 1987; Palmour et al., 1991), including MESFETs, JFETs, MOSFETs, and bipolar transistors. 6H-Sic wafers are available commercially from Cree Research, Inc., Durham, NC, and are now grown at a number of research laboratories in the United States, Europe, Japan, and the states constituting the former Soviet Union. S i c is physically robust, being one of the hardest and most chemically inert materials known to humankind. It is thermally stable, and electronic devices retain good electrical characteristics to very high temperatures. MOSFET operation has been demonstrated (Palmour, Kong, and Davis, 1987) to 65OoC, and packaged devices operate reliably for extended periods at temperatures up to 35OoC, limited by the thermal stability of the package. Therefore, a major application for S i c is high-temperature and high-power electronic devices. For further information on S i c crystal growth, fabrication techniques, and electrical properties, the reader is referred to the literature. In order to evaluate S i c for use in long-term dynamic memory applications, we have investigated the storage time of npn storage capacitors in 6H-Sic (Gardner et al., 1991). A cross section of the experimental device is shown in Fig. 61. All layers are doped in situ during epitaxy. Circular npn diodes are isolated by reactive ion etching and passivated with S O z formed by wet thermal oxidation. Ohmic contacts are annealed Ni. Capacitance recovery times are measured on various devices using the techniques described in Section 11. Referring to equations (33) and (34) of Section 11, we are reminded that the recovery time of a pn junction storage capacitor is expected to increase exponentially with band-gap energy as exp (EG/2kT), assuming that generation lifetimes in the materials are comparable. Since the band-gap energy of 6H-Sic is 1.48eV greater than the band-gap of GaAs, one expects the storage time at room temperature to be larger by a factor of exp(28.6) or approximately 12 orders of magnitude. Alternatively, we expect to observe the same storage time as GaAs at an absolute temperature that is higher by the ratio of the band-gaps, or approximately a factor of 2. This means that S i c devices should exhibit
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
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Ni Ohmic Contact
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FIGURE 61. Prototype n-i-p-i-nstorage capacitor fabricated in 6H-Sic for storage time measurements. The etched surfaces are passivated by thermal SiO, grown by wet oxidation.
storage times at 600 K (3OOOC) that are comparable to those of GaAs at room temperature. Figure 62 shows storage time versus temperature for several Sic diodes (Cooper et al., 1991). As predicted, storage times on the order of 10 min are observed at 300°C. All diodes have an activation energy around 1.48 eV, close to half the band-gap. If we extrapolate these data to room temperature, we would predict a storage time of about loi3sec, or about 300,000 years! Of course, such an extrapolation is not realistic - other mechanisms having lower activation
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JAMES A. COOPER, JR.
energies (or not thermally activated at all) will become dominant before room temperature is reached. The point, however, is that thermal generation is not likely to limit storage times in these devices. How long will room temperature storage times be? That question is difficult to answer with any confidence, since it will require actual room temperature measurements over extended periods of time. Such measurements have not yet been attempted. To summarize, we have shown the possibility of one-transistor memories having exceedingly long storage times at room temperature. For practical purposes, such memories can be regarded as static. In addition, since the bipolar cell requires no external bias to retain data, these memories are also nonvolatile. Because they can be written in nanoseconds, these devices can be used in high-speed RAM applications. E. Nonconventional Applications
TOconclude this chapter, we wish to suggest some nonconventional applications for these compact storage devices. Dynamic memory is usually associated with digital electronics. However, the applications we will describe in this section use the fact that the dynamic memory is inherently an analog device. The basic elements of the dynamic memory cell, storage capacitors and access transistors, are utilized in a number of analog applications such as switched capacitor filters. In addition, the basic capacitor structure, which has been optimized for exceedingly low dark current, is ideal for use in low-light-level imagers. Perhaps the most novel application, one that has arisen only in the last few years, is in the emerging field of electronic neural networks. We will describe this particular application next. Artificial neural networks are electronic circuits that embody many of the features of biological neural systems (Hopfield, 1988; Lippmann, 1987). In particular, they are highly interconnected networks composed of a large number of very simple identical elements. The basic elements of neural networks are neurons and synapses. In electronic neural networks, neurons are simple amplifiers having saturating (or sigmoidlike) input-output characteristics. The input to each neuron is a summing node connected to a large number of surrounding neurons by resistive connections called synapses. An example of a simple electronic neural network is shown in Fig. 63. Here the network consists of a row of amplifiers (neurons) whose outputs are brought around to a matrix of resistive connections (synapses). The synapse matrix forms the interconnections between neurons. One simple way to visualize the operation of a neural network is to define an energy function for the network. This energy function depends on the output voltages of the neurons in the array. If there are n neurons, the energy function is defined on an n-dimensional space. The exact dependence of the
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
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FIGURE63. Illustration of a simple Hopfield neural network. The network consists of a row of amplifiers (neurons) whose outputs are brought around to a matrix of resistive connections (synapses). The synapse matrix forms the interconnections between neurons. Programming is accomplished by specifying the strengths of the resistive connections in the synapse matrix.
network energy on the individual neuron voltages is determined by the resistive weights of the synapse elements in the interconnection matrix. Thus, the information content of the network, in effect its programming, is contained in the resistive weights of the synapse connections. One use of such a neural network is in pattern recognition. Suppose that an input pattern (which could be an optical image, a fragment of speech, a radar signature, etc.) is to be classified based on a number of predetermined “example” patterns, To be specific, let us assume that the network is to identify a two-dimensional image as belonging to one of 26 possible classes: the letters of the alphabet. The weights in the synapse matrix of the neural network are selected so that the energy function of the network exhibits local minima. Each local minimum corresponds to one of the “example” patterns that are acceptable answers to the identification problem. The inputs to the neurons are then preset to potentials that correspond to the input image to be identified. This, in effect, places the network in an initial condition at some point in the n-dimensional parameter space corresponding to the input pattern. The network is then allowed to settle into the local energy minimum that is “nearest” the starting point. This minimum corresponds to one of the 26 possible “answers” - the 26 letters of the alphabet. In this way, the network performs a natural minimization function, determining which “example” pattern is the minimum distance from the input pattern.
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JAMES A. COOPER, JR
The question of how to specify the weights in the synapse matrix so that the local minima in the energy function are efficiently placed is a subject of current research. However, for our purposes it suffices to understand that the network is “programmed” by specifying these synapse weights. To perform a meaningful pattern recognition task, the electronic neural network must be of sufficient size. In particular, the number of local minima in the energy function grows approximately as the square root of the number of neurons. Unfortunately, the number of synapse connections grows as the square of the number of neurons. It is easy to see that simply identifying the letters of the alphabet would require perhaps a few thousand neurons and a few million synapses. How does all this relate to dynamic memories? In Section C , we described a combination bipolar-field-effect (BiFET) cell capable of nondestructive readout of stored information. We now suggest that this BiFET cell can be used to implement a very compact synapse connection for electronic neural networks. As discussed earlier, the potential on the floating collector in this device serves to back-gate the channel of the lateral JFET formed by the base layer. Thus, the conductance of this lateral JFET can be programmed to an analog value by storing the proper voltage on the floating collector. The JFET is then used to provide the desired resistive connection required of the synapse element. An illustration of the use of the BiFET cell in a synapse array is shown in Fig. 64. We assume that the weighting information is stored off-line in a conventional semiconductor memory. This weighting information is then loaded into the BiFET array using the data lines shown. Once initialized, the BiFET array is ready to provide weighted synapse connections for the neural network. Since it is important that the analog voltage in each cell does not change appreciably, the array will need to be refreshed in a time that is much shorter than the l/e storage times previously quoted for our DRAM cells. However, considering the long room-temperature storage times of GaAs bipolar cells (not to mention the storage times of S ic cells), such periodic refreshing should not be a significant problem, particularly since the normal settling time of the neural network is on the order of a few microseconds. The use of dynamic storage for the synapse weights allows the network to be reprogrammed on-the-fly to solve different classification problems, in effect becoming a general-purpose neural computer. In conclusion, we have pointed out a number of nonconventional applications for dynamic storage devices. The ultra-long storage times now being realized make possible a number of novel applications, as diverse as nonvolatile digital memory and high-density neural networks. The evolution of nonsilicon dynamic memory devices has been rapid, and a number of exciting directions are opening for future development.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
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FIGURE 64. Realization of a Hopfield network using the BiFET storage cell of Fig. 60 as a programmable analog synapse element. Synapse weights are entered using the horizontal “data” lines.
REFERENCES Auret, F. D., Myburg, G., Bredell, L. J., Barnard, W. O., and Kunert, H. W. (1991). 16th Int’l Conf. on Defects in Semiconductors, Bethlehem, PA. Batey, J., and Wright, S. L. (1986). J. Appl. Phys. 59, 200. Bedair, S. M., Tischler, M. A., Katsuyama, T., and El-Masry, N. A. (1985). Appl. Phys. Lett. 47, 51.
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Davis, R. F., Sitar, Z., Williams, B. E., Kong, H. S., Kim, H. J., Palmour, J. W., Edmond, J. A,, Ryu, J., Glass, J. T., and Carter, C. H., Jr. (1988). Mat’l. Sci. and Engr. B1, 77. Dungan, T. E. (1989). Ph.D. dissertation, Purdue University, West Lafayette, IN (available as Tech. Rept. TR-EE 89-47). Dungan, T. E., Neudeck, P. G., Melloch, M. R., and Cooper, J. A,. Jr. (1990). IEEE Trans. Electron Devices ED-37, 1599. Fiedler, A., Chun, J., and Kang, D. (1988). IEEE GaAs IC Symposium Tech. Dig. 67. Frenkel, J. (1938). Phys. Rev. 54, 647. Frohman-Bentchkowsky, D. (1974). Solid-state Electron. 17, 517. Gardner, C. T., Cooper, J. A,, Jr., Melloch, M. R., Palmour, J. W., and Carter, C. H., Jr. (1991). 4th Int’l Conf. on Amorphous and Crystalline Silicon Carbide and Other IV-IV Materials, Santa Clara, CA. Hetherington, D. L., Klem, J. F., and Weaver, H. T. (1991). IEEE ELectron Device Lett. EDL-13, 146.
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ADVANCES IN ELECTRONICS AND ELECTRON PHYSICS VOL . 86
Recent Advances in GaAs Dynamic Memories JAMES A . COOPER. JR . School of Electrical Engineering. Purdue University. West Lafayette. IN
I . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . A . Introduction and Background . . . . . . . . . . . . . . . . . B. Motivations for the Development of DRAM Technology in GaAs . I1. pn-Junction Storage Capacitors . . . . . . . . . . . . . . . . . . . A . General Description . . . . . . . . . . . . . . . . . . . . B. Charge Storage on pn Junctions . . . . . . . . . . . . . . . . C . Theory of pnp Storage Capacitors . . . . . . . . . . . . . . . D . Experimental Results . . . . . . . . . . . . . . . . . . . . . I11. JFET and MESFET DRAM Cells. . . . . . . . . . . . . . . . . A . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . B. Implementations of JFET and MESFET DRAM Cells . . . . . . C . Effect of Transistor Gate Leakage . . . . . . . . . . . . . . . D . A 4-Bit JFET Dynamic Content-Addressable Memory . . . . . . IV . Heterostructure DRAM Cells . . . . . . . . . . . . . . . . . . . . A . Introduction . . . . . . . . . . . . . . . . . . . . . . . . B . Undoped Heterostructure DRAMs . . . . . . . . . . . . . . . C . Quantum-Well Floating-Gate DRAMs . . . . . . . . . . . . . D . Modulation-Doped Heterostructure DRAMs . . . . . . . . . . . V . Bipolar DRAMs . . . . . . . . . . . . . . . . . . . . . . . . A . Introduction . . . . . . . . . . . . . . . . . . . . . . . . B. Concept of the Bipolar DRAM Cell . . . . . . . . . . . . . . . C . Experimental Results . . . . . . . . . . . . . . . . . . . . . VI . Future Directions . . . . . . . . . . . . . . . . . . . . . . . . A . Introduction . . . . . . . . . . . . . . . . . . . . . . . . B. Trench Capacitors and Stacked Capacitors in GaAs . . . . . . . C . Nondestructive Readout Cells . . . . . . . . . . . . . . . . . D . Ultra-Long Storage Times: Quasi-Static and Nonvolatile DRAMs . E . Nonconventional Applications . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . .
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1. INTRODUCTION. MOTIVATION. AND POTENTIAL APPLICATIONS A . Introduction and Background
The evolution of electronic systems inevitably creates demand for integrated circuits with higher integration densities. higher speeds. and lower power consumption. Often the performance of a system is limited by a relatively 1
Copyright 0 1993 by Academic Press. Inc . All rights of reproduction in any form reserved . ISBN 0-12-014728-9
2
JAMES A. COOPER, JR.
small number of components in certain critical paths, so that improvements in the speed of these components reflect directly in enhanced performance of the system as a whole. The desire for high-speed integrated circuits for such applications has led to the investigation of GaAs as a host semiconductor for high-performance systems. The trend toward programmable digital systems has intensified the need for large quantities of high-speed digital memory. To date, most of the memory development in GaAs has been based on simple adaptations of existing GaAs circuit technology in the form of six-transistor static storage cells (Fiedler, Chun, and Kang, 1988; Makino et al., 1988, 1990; Vogelsang et al., 1988; Terrell, Ho, and Hinds, 1988; Maysue et al., 1989; Nakano et al., 1990), as shown in Fig. l(a). These cells are organized in a two-dimensional array to form a random-access memory (RAM). Circuits of up to 16 kilobit complexity have been demonstrated, with access times in the 3-7 nsec range. While straightforward to design and build, these static RAM (SRAM) cells are inefficient in two respects: they occupy considerable chip area, and they dissipate static power in the storage state. In silicon integrated circuit technology, the majority of large-scale RAM circuits are one-transistor dynamic RAMS (DRAMs) of the type shown in Fig. l(b). The one-transistor DRAM cell is much smaller than the six-transistor SRAM cell and dissipates negligible standby power, thus permitting large arrays to be incorporated on a single chip. The one-transistor cell consists of a storage capacitor and a single access transistor. In operation, the access transistor is turned on by the word line, electrically connecting the storage capacitor to the bit line. The storage capacitor is then charged to the potential of the bit line, representing either a logic 0 or a logic 1. When the access transistor is turned off by the word line, the storage capacitor is isolated from the bit line and remains charged to the former bit-line potential until leakage currents eventually destroy the stored information. This gradual degradation of the stored potential requires that the storage cell be periodically read and refreshed. The refreshing period must be substantially shorter than the storage time of the weakest cell in the array at the highest operating temperature. In silicon DRAM systems, refresh rates in the neighborhood of 1 kHz are commonly used, and therefore the weakest DRAM cell must have a storage time greater than about 20msec at the highest temperature. The storage capacitor in most silicon DRAMs is a metal-oxide-semiconductor (MOS) capacitor, made possible by the high-quality SiO, insulator formed by thermal oxidation of silicon. One of the obstacles to the development of DRAM cells in GaAs has been the lack of a high-quality native oxide. However, it has been found that charge storage in GaAs can be successfully accomplished using the capacitance of properly designed reversebiased p n junctions. As evidence of progress in this area, Fig. 2 shows the
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES Bit Line
VDD
VDD
3
Bit Line
+ Bit Line
Word Line
(b) FIGURE 1. Six-transistor static RAM cell (a), and one-transistor dynamic RAM cell (b). Static RAM cells in GaAs usually use MESFETs or JFETs.
evolution in room temperature storage time of GaAs homojunction capacitors over the past four years. Note that storage times have increased about one order-of-magnitude every two years and are now over 10 hours at room temperature. These results are far superior to those observed in silicon MOS capacitors. Several types of access transistors are possible in GaAs. These include metal-semiconductor field-effect transistors (MESFETs), junction field-effect transistors (JFETs), modulation-doped field-effect transistors (MODFETs), and heterojunction bipolar transistors (HBTs). All have been investigated
4
JAMES A. COOPER, JR.
loo I
,
1986
,
'
'
' ' ' ,
1987
'
1988
' ' ,
'
1989
' ' '
'
'
1990
' ' '
'
, ' ' ,
1991
I
1992
Year FIGURE 2. Room temperature storage time of GaAspn homojunction storage capacitors as a function of year since development began in 1987. The trend line indicates one order-ofmagnitude increase every two years.
and will be discussed and compared in Sections 111-V. At this point, however, it is appropriate to consider possible applications for GaAs DRAMS. B. Motivations for the Development of DRAM Technology in GaAs As mentioned previously, digital systems in GaAs will require digital memory, and in order to preserve the speed advantage of GaAs systems, this memory must be fast. As a specific example, consider a GaAs microprocessor operating at a clock rate of 200MHz (5nsec cycle time). Such a processor would be similar to the 32-bit GaAs RISC microprocessor designed by Texas Instruments as part of the VSHIC program (Whitmire, Garcia, and Evans, 1988). A typical instruction requires several accesses to external memory. The simple instruction shown in Fig. 3(a) consists of four cycles: fetch instruction, decode instruction, fetch data, operate on data. Each cycle requires 5 nsec, for a total of 20 nsec for the entire instruction. However, if the program and data are stored off-chip in a silicon memory, operation is slowed considerably. For example, assume a 20nsec silicon SRAM is used. Then each external memory access requires the insertion of three "wait states," bringing the total instruction time to 50 nsec, as shown in the bottom half of Fig. 3(a). Now suppose instead we place a high-speed GaAs cache memory on the same chip as the microprocessor. Assuming a good ratio of cache "hits," the wait states can be eliminated and the instruction execution time decreases by a factor of 2.5. Figure 3(b) shows system throughput as a function of CPU cycle time for two cases: (i) when each memory access must be directed to a 20 ns off-chip RAM, and (ii) when each access can be handled by a 0.5 ns
RECENT ADVANCES I N GaAs DYNAMIC MEMORIES
5
Simple 4-Cycle Instruction Format
-
Decode
Fetch Instruction
I Instruction 1 I
+t
Fetch Data
Operate on Data
I
I
I
cycle
Introduction of Wait States to Accomodate Slow Memory (5 ns cycle time, 20 ns memory access time)
Fetch
I
Wait Wait Wait
I
I
I
Decode Fetch Data
I
I
Operate
Wait Wait Wait
I
D~~
I
CPU Clock Rate (MHz) 1oooo
1000
1000
100
1
10
100
10
0.1
Cycle Time (ns)
FIGURE 3. Part (a) shows a basic four-cycle CPU instruction. Assuming a 5 nsec CPU cycle time, each access to a 20 nsec external memory would require the introduction of four wait states, increasing the execution time to 10 CPU cycles. In part (b) we illustrate the impact that a 0.5 nsec on-chip cache memory would have on system performance as a function of cycle time, assuming a unity cache hit ratio.
on-chip cache memory. It is apparent that the benefits of cache memory increase significantly as the CPU cycle time decreases. In order to be useful, a cache memory must be sufficiently large to ensure a good ratio of cache “hits.” A typical size would be 16 kilobytes (131,072
6
JAMES A. COOPER, JR.
bits). If such a memory were constructed with six-transistor static RAM cells, it would probably be too large to be included on a GaAs microprocessor chip. However, such a cache memory could be implemented using one-transistor dynamic RAM cells without excessive area penalty. There are other motivations for the development of dynamic memory technology in GaAs. A dynamic memory is inherently an analog device, and several specialized applications exist for analog storage. Examples include switched capacitor filters and electronic neural networks (see Section VI). In addition, the basic information obtained in the course of DRAM development is applicable to any device or circuit that requires low leakage, such as GaAs dynamic logic or low-dark-current imagers. As an example, GaAs DRAM research has led to a technique for reducing the subthreshold current in GaAs MESFETs by three orders of magnitude (see Section 111). In the sections that follow we will consider the factors limiting long-term charge storage on pn junctions in GaAs. We will then describe several types of one-transistor DRAM cells, including JFET, MESFET, MODFET, heterojunction, quantum well, and bipolar cells. We will conclude with a discussion of future directions, applications, and opportunities. 11. PN-Junction Storage Capacitors
A . General Description
Dynamic charge storage in GaAs can be accomplished quite efficiently using the capacitance of a properly designed reverse-biased p n junction. In this section we will first discuss the operating principles and design considerations for pn junction storage capacitors. We will then present experimental data on the performance of GaAs p n junction capacitors as a function of doping, geometry, and temperature. To begin, let us consider the pnp test structure shown in Fig. 4. Here the central n-layer is floating, and forms two back-to-back pn junctions with the surrounding p-type layers. The storage time of these back-to-back p n junctions is tested as follows: A bias Vpof either polarity is applied across the structure. This forward biases one p n junction and reverse biases the other. In the process, electrons are removed from the floating n-region across the forward-biased junction, leaving the n-layer at a positive potential. In steady state, the potential of the n-layer is essentially equal to V,, since the steady-state current will be negligible unless the reverse-biased junction is driven into breakdown. When the applied bias is returned to 0, the charge on the n-region redistributes between the two junctions in such a way that both are reverse biased. The n-region is now floating at a positive potential
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
P GaAs Substrate
FIGURE 4. Schematic of a pnp charge storage capacitor, with junction voltages defined for further analysis. Note that the voltage polarities are chosen so that positive values indicate reverse bias.
somewhat less than V,, as determined by the capacitance divider formed by the two junctions. The storage capacitor will gradually discharge as thermal generation supplies electrons to the positive n-region. This discharge can be monitored by observing the capacitance of the two back-to-back junctions, as illustrated in Fig. 5. Immediately following the bias pulse, this capacitance is small due to the large depletion regions of the reverse-biased junctions. As thermal generation returns the structure to equilibrium, the capacitance gradually rises to the value determined by the zero-bias depletion widths of the two junctions. For discussion purposes, we define the storage time as the time required for the capacitance to return to within l/e (36.8%) of its equilibrium value. In designingpn junction storage capacitors, two objectives must be kept in mind. First, we wish to maximize the charge storage density at a given voltage; i.e., the capacitance per unit area of the junction. Second, we wish to minimize the generation current that discharges the capacitor. Up to a certain point, both these objectives may be met by increasing the doping on both sides of the junction. There is, however, a limit beyond which increasing the doping will actually increase the generation current per unit area and reduce the storage time. These effects will be discussed later in this section. Before moving to a more detailed discussion of charge storage in the pn junction capacitor, however, we will anticipate the final results of this chapter by
8
JAMES A. COOPER, JR.
FIGURE 5 . Capacitance transient observed on a symmetrically-doped pnp storage capacitor. For t < 0 the bias is 0 and the structure is in equilibrium. A bias pulse V, is applied at I = 0 and removed at I = to. During the bias pulse, one junction is forward biased while the other is reverse biased. Electrons are removed from the n-region by the forward-biased junction, leaving that region positive charged. The capacitance decreases due to the increased depletion width of the reverse-biased junction. At t = to the bias is returned to 0. The n-region remains positively charged and both junctions are now reverse biased. Thermal generation gradually returns the structure to equilibrium. The capacitance recovery is approximately exponential in time, with time constant T ~ .
revealing that, by proper design, it has proven possible to achieve both high-charge storage densities (1.85 fC/pm2for a single junction or 3.7 fC/pm2 for a pnp structure at 1 V reverse bias [Dungan, 1989; Dungan et al., 19901) and long storage times ( 2 10 hours at room temperature [Stellwag, Melloch, and Cooper, 1991b]) using pn-junction storage capacitors. B. Charge Storage on pn Junctions 1. Steady-State Relationships
In order to examine the most important features of charge storage on p n junctions, we will make a number of simplifying assumptions. We assume an abrupt (step) junction having uniform nondegenerate doping on each side, as shown in Fig. 6 . We also assume that all dopant atoms are ionized at the temperatures of interest. Employing the depletion approximation, it is easy to show that the maximum electric field, which occurs at the metallurgical
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
9
Mx -X
0
FIGURE 6 . Cross section of an abrupt pn junction. The voltage polarity is defined so that a positive value represents a reverse bias.
junction, is given by
where E, is the semiconductor permittivity, NA and No are the doping on the p and n sides, respectively, and xp and x, are the depletion widths on thep and n sides. These depletion widths can be expressed in terms of the total potential drop across the junction as
Here VAis the applied voltage, taken to be positive under reverse bias, and V,, is the built-in potential of the junction, given by (4)
where q is the electronic charge, k is Boltzmann’s constant, T is absolute temperature, and niis the intrinsic carrier concentration at temperature T. The capacitance of the junction serves as a useful indicator of the electrostatic state at any given time and is given by
where A is the junction area. Finally, we will calculate the charge storage density of a pn junction. The charge per unit area removed from the junction under reverse bias VAis given
10
JAMES A. COOPER, JR.
where xpoand xn0are the equilibrium values of xpand x,. Making use of either (2) or (3), the charge stored per unit area at reverse voltage V, is
Here we see that the charge storage density increases as the square root of doping and also as the square root of (VB,+ 5 ) .The maximum charge storage density is limited by junction breakdown. In GaAs, to achieve breakdown fields requires charge densities in excess of 5 fC/pm2.However, a more reasonable value for maximum charge storage density is in the range of 1-2 fC/pmz. This is comparable to the planar charge storage densities presently achieved in silicon dynamic RAMS. 2 . Generation Mechanisms In describing the operation of a pnp storage capacitor, we indicated that if the voltage is quickly swept back toward 0, the charge removed from the n-region will not change appreciably. The rate at which charge “leaks back” onto the n-region is a central issue in DRAM cell operation. Working toward an understanding of the charge recovery transient in a pnp structure, we first need to consider the generation mechanisms responsible for leakage in reverse-biased pn junctions. Electron-hole pairs can be created by thermal generation, photogeneration, or impact ionization. Assuming the capacitor is kept in the dark and that internal fields are low enough that impact ionization can be neglected, the primary leakage mechanism is thermal generation (Dungan, 1989). Thermal generation can occur within the depletion region itself or in the neutral bulk within a diffusion length of the depletion region. We will show that generation in the neutral bulk can be neglected compared to generation in the depletion region. Finally, thermal generation may occur along the periphery of the device, where thepn junction is exposed by a mesa etch. This “edge” generation will prove to be important and must be included in calculation of the charge recovery transient. Thermal generation may involve either direct band-to-band transitions or transitions through defect centers in the forbidden band-gap (ShockleyRead-Hall generation). Because of the greater energy required for each transition, band-to-band generation is much less likely than generation by means of defect centers (SRH generation). Therefore, we will neglect bandto-band generation in the discussions which follow.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
11
a. Generation in the Depletion Region. The bulk generation rate per unit volume due to a single-level defect center at energy ETis given by (Shockley and Read, 1952)
n: - np (8) zp(n + n1) + TAP +PI) Here n and p are the electron and hole densities, z, and 7p are electron and hole lifetimes, and n, and p , are constants that depend on the energy E T of the defect center. Since we have assumed nondegenerate material, the carrier densities can be written
G=
n = niexp( F,, T - Ei
)
(9)
where F, and Fp are the quasi-Fermi levels for electrons and holes, and E, is the intrinsic Fermi level, usually taken to lie approximately at midgap. The constants n, and p, are the carrier densities that would be present if the respective Fermi levels lay at the energy ET. Therefore, we can write
PI =.PI(
T)
- ET
The np product in the numerator of (8) can be obtained by multiplying (9) and (10): np = n:exp( F" -7;T-) -Fp It is commonly assumed that the quasi-Fermi levels can be extended across the depletion region of a pn junction with essentially zero slope. Under this assumption, the splitting of the quasi-Fermi levels within the depletion region is equal to the applied voltage, and (13) may be written np
= n:exp(
%)
Combining (8)-(12) and (14), we can write
Equation (15) gives the generation rate per unit volume at any point within
12 1.5
,
JAMES A. COOPER, JR.
,
,
,
,
,
,
,
,
N A = N D = l x l O ” cmm3
-
. c
V*=5V 1.0
-
0.5
-
i
1
0 b‘
u
,
0.0
I
,
t i , ;
FIGURE 7. Generation rate per unit volume as a function of position in the depletion region, calculated using (15). Here we have assumed a symmetrical junction with midgap generation centers.
the depletion region. To calculate the total leakage current per unit area arising from generation within the depletion region, we need to integrate (15) with respect to position from one edge of the depletion region to the other: + XP
Jdepl
=4
G ( 4&
(16)
The integration in (16) is complicated by the fact that the terms (F, - E,) and ( E , - F,) in (15) are strong functions of position. The simplest way to evaluate the integral in (16) is to recognize that the integrand is very nearly a rectangular function of position. Figure 7 shows the generation rate given by (15) as a function of position for a typicalpnjunction. Note that G(x) goes exponentially to 0 wherever either (F,, - E T ) or ( E , - 4 ) is positive. When both (F,, - E T ) and (ET - F,) are negative, the exponential terms may be
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
13
neglected and (15 ) reduces to G=“[l %
-exp(s)]
where z, is a generation lifetime given by %=
p
e(E~-EOIkT
+
n
e(E,--Er)IkT
(18)
In the typical case, V, 9 kT/q, so that (17) becomes simply G = ni/zc.The leakage current can then be expressed as
where W, is the generation width, defined as the region within which (Fn- E,) and (E, - F,) are negative; i.e., the region where F, < E, < Fp.
b. Generation in the Neutral Regions. Hole-electron pairs that are thermally generated withln one diffusion length of the edge of the depletion region can also contribute a leakage current that will discharge the capacitor. This diffusion current is described by the Shockley diode equation:
where D,and Dpare diffusion coefficients, L, and Lpare diffusion lengths, and npo and pnoare equilibrium minority carrier concentrations for electrons and holes, respectively. This diffusion current arises as a result of the concentration gradient of minority carriers in the neutral regions adjacent to the edge of the depletion region. Under sufficiently large reverse bias (V, > 0), the minority carrier concentrations at the edge of the depletion regions are essentially 0, while deep within the neutral regions they are at their equilibrium values: npo= n f / N Aand pno= $IND. This concentration gradient gives rise to a steady diffusion current in the reverse direction. In GaAs pn junction storage capacitors, however, this diffusion current is negligible compared to generation within the depletion region (Dungan, 1989). This can be seen by the following calculation: At room temperature, n: in GaAs is approximately 4 x 10l2cm-6 while the doping densities N, and ND for typical storage capacitors are in the range lO”-lO’*~m-~.Thus the equilibrium minority concentrations npoand p,,,, are typically on the order of lo-’ ~ r n at - ~room temperature. Assuming reasonable values for diffusion coefficients and diffusion lengths, we estimate a total diffusion current of about 2000 carriers/(cm2s). If the capacitor has an area of 10 x 10 pm’, the Carrie&, or total diffusion current discharging the capacitor is only 2 x one carrier returned to the storage capacitor every eight minutes. Since the
14
JAMES A. COOPER, JR.
minimum charge stored on the capacitor is at least lo6 carriers, this leakage rate is totally negligible. c. Generation at the Junction Perimeter. Leakage current arising from generation at the perimeter of the storage capacitor must also be considered. Experimental measurements on real storage capacitors indicate that a substantial portion of the leakage current is due to such generation. At etched surfaces the termination of the crystal lattice gives rise to a continuum of generation-recombination centers distributed across the bandgap in energy. The total generation rate per unit area at the perimeter can be calculated by summing the contributions from generation centers at various energy levels across the band-gap. Thus, in analogy to (8), we may write (Schroder, 1987)
where n, and p , are the carrier densities at the surface, ,c, and c,, are capture coefficients of surface centers for holes and electrons, and D,T(E) is the density of surface centers at energy E measured per unit area per eV. The terms nls and pisare functions of energy E and are analogous to the n, and p i terms defined for bulk centers in (11) and (12) earlier. As in the case of bulk generation, we regard (21) as representing the surface generation rate at one point within the depletion region and integrate (21) with respect to position within the depletion region. Thus, by analogy to (16), the surface generation contribution to current in the depletion region is given by
j
+X P
J W P
=4
GP(x)dx
(22)
- Xn
In order to calculate this integral, we recognize that n, and p s are functions of x,and that the G, in the integrand will be negligible except in the region WGpwhere both n, and p s are small compared to ni. Since n, and p , are negligible within W,,, the integrand GPis independent of position and can be taken outside the integral in (22). Thus, combining (21) and (22) using these considerations leads to
where s, is identified as the surface generation velocity. Equation (24) for surface generation in the depletion region is the direct counterpart to (19) for bulk generation in the depletion region.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
15
3. Charge Recovery Transient
Combining (19) and (24) and taking into account the area and perimeter of the junction leads to an expression for the total generation current discharging the p n junction storage capacitor
z = ( ~ c e p )l A +
( ~ d e p 1 . P )= ~
qni
[(3) + w,,s)P] 7,
A
(
(25)
Using (6), the total charge stored on the capacitor can be written
Q = qNA(xp - x p ~ ) A (26) where xp is the depletion width on the p side of the junction and x is the 40 value of xp in equilibrium. To maintain charge neutrality, we require that NA ( x p - x p O ) = ND ( x n - xnO) (27) where x, and xd are the actual and equilibrium values of depletion width on the n-side of the junction. Denoting (x, + x , ) by Wand (xpO xd) by Wo,we can write
+
In order to write the differential equation governing charge decay in a p n junction charge storage capacitor, we must obtain expressions for the effective generation widths W, and W, in (25). The generation width W, was introduced in (19) and defined as the width of the region where F, < E, < F,. For the most general situation where NA # No and E , # E,, the expressions for W, as a function of bias are cumbersome (Dungan, 1989). However, if the generation centers lie very close to midgap ( E , x E,) and the junction is symmetrically doped (NA= ND = NB),then the expression for the generation width W, is simplified considerably. Under these assumptions, one can show that W,
(W - W,). . .if NA = ND and E,
= E,
(29) where W is the depletion width at reverse bias and W, is the equilibrium depletion width ( VA= 0). If we further assume that the generation width at the perimeter is the same as the generation width in the bulk, we can write (Dungan, 1989) that -+
w,=
W,,=(W-
Inserting (30) into (25) yields
W,)=- 2Q qAN,
16
JAMES A . COOPER. JR
Equation (31) has the solution
Q(r)
=
Q(0)eKf’7s
where tS is the storage time constant defined by
Equation (33) is extremely important to understanding the capabilities of pn junction storage capacitors in GaAs. As will be confirmed by experimental measurements in Section II.C, (33) tells us that the storage time should be a strong function of temperature, since the intrinsic carrier concentration ni increases exponentially with temperature according to
where N, and Nvare the effective density of states in the conduction band and valence band, respectively, and EGis the band-gap energy. Although N,, N,, and E G are weak functions of temperature, the dominant temperature dependence arises because of the kT factor in the exponent. Thus, if (34) is inserted into (33), one expects that a plot of In (tS)versus l/Twould be linear with a slope approximately equal to EG/(2k).In other words, the storage time of a pn junction storage capacitor decreases exponentially with temperature. A second point that is apparent from an examination of (33) is that a plot of 1 / t S versus ( P / A ) should be linear, with slope 2nis,/NB and intercept 2n,/NBt,. From such a plot, it should be possible to estimate both the surface generation velocity and the generation lifetime at a given temperature. A final point should be made with regard to (30)-(33). In developing these equations we have assumed a symmetrically doped junction with generation centers at midgap. If either of these assumptions fail, our equations have to be modified. In the general case where ND# NAor E , # E,, WGis larger than ( W - W,) and the ratio of WG/( W - W,) is bias dependent (Dungan, 1989). As a result, the charge recovery transient in (32) is no longer exactly exponential, and the storage time in (33) loses its special significance. A recovery time can still be defined, however, but it becomes bias dependent. We will touch on this matter again in Section II.C.2. C. Theory of pnp Storage Capacitors Having considered the generation mechanisms and charge recovery transient in pn junctions, we now return to the pnp storage capacitor structure shown
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
17
in Fig. 4. The behaviour of this structure was described qualitatively in Section 1I.A. 1. Steady-State Capacitance- Voltage Relationship At this point we wish to calculate the capacitance-voltage relation of the pnp structure shown in Fig. 4.We assume that, in general, the two pn junctions are not doped symmetrically, and we designate the doping of the top layer NAl and the bottom layer NA2.When a bias is applied across the pnp structure, negligible current will flow in steady state, since one of the pn junctions is reverse biased. Consequently, the voltage drop across the forward-biased junction is also negligible, and virtually all the applied voltage develops across the reverse-biased junction. Thus, the total capacitance of the structure is that of two capacitors in series, one at essentially zero bias and the other reverse biased by an amount V,. Assume that V, > 0, so that the top junction is forward biased and the bottom junction is reverse biased. Under these conditions (and assuming the dopings NAIand NA2are within about two orders of magnitude of each other) the capacitance of the top junction CJ,(0) will be larger than the capacitance of the bottom junction cJ2( V,). Equation ( 5 ) can be used to calculate both these capacitances. The total capacitance of the pnp structure measured in steady state is then
The total charge stored is given by (7) evaluated for the reverse-biased junction (junction 2):
The steady-state capacitance-voltage relationship (V, swept away from 0 ) is illustrated for two values of NA2in Fig. 8. Note that if the doping is not symmetrical (i.e., NA2# NAI), the capacitance-voltage relationship will not be symmetrical about VA= 0. Figure 8 shows a decreasing capacitance when the voltage is swept away from 0 in either direction (assuming quasi-steady-state conditions), and a different, almost flat, capacitance if the voltage is swept rapidly back toward 0. The capacitance remains nearly constant when the voltage is swept toward 0 because the charge Qlotal removed from the n-region during the outward sweep cannot be quickly restored when the voltage is reduced. Again, assume that V, > 0, so that the top junction is forward biased and the bottom junction is reverse biased. When the applied bias is swept toward 0, the charge Q,,,,, , which originally resided entirely on the bottom junction, must
18
JAMES A. COOPER, JR. 4.0 10
3.5 10
. E
N -
3.0 10
8 .-0
c)
p
0
2.510 2.0 10
-5
-4
-3 -2
-1
0
1
2
3
4
5
Applied Voltage (V)
FIGURE8. Capacitance-voltage curves of a pnp storage capacitor for two different values of doping in the second pf region.
now redistribute between the two junctions in such a manner that the total voltage drop across both junctions adds up to V, . Thus, the voltages V, and V, must satisfy
where Qto,,, is given by (36) when V, reaches its maximum value on the outward sweep. At the same time, we can write
-v,+v,=V,
(38)
Substituting ( 3 8 ) into (37) yields
Equation (39) can be solved for V, as a function of VA.The capacitance of the pnp structure as VAis swept back toward 0 is then given by
where V, is obtained from the solution of (39). Depending on the relative dopings N,, and N A 2 ,the capacitance may increase or decrease as VAis swept toward 0. An example of C-V relationships for both symmetrical and asymmetrical doping is shown in Fig. 8. The value of V, that satisfies (39) when V, = 0 is of particular importance, since this is the voltage across each of thepn junctions at the end of the "write pulse." It is this voltage that determines the generation widths W, and W,, at the start of the charge recovery transient.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
19
2. Capacitance Recovery Transient (Dungan, 1989) Assume that the pnp structure has been ,pulsed to a specific voltage V, = Vp, resulting in a stored charge QtOmi, where Qtotai is given by (36).If the structure is symmetrically doped ( N A i= NA2),the charge Qtota, divides equally between junctions 1 and 2. If we further assume that each junction individually is symmetrically doped (N,, = NA2= N,, call this value of doping NB)and that the dominant generation centers lie at midgap (E, = Ei),the charge recovery transient of each junction is given by (32), with Q(0) set equal to Qtota,/2.The instantaneous charge on each junction given by (32) can be related to an instantaneous value of depletion width using (28). Thus, combining (32) and (28), we can write for each junction that Q(t)
Qtotai
= -exp 2
(- t/z,)
=qANB 2 ( W ( t )-
6)
(41)
Solving for W(t), W ( t ) = W,+-exp(-t/z,) Qtotai qANB Since the capacitance of the pnp structure is that of two junctions in series, we can write
As can be seen from (43), the capacitance transient that occurs due to generation within the pn junction is not exponential, but rather the reciprocal of a constant plus an exponential. Plots of (43) for NB = 5 x 10’7cmp3and pulse voltages of 1,2, and 5 V are shown in Fig. 9 as symbols. One is tempted to view the curves in Fig. 9, as truely exponential; i.e., as represented by an equation of the form C(t) = C,, - [C,,- C(O)]exp ( - t / z c )
(44)
In fact, the lines in the figure (barely visible beneath the symbols) are least-squares fits of (44)to the “data” represented by the symbols. The agreement would appear to be excellent, but the time constants zc obtained by the fit are approximately 9, 16, and 32% longer than z, for the 1, 2, and 5 V curves, respectively. Under the assumed conditions of symmetrical doping and midgap generation centers, we can derive an expression relating the measured capacitance recovery time constant zc to the actual charge recovery time constant z, by
20
JAMES A. COOPER, JR.
h
2
8 a C .-8
c)
P 0
610.’
510-8
4 10 -
1
0
1
2
3
4
5
t l zs
FIGURE 9. Capacitance recovery transients (symbols) calculated from (43) for a symmetricalpnp storage capacitor with NA = ND = 5 x lO”cm-’ and pulse voltages of 1,2, and 5 V. The solid lines (almost obscured by the symbols) are least-squares fits to (44).Although the fits appear to be quite good, the time constants T~ obtained by the fitting are longer than T~ by 9, 16, and 32%, as shown on the figure.
equating (43)and (44).As shown by Dungan (1989), this ratio can be written
Here e is the base of natural logarithms (e = 2.7182). The time constant ratio in (45)is typically between 1 and 2. In particular, since Qtota, increases as the square root of pulse voltage V, through (36), the capacitance recovery times observed in experiments will be voltage dependent, increasing as pulse voltage is increased. This is consistent with the trends in Fig. 9. As stated, such variations are typically less than a factor of 2 over the normal range of pulse voltages used (1 V < I V,l < 5 V). Note that the charge recovery time constant ss is not voltage dependent (see eq. 33) - rather it is our approximation of zs by zc that is voltage dependent. The preceding discussion required the rather restrictive assumptions that both junctions are symmetrically doped ( N A ,= ND = N A 2 ) and that the dominant generation centers lie at midgap (ET = Ei). These restrictions may be removed through a more careful calculation of the generation volume, the region where FN < ET < F,. The mathematics involved are straightforward but tedious (Dungan, 1989) and will not be reproduced here. However, an example of such a calculation is shown in Fig. 10. Here we plot the normalized capacitance recovery transient for two pulse voltages and three generation center positions. All six curves are calculated assuming that the effective generation current per unit volume in the depletion region, Jeff (A/ cm’), is equal to unity. The “time” axis actually represents the time integral of the charge density generated per unit volume in the depletion region during
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
21
1.o
0.8 0.6 0.4
0.2 0.0 0.00
0.01
0.02
0.04
0.03
JEFFt (C/cm
0.05
3,
FIGURE10. Normalized capacitance recovery transients for a nonsymmetrical pnp capacitor ( N A ,= NA2= 1 x 10’8cm-3,ND = 1 x l O ” ~ m - ~for ) two pulse voltages and three generation center energies. The horizontal axis is “time” multiplied by the effective generation current per unit volume Jeff= qn,(l/s, + s,P/A).
the recovery. Actual times can be computed by dividing the normalized “time” axis by Jeff = qn,(l/tG s G P / A ) . One observes that the capacitance recovery time constants in Fig. 10 (the point where the normalized capacitance is 0.632) are dependent both on initial bias and on the energy of the generation center. Again, higher pulse voltages lead to longer capacitance recovery times. However, as stated earlier, the variations are typically less than a factor of 2. We shall see that these corrections are small compared to the range of storage times that arise due to variations in the design of the storage capacitors and the procedures used to fabricate them. In the sections that follow, we will make no particular distinction between the capacitance recovery time constant tC and the charge recovery time constant tS and will simply refer to the measured capacitance recovery time constant as the “storage time” ts.
+
3 . Charge Removal Transient
In the development in Section II.C.1, we made the tacit assumption that charge is removed instantaneously from the n-region whenever a bias V, is applied across the pnp structure. This is not the case, and in fact the charge removal transient that occurs on the application of bias can be extremely slow in a higher band-gap semiconductor material such as AlGaAs or Sic. To obtain closed-form expressions for the charge removal transient, we will consider the simple circuit consisting of a forward-biased diode charging a capacitor, as shown in Fig. 11. For this development, we assume the capacitor has a fixed value independent of voltage. The capacitor is initially at zero voltage, and a bias 6 is applied across the diode-capacitor combination at t = 0. We wish to obtain an expression for the voltage V , across the
22
JAMES A. COOPER. JR
I +
t=O
-
T
VA
7i7T FIGURE11. Simple circuit model for visualizing the charge removal transient in a pnp capacitor structure.
capacitor as a function of time. The current flowing through the forwardbiased diode may be written 1 = lo ( e q ' ~ ' ~ ' - 1) = C dQ
dt
(46)
where Qc is the charge on the capacitor and I, is the saturation current density of the diode given by I,
=
ya.i(0" + L~NA
--)
0,
LpND
(47)
It is significant to note that I, varies as the square of n,. Since n, decreases exponentially with band-gap energy, as shown by (34), I, may be extremely small in high-band-gap semiconductors at room temperature. The charge on the capacitor can be written Qc = cvc = C ( ~-A VD)
(48)
and its derivative is
Combining (46) and (49) gives a differential equation that may be solved for Vo(t).After algebra, we find that
where
T,,
given by
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
10.1510-1310-11
l o - O 10-7 .,0-5
23
lo-3
t IT,
FIGURE 12. Diode voltage drop as a function of time for several values of applied voltage
6 during the charge removal transient. The write time can be made arbitrarily short if the write
process is terminated before the diode voltage reaches 0. For example, if we are willing to provide a write voltage V, that is 0.25 V greater than the final value of capacitor voltage (allowing VD to be 0.25V % 10kT/q at the end of the write process), then the write time can be reduced to 10-~~,.
is the time for a steady current I, to charge the capacitor C to a potential kT/q. Equation (50) is plotted for several values of V, in Fig. 12. If V, b kT/q and t -g q,, (50) can be simplified to
This relationship explains the linear dependence of the V, = co curve in Fig. 12. It is perhaps more enlightening to plot the capacitor voltage as a function of time, as shown in Fig. 13. The point to note from both figures is that the capacitor charges to within VD(t)of the pulse voltage V, in a specific time t , regardless of the value of VA. Therefore, if we wish to charge the capacitor to a voltage V,, in time t , , this can be accomplished by applying a pulse voltage V, given by V, = V,, + V D ( t l )where , V D ( t lis ) obtained from (50) or Fig. 12. These arguments can be refined by including the specific voltage dependence of the capacitance using (5). This is left as an exercise for the reader.
D . Experimental Results 1. Eflect of Temperature
Consider a large-area storage capacitor in which bulk generation dominates
24
JAMES A. COOPER, JR.
lo-’
10.5
10’
t IT,
FIGURE13 Capacitor voltage as a function of time for several values of applied voltage VA the capacitor dunng the charge removal transient. Note that at a specific time, say t/ro = voltage falls short of the applied voltage VAby the same amount, regardless of the value of VA. This “shortfall” is, of course, the diode voltage drop.
(A/PS
sGtG) so
that the storage time constant given by (33) can be written
Inserting (18) and (34) into (53) and assuming that (i) the dominant generation center is above midgap (this assumption is arbitrary, and equally valid equations would result if the opposite assumption were made), and (ii) z, is of the same order of magnitude as r P ,leads to
where AET = IE, - E l / .Equation (54) suggests that the storage time will be thermally activated with an activation energy EAgreater than or equal to half the band-gap. (Note that we would have reached the same conclusion if we had assumed the generation center to be below midgap, except that t pwould be replaced by 7,). To further appreciate the temperature dependence of (54), note that N , and N y are proportional to T3I2and that T~ is inversely proportional to the thermal velocity vth, which increases as TIi2.Thus, the prefactor is proportional to (1 / T)’. This dependence, however, is overshadowed by the temperature dependence of the exponential factor. In the exponent, the band-gap energy EG is a weak function of temperature and can be approximated by a firstorder Taylor expansion as EG(T) % E G O
-
UT
(55)
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
25
Temperature ("C) 181
144
111
2.4
2.6
84
60
40
21
3.0
3.2
3.4
F8
d
I"
2.2
2.8
1000/T
(1IK)
FIGURE14. Measured capacitance recovery time constants as a function of temperature for pnp capacitors in GaAs and Al,Ga,_,As (x x 0.2). The recovery process is thermally activated, with activation energies very close to half the band-gap.
where EGO is the extrapolated zero-temperature band-gap and ci is a parameter. For GaAs in the neighborhood of room temperature (Thurmond, 1975), EGO z 1.56eV and ci = 4.17 x 10-4eV/K. Inserting (55) into (54) yields
The first exponential term is now explicitly temperature independent. From the second exponential term, we see that the activation energy should be greater than or equal to half the extrapolated zero-temperature band-gap, which for GaAs is about 0.78 eV. Figure 14 shows measured storage times (Dungan, 1989) forpnp capacitors fabricated in GaAs and Al,Ga,-,As (x z 0.2). These capacitors were grown by molecular beam epitaxy (MBE) and were mesa isolated by chemical etching. The doping and thickness of the layers are the same. The storage times in Fig. 14 are indeed thermally activated, as required by (56), and the activation energies are consistent with generation sites at or very close to midgap (AETz 0). In considering the magnitudes of the storage times, we note that dynamic memories in silicon are typically refreshed at a 1 kHz rate, so that the storage times of individual cells must be longer than the refresh period of 1 msec. To take a conservative view, we shall require a storage time of at least 100msec
26
JAMES A. COOPER, JR Temperature (“C) 182 l0000
144
111
2.4
2.6
84
60
40
21
5
2.8
3.0
3.2
3.4
3.6
1000 100 10 1 0.1 0.01 2.2
lOOO/T(1/K)
FIGUREIS. Capacitance recovery time constants for three GaAs pnp capacitors having different doping concentrations. The doping on the lightly doped side is given in the legend. The ~ ~ Note the reduction longest storage times are obtained for dopings in the low l O ’ ’ ~ n -range. in activation energy for the most highly doped sample (0 1990 IEEE).
for GaAs-based memories. By this criterion, Fig. 14 indicates that both these (unoptimized) pnp storage capacitors would be capable of satisfactory operation to over 100°C. 2. Effect of Doping
Equation (33) indicates that the charge storage time constant T~ is expected to scale directly with doping. This is because higher dopings result in smaller depletion regions, and generation within the depletion region determines the storage time. Also, (7) tells us that the charge storage density, i.e., the charge stored per unit area at a given voltage, increases as the square root of doping. Since long storage times and high-charge storage densities are both desirable, it would appear that high doping levels on both sides of the junction are called for. Figure 15 shows measured time constants for three pnp storage capacitors grown by MBE and mesa isolated by chemical etching (Dungan, 1989; Dungan ef al., 1990). All growth and processing conditions were the same except for the doping of the layers. In all three structures the n-layer is doped 1 x l O ” ~ m - ~The . p-layer dopings are 7 x 1015cm-3,1 x 1017cm-3,and 1 x 1019cm-3.All three capacitors are effectively one-sided step junctions, with the generation occurring primarily on the lightly doped side. The doping of the lightly doped side is shown in the figure. (Note that for the sample with NA = 10’9cm-3,the lightly doped side is the n-region, ND = l O ” ~ m - ~ ) . Equation ( 3 3 ) suggests that the charge recovery time constant should scale linearly with the doping of the lightly doped side. Figure 15 shows that
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
27
recovery time indeed increases with doping up to about 1 x 1017cm-3. However, the sample with dopings of 1 x 1018cm-3exhibits a reduced time constant at all temperatures and a reduced activation energy. Thus it appears that there is a practical limit above which further increases in doping actually reduce the storage time. The reduced storage time of the most highly doped sample can be explained by the phenomenon of field-induced barrier lowering. This effect occurs when electric fields within the depletion region become high enough to modify the escape energy of carriers confined on a generation center. This can occur when the potential drop over a distance comparable to the radius of the electron orbit is significant compared to the ground-state energy of the center. Frenkel(l938) showed that the change in escape energy AEA is given by -
AEA = 2q/$
(57)
where F is the electric field in V/cm. Thus, AEA calculated by (57) can be viewed as the reduction in activation energy resulting from field-induced barrier lowering. Applying this correction to the data of Fig. 15, we obtain AE, values of 90, 180, and 330meV, respectively, for the three curves of increasing doping density. These values correspond approximately to the differences between activation energies seen in the figure. It has been found experimentally (Dungan, 1989; Dungan et al., 1990) that higher doping levels can be used successfully if a small undoped (or lightly doped) i layer is inserted between the p and n-type regions in each junction, resulting in a p-i-n-i-p structure such as shown in Fig. 16. The i layer has the effect of reducing the maximum electric field in the depletion region, thereby avoiding the barrier lowering phenomenon, while maintaining a very highcharge storage density (high capacitance per unit area). The storage times of two p-i-n-i-p storage capacitors are compared to a pnp storage capacitor of similar doping in Fig. 17. 3. Eflect of Device Area and Device Scaling In order to construct a high-density memory array using p n junction storage capacitors, it is important that the size of the capacitor be reduced as much as possible. Two issues arise immediately: (i) charge storage capacity and (ii) storage time. Clearly, as the area of the capacitor is reduced, the amount of stored charge is reduced proportionally. What is perhaps not immediately apparent is that the storage time is also reduced. We shall consider both of these limitations in this section. First, we consider the charge storage capacity. To permit reliable detection
28
JAMES A. COOPER. JR.
i (undoped) 30nm
N+ 10’’ cmJ i (undoped) 30nm
FIGURE16. Storage capacitor having p-i-n-i-p structure. The presence of the undoped i layers reduces the maximum electric field in the junction, minimizing field-induced barrier lowering, while still providing a high capacitance per unit area.
of the signal charge during readout and to minimize soft errors due to alpha particle strikes, a dynamic memory must store a certain minimum charge in each cell. In silicon dynamic memories, this minimum is typically on the order of lo6 electrons. To understand how this restriction affects the GaAs storage cell, let us consider the p-i-n-i-p capacitor of Fig. 16. For this capacitor, the Temperature (“C) 182 10000
144
111
84
60
40
21
5
2.4
2.6
2.8
3.0
3.2
3.4
3.6
1000
100
sE H
10 1
0.1 0.01 2.2
10001T(IIK)
FIGURE17. Capacitance recovery times for pnp and p-i-n-i-p storage capacitors. By introducing an i layer, we are able to avoid the reduction in room temperature storage time caused by field-enhanced generation.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
29
Square Edge Length (pm) 198
98
78
62
5.0
.-cE
6.25
0.16
a,
0.12
8.33
8
0.08
12.5
0.04
25.0
P
f
-
3 v
$
C
0
0 100 200 300 400 500 600 700 800
Perimeter / Area (Ilcm)
FIGURE18. Inverse storage time of square pnp capacitors as a function of P / A ratio at several temperatures. At each temperature, the generation lifetime T~ is calculated from the intercept and the surface generation velocity sc from the slope.
charge storage density of each junction is about 1.85fC/pm2 at a reverse voltage of 1V. Accounting for both junctions, the area required to store lo6 electrons would be 43 pm2 or 6.6pm on a side. This area would be reduced if a higher signal voltage were used. A reasonable lower limit would appear to be around 25 pm2 or 5 pm per side.’ Next we consider the effect of scaling on storage time. One obvious geometrical consequence of reducing the capacitor area is the fact that the perimeter-to-area ratio P / A increases. Taking the inverse of (33),
(-+
1 =2ni 1 TS
NB
sG;)
TG
This implies that a plot of inverse time constant versus P / A should produce a straight line whose slope is determined by the surface generation velocity and whose intercept is determined by the bulk generation lifetime. This is illustrated by the data (Sheppard, 1991) in Fig. 18 for four different temperatures. The inverse storage time increases linearly with P / A , in good agreement with (58). From the slopes and intercepts, we can calculate values of T~ and sG at each temperature using (58). These data are shown in Fig. 19. Here we see that both T~ and sG are relatively weak functions of temperature I As an aside, we note that one wishes to retain lo6 electrons at the end of one refreshing period. We have defined storage time as the time for the electron density to be reduced to l/e of its initial value. Thus, we should store 2.7 x lo6 charges at the beginning of the transient, requiring 2.7 times the quoted area. However, in practice one never allows the charge to decay to lie of its initial value before refreshing. In fact, if we require the storage time to be at least IOOmsec, but refresh at a 1 kHz rate, the initial charge will only decay to 0.99 of its initial value at the end of one refreshing period.
30
JAMES A. COOPER, JR
-
Temperature (“C) 111
104
97
91
84
-‘E In
78
In
Y
r”
C
.-0
e
c)
al c
8 0 Q
lo4 3 2.60
2.65
2.70
2.75
2.80
2.85
h
lOOO/l(lIK)
FIGURE19. Bulk lifetime tG and surface generation velocity sG deduced from the plot of Fig. 18.
(at least compared to the temperature dependence of n,). This slight temperature dependence indicates that the dominant generation centers are not precisely at midgap. The generation lifetime is in the vicinity of 200 ns, which is an excellent value for GaAs. We note that the precise values of T~ are somewhat uncertain, since the intercepts in Fig. 18 are estimated by extrapolation and are sensitive to small errors in fitting the data. Of more practical interest is the time constant to be expected if the area of the storage capacitor is reduced below the 62pm per side of the smallest capacitor shown. If we extrapolate the data in Fig. 18 to a side length of 5 pm, we find a storage time of 1.5 sec at 101OC. This is still comfortably above our criterion of 100msec. Therefore it appears that adequate charge storage densities and acceptable storage times can be achieved with storage capacitors down to 5pm on a side.
4. Metal Evaporation Technique Since storage time is determined by extremely small generation currents, it is to be expected that it should be sensitive to certain details of the processing. One of the most important aspects of the processing in this regard is the method of metal deposition. In fact, the storage time of well-made identically prepared samples is reduced by about three orders of magnitude if the ohmic metal is deposited in an electron-beam evaporator as compared to a thermally heated evaporator (Stellwag et al., 1992a). Figure 20 shows storage time versus temperature for four 100 x 100pm2 p-i-n-i-p storage capacitors (Stellwag et al., 1992a). These capacitors are taken from two wafers whose epitaxial layers were grown by MBE using As, and As, flux, respectively. Both p+ layers are doped 1 x 1019cm-3,the n-layer is
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
/
lo5
5
Thermally
lo3
Evaporated
i!
i=
$
10'
z
d
/
// / AS2
lo-'
10"
E-Beam Evaporated
,
1
I
,
1
,
1
,
1
,
1
1
,
I
,
31
32
JAMES A. COOPER, JR
on the flux conditions during MBE growth. This suggests that, rather than creating new centers, the electron-beam environment is simply activating preexisting centers present in the As-grown film, the density of which depends on the growth conditions. 111. JFET
AND
MESFET DRAM CELLS
A . Introduction
In Section I1 we considered the design and performance of pn junction storage capacitors in some detail. However, the storage capacitor is only half the story. In order to construct a complete DRAM cell, it is necessary to provide an access transistor that will connect the storage capacitor to the bit line for reading and writing and isolate the storage capacitor from the bit line during storage. In this section we will consider two means of implementing this access transistor in GaAs: (i) using junction field-effect transistors (JFETs), and (ii) using metal-semiconductor field-effect transistors (MESFETs). Figure 21 shows how one might implement a one-transistor DRAM cell utilizing a JFET access transistor and a MESFET access transistor. In the following sections we will present experimental results on early versions of both JFET and MESFET DRAM cells, with special attention to the effects of transistor leakage on storage time.
B. Implementations of JFET and MESFET DRAM Cells The first demonstration of a complete JFET-accessed GaAs DRAM cell was reported by Neudeck et al. (1989). The structure, shown in Fig. 22, consists of two large-area p + n storage capacitors surrounded by a ring-gate JFET. Two storage capacitors are used in this implementation so that the charge can be monitored by observing the capacitance between the two p+ plates. This is necessary since the structure is fabricated on a 1 pm undoped buffer layer. The layers are grown by MBE, and the p + gates are patterned by wet etch. The 50nm p-type GaAs layer under the channel is included to improve subthreshold performance of the access transistor, and it is fully depleted during normal operation (Yamasaki, Kato, and Hirayama, 1985). Figure 23 shows waveforms obtained during electrical writing of the cell. The top waveform is the capacitance between the twop+ capacitor plates, the middle waveform is the bit line voltage applied to the source of the JFET, and the lower waveform is a series of 1 msec write pulses applied to the gate of the access transistor (the word line). The word line is held at a negative
33
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES Bit Line
Word Line
PorS.1. GaAs
JFET DRAM Cell
Bit Line
Word Line
ohmic contac
PorS.1. GaAs I
I
MESFET DRAM Cell
FIGURE21. Two examples of FET-accessed DRAM cells in GaAs. Each cell consists of a pn junction storage capacitor and an access transistor. The top drawing depicts a JFET DRAM cell, while the bottom drawing illustrates a MESFET DRAM cell.
potential to keep the JFET biased off. When the word line is pulsed to 0, the JFET is turned on and the potential of the bit line is connected to the storage capacitor. During the first pulse the bit line is positive, and electrons are removed from the n-side of the p n junction storage capacitors. This reverse biases the p n junctions, widening the depletion regions and reducing the capacitance signal. When the second word line pulse occurs, the bit line has returned to 0. This allows electrons from the bit line to flow to the storage capacitors, returning them to their equilibrium conditions. The capacitance is thus increased. One notes that the capacitance signal changes only when the word line is pulsed to 0. This proves that the storage capacitor is effectively isolated by the access transistor: changes in bit line potential have no effect on capacitance while the access transistor is off. The high-capacitance condition occurs when the storage capacitors are in equilibrium, so this state will not decay
34
JAMES A. COOPER, JR. JFET Source (Bit Line)
JFET Drain
JFET Ring Gate (Word Line)
PN Junction Charge Storage Capacitors
50 nm P+ GaAs
FIGURE 22. A prototype JFET DRAM cell implemented in GaAs by Neudeck et al. The cell consists of two storage capacitors surrounded by a ring-gate JFET. Two storage capacitors are used to allow the charge recovery to be monitored by observing the capacitance between the storage gates. A second JFET is included for evaluation purposes (01990 IEEE).
with time. The low-capacitance state represents a reverse bias on the storage capacitor. This is a temporary condition, and the capacitance will gradually return to its equilibrium value as thermal generation discharges the storage capacitor. This can be seen in the waveforms of Fig. 23, where the storage
r
-
1 -
0
L
-2 -
A
4
wPiue I
4 WPite 0
Bit Line Voltage
1 msec Write pulse
--)-
-1
CPII
Capacitance Signal
4 wuiue I
Word Line Voltage
Time (s)
FIGURE23. Writing waveforms for the JFET DRAM cell of Fig. 22. The upper trace is the cell capacitance, the middle trace is the bit line voltage, and the lower trace is the write pulse train applied to the word line. Note that the cell capacitance changes only at the moments when write pulses are applied to the word line. The stored 1 state gradually decays due to gate leakage in 1990 IEEE). the JFET access transistor and generation in the substrate depletion region (0
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
-
-
Storage Node Write Pulse
0
>
35
-1 -
r
;
:
?
,
:
:
;
:
-
;
;
Word Line Voltage
time is estimated to be on the order of 1 s. This low storage time is due to two factors. First, the gate-to-drain leakage current in the access transistor flows directly to the storage capacitor. In this prototype geometry, the access transistor is a ring-gate configuration that actually maximizes the leakage current supplied to the storage capacitor. Second, the large undoped buffer layer below the storage capacitor provides a large generation volume for leakage currents discharging the storage capacitor. During normal operation of a GaAs DRAM cell, the cell capacitance would not be monitored. Instead, the charge state of the cell would be detected by a change in potential of the bit line when the access transistor is turned on. This mode of operation is demonstrated in Fig. 24. Here the bit line is connected directly to a high-impedance active oscilloscope probe. The top waveform in the figure is the potential of the probe, the middle waveform is a write pulse applied to the p + terminal of the storage capacitor, and the bottom waveform is the pulse train applied to the word line. The write pulse (middle waveform) momentarily forward biases the pn junction storage capacitor, removing electrons from the n-region. During the first word line pulse, the JFET is turned on and electrons flow from the bit line to the storage capacitor to restore the missing electrons. This causes the bit line to jump to a positive potential. The rapid decay of the bit line signal is caused by the RC time constant of the active probe. By the end of the first word line pulse, the bit line potential has essentially returned to ground, and as a result the storage capacitor is also essentially at ground, The second word line pulse produces almost no response on the bit line, since the storage capacitor is
36
JAMES A. COOPER, JR.
Alloyed Ohm (Bit Line) Contact
E,
i 0
10pm x 200 p n Au MESFET Ga (Word Line)
0
Storage Node Connection
50 nm
P-
NA = 1 x 10" cm-3
Undoped GaAs
FIGURE25. Top view and cross section of a MESFET DRAM cell implemented by Neudeck et al. This cell employs a linear gate rather than a ring gate, in order to minimize gate leakage current discharging the storage capacitor.
now at ground potential. Thus the charge state of the cell can be determined by detecting the bit line potential when the access transistor is turned on. Similar results have also been achieved using MESFET access transistors (Dungan et al., 1990). Figure 25 shows the top view and cross section of an experimental MESFET DRAM cell (Neudeck, 1991). Notice that in this structure the ring gate has been replaced by a linear gate. Writing waveforms for the MESFET cell are shown in Fig. 26. These waveforms are very similar to those of the JFET DRAM cell in Fig. 23. In order to eliminate the need for a negative supply voltage, the cell is operated with bit line potentials that vary from 1.3V for a logic 0 to 2.45 V for a logic 1. (A thorough discussion of operating voltage considerations for FET-accessed GaAs DRAM cells can be found in Dungan, 1989, and in Dungan et al., 1990). As expected, the cell capacitance changes only when the access transistor is turned on. In spite of the reduced gate width exposed to the storage capacitors, the storage time for this cell is only about 25 msec at room temperature. The drastic reduction in storage time is the result of increased gate leakage in the MESFET as compared to JFET. This effect will be discussed next.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES L
P5
-
3-5
-0
2 -
Q
s”
,
Cell Capacitance Signal
4 :
1
-
5 c
’
37
r
Bit Line Voltage
-_
-
1 -
1 psec Pulse
*-Write
MESFET Gate (Word Line) Voltage
0 I
I
I
I
I
I
I
I
FIGURE 26. Writing waveforms for the MESFET DRAM cell of Fig. 25. The top trace is the cell capacitance, the middle trace is the bit line voltage, and the lower trace is the write pulse train applied to the word line. The access transistor threshold voltage is + 0.8 V, and positively 1990 IEEE). shifted logic levels are employed (0
C . Eflect of Transistor Gate Leakage When an access transistor is connected to the storage capacitor, additional leakage mechanisms are introduced that reduce the storage time of the cell, even when the access transistor is deliberately biased into the off state. These leakage mechanisms are illustrated in Fig. 27. The primary leakage mechanisms are subthreshold leakage of electrons from the source to the drain and leakage of electrons from the gate (or gate depletion region) to the drain. Since the drain is connected directly to the storage capacitor, these leakage paths tend to prematurely discharge the capacitor. Subthreshold leakage from the source can be described by (Conger, (Word Line)
t
4 -
Source
(Bit Line)
ov
IDG
Drain
(Storage Node)
++I++
4
IDS
--r-
FIGURE 27. Drain current components in a GaAs field-effect access transistor. The primary mechanisms affecting DRAM storage time are drain-to-source current I,,, and drain-to-gate current I,.
38
JAMES A. COOPER, JR. 10
10 -5 0..
- VDs = + 0.5V
Transistor
ON
c p! L
a /,
10 -10
-1 .o
-0.5
\
0.0
. 0.5
Gate Voltage (V)
FIGURE28. Drain current as a function of gate voltage in a GaAs field-effect transistor. I,, is the drain-to-source current and IDG is the drain-to-gate current. I,, decreases exponentially with gate voltage below threshold, but eventually I,, dominates. This gate current is not present in silicon MOS transistors, but it is the dominant leakage mechanism in most FET-accessed GaAs DRAM cells.
Peezalski, and Shur, 1988)
Here ZDs, is the current measured at threshold (VGs= VT), V,, is gate-tosource voltage, VTis the threshold voltage, VDs is drain-to-source voltage, and n is a subthreshold ideality factor. If V,, is greater than a few kT, the term in square brackets approaches unity. In any event, the last factor shows that the current decreases exponentially as V,, is reduced below threshold. Unfortunately, one encounters a fundamental difficulty in taking advantage of this exponential reduction in subthreshold current. This is because GaAs, unlike silicon, does not possess a true insulator that can be placed between the gate and channel. As a result, a significant gate-to-drain current can flow whenever the gate becomes too strongly reverse biased with respect to the channel. This is illustrated in Fig. 28, where we show the measured drain current for a GaAs MESFET as a function of gate voltage (Neudeck, 1991). As gate voltage is reduced below threshold, the drain current in Fig. 28 drops exponentially with gate voltage, in agreement with (59). However, a minimum is reached at a gate voltage of about -0.2V; below - 0.2 V the drain current increases. This increase is due to electrons flowing from gate to drain, and the I-V characteristic in this region is that of the reverse-biased gate-to-channel junction. If the transistor of Fig. 28 were used in a p n junction DRAM cell, the storage time would be reduced to a few hundred milliseconds at room temperature. Obviously, there is considerable motivation for minimizing this effect.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
39
o3
1
10-4
*
=: 3
j
105
104 107
lo4 lov 10-10 10 -11
-2.0
-1.o
-1.5
-0.5
0.0
Gate Voltage (V)
FIGURE29. Drain current vs. gate voltage for a 5 x 350pm ring-gate JFET.
For comparable devices, gate leakage is considerably lower in a JFET than a MESFET (Dungan et al., 1990; Neudeck, 1991). Figure 29 shows drain current versus gate voltage for a 5 x 350pm ring-gate JFET, while Fig. 30 shows drain current in a 10 x 350pm ring-gate MESFET. At room temperature, the gate-to-drain leakage in the JFET is more than two orders of magnitude smaller than in the MESFET. Thus, one expects superior storage time performance from a JFET-based memory. It has been found that the gate-to-drain leakage of MESFETs can be reduced significantly by treating the GaAs surface with ammonium sulfide (NH,),S just prior to thermal evaporation of Schottky metal (Neudeck et al., 1991a). (It is important in this procedure that the metal not be deposited in an electron-beam evaporator). Figure 31 shows drain and gate currents at room temperature for treated and untreated 10 x 350pm ring-gate
10.~ 10’~ 10.~
10.’
10.’ 10.10
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
Gate Voltage (V)
FIGURE30. Drain current vs. gate voltage for a 10 x 350 pm ring-gate MESFET. Note that at room temperature the gate-to-drain leakage in the MESFET is more than two orders of magnitude higher than in the JFET of Fig. 29.
40
JAMES A. COOPER, JR
10.~ 10.6 10” 10-8
10.”
lo-’*
-1.o
-0.5
0.0
0.5
Gate Voltage (V)
FIGURE31. Drain and gate currents for a 10 x 350pn ring-gate MESFET with and without (NH,),S surface treatment prior to gate metal deposition. In the treated device the gate current exceeds the drain current for Vc < - 0.3 V because the gate depletion region is punching through to the substrate, causing substrate holes to flow to the gate. This phenomenon has no effect on DRAM storage (01991 IEEE).
MESFETs. The drain current in the treated device is reduced by about three orders of magnitude compared to the untreated device. (In the treated device, the gate current exceeds the drain current below about - 0.3 eV. This excess gate current is due to gate-to-substrate punchthrough, and has no effect on the storage time of the DRAM cell, since it does not flow to the storage capacitor .) The reduction in gate-to-drain current in the treated devices is attributed to an increase in Schottky barrier height that results from an unpinning of the Fermi level (Carpenter, Melloch, and Dungan, 1988). The (NH,)2S layer is thought to passivate most of the surface states that otherwise would exist at the metal-semiconductor interface. Although (NH,),S-treated surfaces degrade within a few hours if exposed to air, the presence of the metal gate protects the (NH,),S layer in these MESFETs. No changes in I-V characteristics could be detected after over a year of undessicated storage at room temperature.
D. A 4-Bit JFET Dynamic Content-Addressable Memory As a final example of demonstration circuits involving GaAs DRAM technology, we consider the four-bit dynamic content addressable memory (DCAM) constructed by Neudeck and coworkers (Neudeck, 1991). In a content-addressable memory, each storage cell contains logic to compare the bit of information stored in the cell with a binary signal presented on the bit line. The organization of a typical content addressable memory is depicted in Fig. 32. Each word in the memory array contains many bits of data stored
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES Bit Line
41
Bit Line
Word Line
Match Line
Word Line
Match Line
FIGURE 32. Schematic diagram of a content-addressable memory. Each memory cell contains logic elements that compare the contents of the cell to the information on the bit lines. If a bit fails to match, the cell pulls its match line to ground. Only if all cells in a word match the input pattern will the match line for that word remain high.
in individual cells connected to a common word line. In addition, the storage cells in each word of a content addressable memory are also connected to a second horizontal line called the match line. To select a stored word based on content, a binary pattern is impressed on the bit lines. Each cell in the memory compares its stored bit to the bit on its bit line. If any cell finds a mismatch, it pulls its associated match line to ground. Only if every bit in a word matches the input pattern will the associated match line remain high. Content addressable memories are useful in situations where large data bases are to be searched rapidly for specific patterns. The GaAs DCAM cell (Neudeck, 1991) is shown in Fig. 33. This cell consists of two JFET DRAM cells and four additional n-channel JFETs used to implement an exclusive-nor (XNOR) function. A unique feature of this design is the fact that an ohmic contact is established to the n-type region of the storage capacitor in each DRAM cell. This contact is connected to the gate of an n-channel JFET in the XNOR logic so that the contents of the cell can be compared with the new data on the bit lines. Altogether, six transistors and two storage capacitors are required per cell. The cell of Fig. 33 is implemented in a 2 x 2 DCAM array, complete with peripheral circuitry to load the memory with initial data, read the stored data using the bit lines, select the word lines, and read the match lines. In all, 40 JFETs and 8 storage capacitors are involved. Figure 34 shows operating waveforms of the 2 x 2 DCAM array. During the first six cycles a distinctive binary pattern (all 0s) is loaded into the
42
JAMES A. COOPER, JR. Word Line I
-
. Bit
Bit Line
Line
Match Line
5 0,
m
L
B L
Storage Node Contact
Storage Capicitor (Gate Metal)
v)
>m
‘DRAM Access JFET
FIGURE33. Schematic of one cell of the JFET DCAM cell (top) and layout of the cell (bottom). Each cell consists of two one-transistor DRAM cells and four n-channel JFET XNOR transistors. A two-level metal process is employed, with the top interconnect metal placed on polyimide for isolation.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
43
Keyword Input (81 & 82) and Match Line Output (M1 & M2)
MI M2
81
881
82
882
Stored Memory Contents
FIGURE 34. Operating waveforms of the 2 x 2 JFET DCAM array. The two match line and four bit line waveforms are shown for six cycles. During each cycle, the memory is loaded with a four-bit data pattern and then presented with nine interrogation patterns. The boxes at the bottom indicate the data pattern written into each word of the memory. The boxes at the top indicate the nine interrogation patterns and the match line responses. A d represents a “don’t care” condition, implemented by taking both bit and bit-bar lines low; d bits always match the stored bit.
memory. In the next nine cycles, all possible binary input patterns (including “don’t care” inputs) are presented and the match line outputs tabulated at the top of the figure. Beginning with the sixteenth cycle, a new data pattern (all 1s) is loaded into the memory and the interrogation pattern repeated. This cycle continues until all stored data patterns are verified with all possible input combinations. In all cases, the DCAM produced the correct outputs. The array was also tested as an eight-bit DRAM. In this mode, the match lines are ignored and the individual DRAM cells in each DCAM cell are written and read out using the bit lines. The array was fully functional in this mode as well.
44
JAMES A. COOPER, JR.
This DCAM array is far too small to be useful, it does not contain all the necessary peripheral logic such as sense amplifiers and address decoders, and it has not been optimized for minimum cell size or maximum speed of operation. Nevertheless, it does demonstrate that GaAs JFET DRAM cells can be combined into a working memory array, that they can be read and written electrically without interference between adjacent cells or excessive cross talk, and that they can be combined with logic within each cell to operate as a content-addressable memory.
IV. HETEROSTRUCTURE DRAM CELLS A . Introduction
Heterostructure DRAM cells have been investigated by several groups. These cells can be classified into two types: (i) generation-limited cells, similar to the pn junction JFET and MESFET DRAM cells already discussed, in which the nonequilibrium state is a deficit of carriers and the cell returns to equilibrium by thermal generation, and (ii) leakage-limited cells, in which the nonequilibrium state is an excess of carriers and the cell returns to equilibrium by leakage of excess carriers over a potential barrier. As we shall see, the generation-limited DRAM designs have been more successful, since generation is characterized by activation energies of at least half the semiconductor band-gap. To create a comparable leakage-limited memory would require a heterojunction band discontinuity of comparable magnitude. Such band discontinuities are difficult to achieve in 111-V material systems. In the following sections we shall first review the results obtained with leakage-limited devices (undoped heterojunction cells and quantum-well floating-gate cells). We will conclude with a discussion of generation-limited devices (modulation-doped heterojunction cells). B. Undoped Heterostructure DRAMS
A storage capacitor employing an undoped heterojunction (Cooper, Qian, and Melloch, 1986) is shown in Fig. 35(a). The barrier layer is undoped Al,Ga,-.As (x = 0.38), and excess electrons are confined in a two-dimensional electron gas (2DEG) in the GaAs adjacent to the heterojunction, as shown in part (b). Figure 36 shows C-V and I-V characteristics of the structure at 77 K in the dark and under white light (Kleine et al., 1989b). In the dark no measurable current flows, and the capacitance is that of an MOS structure in deep
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
45
FIGURE 35. A leakage-limited heterojunction storage capacitor formed by undoped AlGaAs on GaAs. A cross section of the structure is shown in (a) and the band diagram for the interface region is shown in (b). The top Al,Ga,-,As layer has a mole fraction x of 0.38, while the Al,Ga,_,As layers in the five-period superlattice have a mole fraction of 0.30. The superlattice buffer layer is included to improve material quality of the subsequently grown layers. Electrons in the 2DEG tend to escape. over the heterojunction to the GaAs gate. This leakage process limits the storage time of this capacitor.
46
JAMES A. COOPER, JR.
-
I . r L , , , , I , , , ,
I
,
,
, ,
,,
, , ,
,
, , ,
,
,
, , , ,,
1n-‘
10-7
Gate Voltage [V]
FIGURE36. Capacitance- and current-voltage characteristics of the heterojunction storage capacitor of Fig. 35 at 77 K. The current and the upper capacitance curves were taken under white light illumination, and the lower capacitance curve was taken in the dark. The dark current was too small to be measured. The ledge in the light-on capacitance curve indicates that electrons 1989 IEEE). are being stored in the 2DEG (0
depletion - the capacitance decreases as voltage is swept positive due to the expanding depletion region in the p-type GaAs. Under illumination, photogeneration occurs in the depletion region. Holes are swept into the substrate, while electrons drift to the GaAs/AIGaAs interface, where they are trapped in the potential well. As voltage is swept positive under illumination, a capacitance ledge is observed. This ledge is caused by the screening effect of electrons in the 2DEG at the GaAs/AlGaAs interface. The leakage current also increases. This can be explained as follows: At any bias, a steady state exists between electrons supplied to the 2DEG by photogeneration and electrons escaping the 2DEG to the gate or to the substrate. In the ledge region, not all of the photogenerated electrons flow from the 2DEG to the gate. Some are injected to the substrate, where they recombine with holes, producing no current. As the gate voltage increases, field emission and thermionic field emission of electrons from the 2DEG to the gate increase, and an increasing fraction of photogenerated electrons flow to the gate. The capacitance remains almost constant for a range of gate voltages (the “ledge”) because additional charges added to the gate by the increasing gate voltage are imaged by additional electrons in the 2DEG; the depletion region is shielded from the additional charges and does not expand. Eventually, the 2DEG contains the maximum electron density that can be contained behind the finite potential barrier (AEc = 0.3eV). Beyond this point no more electrons can be added to the 2DEG, and the depletion region is no longer shielded from increases in the gate charge. As a result, the capacitance again
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
-1 .o
0.0
47
1.0
Voltage (Volts)
FIGURE37. Transient capacitance decay at several gate voltages at 55K.When light is extinguished, electrons in the 2DEG leak over the heterojunction barrier to the gate, and the capacitance decreases to the dark value. The lack of hysteresis in the C-V curves in depletion (V, < - 0.4V) proves that all the stored electrons have been expelled from the ZDEG, and none 1989 IEEE). are held in traps (0
decreases with gate voltage. The gate current saturates, since now essentially all of the photogenerated electrons are flowing from the 2DEG to the gate. The various processes by which electrons escape the 2DEG are illustrated in part (b) of Fig. 35. These include thermionic emission over the potential barrier to the gate, thermionic-field emission through the top of the barrier, tunneling from quantized energy levels at E, and E , , diffusion into the substrate, and black-body photoemission over the barrier to the gate (Kleine et al., 198913). The rate at which electrons escape determines the storage time. This escape rate can be determined from a capacitance-time (C-t) transient at any voltage in the capacitance ledge region. An example of a series of such C-t transients is shown in Fig. 37. By a careful analysis of the rate of change of capacitance during each transient, the leakage current can be determined as a function of electric field in the AlGaAs and the quasi-Fermi level splitting in the 2DEG. From these analyses it is possible to distinguish which of the several leakage mechanisms in Fig. 35(b) is dominant in each bias region and to determine relevant constants in the mathematical expressions for each leakage mechanism. We shall not go into such detail here; the interested reader is referred to the literature (Kleine et al., 1989b). The major conclusion to be drawn from the work on leakage-limited undoped heterostructure DRAM cells is that storage times are too short to be useful except at cryogenic temperatures. This is illustrated by Fig. 38, where electron density in the 2DEG is plotted as a function of time following extinction of the light (Kleine et al., 1989b). Symbols represent experimental data obtained from capacitance transients, and lines are theoretical predictions based on the known emission mechanisms. One observes that storage
48
I
10'
10'
102
Time [s]
FIGURE38. Stored electron density as a function of time at 50 and 80K. The points represent experimental data at several values of gate voltage, while the lines are predictions of the emission theory of Kleine et al. (1989b). Storage times are on the order of a few seconds at 80 K (0 1989 IEEE).
times of around 1000 seconds are obtained at 50K. However, at 80K the storage times have dropped to the order of a few seconds. Measurements at higher temperatures are not practical due to the short time constant of the C-t transient. Figure 39 shows the heterojunction barriers in the GaAs/AlGaAs system as a function of AlAs mole fraction (Batey and Wright, 1986). The largest conduction band discontinuity, about 0.35 eV, occurs around x = 0.4, where the AlGaAs bandgap becomes indirect. This is very close to the mole fraction of the samples presented in Figs. 35-38. However the valence band discon0.6 0.5
I5 '0
w" U
0.4
0.3 0.2 0.1
0 0.0
0.2
0.4
0.6
0.8
1.0
AlAs Mole Fraction
FIGURE39. Conduction and valence band discontinuities in the AlGaAs ternary system as a function of AlAs mole fraction. The largest discontinuity in the conduction band occurs around x = 0.4,where the AlGaAs becomes indirect. In the valence band, however, the discontinuity increases monotonically as x approaches unity.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
0
I
Barrier Potential Well
-
f
49
AuZn
\
3 N GaAs 1 ~ 1 0 cm3 '~
N+ GaAs Substrate
FIGURE 40. A heterojunctioncapacitor for storing holes at the interface between undoped AlAs and n-type GaAs. The valence band discontinuity at this interface is about 0.55 eV.
tinuity increases monotonically, reaching a maximum value of about 0.55 eV at x = 1. Perhaps an advantage can be gained by storing holes in a twodimensional gas at the GaAs/AlAs interface! Figure 40 shows a heterostructure storage capacitor formed by undoped AlAs and n-type GaAs. This capacitor was also studied by the method of C-t transients (Qian, Melloch, and Cooper, 1986, 1989), and the results for a gate voltage of - 3 V are shown in Fig. 41. Here we see that storage times of tens of seconds are obtained at 100 K, and measurable charge storage persists to almost 200 K. Again, however, room temperature operation is not feasible. In addition to questions of storage time, we must also consider the charge storage density of heterojunction DRAM cells. The hole memory capacitor of Fig. 41 can retain about 8 x 10" holes per cm2at 150 K, while the electron capacitor of Fig. 38 retains only about 1 x 10" electrons per cm2at 80 K. In order to store lo6 carriers, the hole capacitor would need to be at least 1 1 x 11pm2, while the electron capacitor would need to be at least 32 x 32 pm2. In Section I1 we found that pnp homojunction capacitors could be made as small as 5 x 5pmZ. C. Quantum- Well Floating-Gate DRAMS
Two groups have investigated charge storage in quantum wells formed by heterojunctions. The first such structure was reported by Capasso and co-workers (Capasso et al., 1988; Beltram et al., 1988), and is shown in Fig. 42. In this structure a GaAs quantum well, formed between two AlAs barriers, serves as a floating gate for an underlying field-effect transistor. Electrons are injected into the quantum well from the gate by a negative pulse. This injection is aided by grading the band-gap of the barrier layer between the gate and the quantum well. Once stored, the electrons cause a positive shift in the threshold voltage of the underlying transistor. This
50
JAMES A. COOPER, JR. 90 K
vg = -3.0 v
10
.---.
3
N
I
b!
E
L
rl
0
4
x
5
h
Y
v
a
..
A
0
lo-'
I
10"
I
10'
I
102
lo3
t [sec]
FIGURE 41. Hole density in the capacitor of Fig. 40 as a function of time at several temperatures. Hole densities in the low 10" cm-' range can be retained for several seconds at temperatures up to 190K, but room temperature operation is not feasible.
threshold shift can be detected by observing the current in the transistor, providing a form of nondestructive readout. In the GaAs/AlAs version, the room temperature storage time was about 2 sec, increasing to about 4 hr at 77 K. Figure 43 shows drain current transients at 140 K and at room temperature following filling pulses from the gate. From measurements of effective threshold voltage shift, a sheet charge density of about 10l2cm-2 was inferred for the quantum well. A similar structure was investigated by Lott, Klein, and Weaver (1989b). This structure differed from the structure of Fig. 42 in that a variable-period superlattice was used to produce the graded-band-gap effect in the injector region. Storage times of around 1 sec were reported at room temperature, with sheet charge densities above 10''cm-2. The latter workers have also reported similar devices using InAs (wells)/ AlAsSb (barriers) on InAs substrates (Lott et al., 1989a), and using InGaAs (wells)/InAlAs (barriers) on InP substrates (Lott et al., 1990). The InAs/ AlAsSb structures exhibited a l / e storage time of only 50 sec at 77 K. Storage time data was not reported at higher temperatures. The InGaAs/InAlAs devices had storage times of around lOsec at 200K, decreasing to less than 1 s at 250 K. In the latter devices, the dominant mechanism of charge loss was
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
N+Gah 500nm
graded undoped
"raped
AlGaAs 180 nm
1
200 nm
U AlAs 100
nm
51
N SI GaAs OeAS 75 Substrate nm
Equlllbrlum
Du~Ing WRITE phase
FIGURE 42. A floating-gate DRAM cell in which electrons are stored in a GaAs quantum well between two AlAs barrier regions. Electrons are injected from the top gate over a compositionally graded AlGaAs barrier. The presence of electrons on the floating gate modulates the current in the GaAs channel below, providing nondestructive readout (0 1988 IEEE).
identified as horizontal leakage over a lateral potential barrier, rather than vertical emission over the heterojunction discontinuity. The quantum-well DRAM structures described previously are qualitatively similar to the single-heterojunction storage capacitors discussed in Section 1V.B. In both cases electrons are retained behind the potential barrier created by the conduction band discontinuity at a heterojunction. The storage time is determined by the rate at which electrons are emitted over the heterojunction. In comparing the storage times reported for these two types of structures, a striking difference in storage time is apparent: The capacitors of Section IV.B, which were based on the heterojunction between GaAs and Al,Ga,_,As
52
JAMES A. COOPER, JR.
-a -E
2 c5-)/-vw (z
atp= loops
Atp=1 ms
(b)
3
za
4T=300K
a
n
3
I
I
9
5-
T= 140K
-
I
WRITE 4-
0
WRITE
ERASE (SHORT LIGHT PULSE)
2
4 TIME
6
(c)
8
10
(5)
FIGURE 43. Channel current in the floating-gate DRAM of Fig. 42 as a function of time at (a) 140K and (b) room temperature. The current transients have time constants of 4 hours at 140 K and 2 seconds at room temperature. Part (c) illustrates the write-erase operation at 140 K (erase is accomplished by shining light on the sample) (01988 IEEE).
(x = 0.38), had measurable storage times only below 100 K. In contrast, the quantum-well capacitors of Section C, based on the heterojunction between GaAs and AlAs, had storage times of 1-2 sec at room temperature and 4 hr at 140K. What can account for such a dramatic difference? One possible explanation is that the GaAs/AlAs and InAs/AlAsSb systems are heterojunctions between direct band-gap and indirect band-gap semiconductors. Thus, electrons residing in the r valley in the quantum well must be emitted into the X valley in the barrier. The thermionic emission rate of
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
53
electrons over a potential barrier decreases exponentially with the barrier height. However, Solomon, Wright, and Lanza (1986) have argued that when the heterojunction is indirect, the prefactor before the exponential term is diminished, owing to reflections caused by wave function mismatch. A similar argument applies to thermionic-field emission (tunneling). Solomon et af. (1986) have calculated these prefactors from measurements of dc current through n+ in- n+ structures, where the i layers were undoped Al,Ga, -,As (0.3 < x < 0.8) and the doped layers were GaAs. They conclude that the prefactor for thermionic emission decreases by about a factor of 200 at x = 0.8 as compared to the value when x < 0.4. For thermionic-field emission, the prefactor decreases by about a factor of 2500 at x = 0.8. However, Kleine, Melloch, and Cooper (1989a) have pointed out that these decreases are insufficient to explain the reported room temperature storage times of the quantum-well storage capacitors. Kleine et al. measured the transient decay of electron density at the heterojunction between GaAs and Al,Ga,-,As at 55K for mole fractions of 0.4, 0.6, 0.8, and 1. The optimum mole fraction for electron storage at this temperature was found to be between 0.4 and 0.6, and the storage time decreased markedly as the mole fraction approached unity (Kleine et al., 1989a). Moreover, they showed that the storage time of a GaAs/AlAs barrier at room temperature, based on the parameters of Solomon et al., would be less than 1psec. Another possible explanation for the long storage times reported for quantum-well capacitors is charge trapping (Kleine et af., 1989a). It is not possible to determine from capacitance or threshold voltage transients whether the stored charges are mobile or confined in deep traps in the material. Certainly, if charges were confined in traps, the storage times would be much greater than predicted by thermionic emission or thermionic field emission theories. If charge trapping were taking place, the cell would also be highly resistant to electrical erasure, and could not function effectively as a random-access (read-write) memory. Indeed, the floating-gate cells of Capasso et al. (1988) and Beltram et af. (1988) could not be electrically erased, and instead were erased with light. Moreover, evidence of charge trapping in the AlAs was specifically mentioned by the groups investigating GaAs/AlAs quantum-well capacitors (Capasso et al., 1988; Beltram et al., 1988; Lott et al., 1989b). In the single-heterojunction results reported in Section B and in the emission study of Kleine et al. (1989a), charge trapping could be ruled out by the fact that no hysteresis was observed when C-V curves were swept rapidly in both directions (electrical removal of stored electrons). To summarize this rather confusing section, quantum-well storage capacitors have exhibited storage times up to 1-2 sec at room temperature, although some controversy exists regarding the explanation for the storage
54
JAMES A. COOPER, JR.
2DEG
I
.................... P+ GaAs
N AlGaAs
I
P GaAs
P+ GaAs Substrate
FIGURE44. Cross-section and band diagram of a modulation-doped heterostructure storage capacitor. Because of the band banding in the AlGaAs layer, the Fermi level at the interface lies above the conduction band in the GaAs. As a result, a 2DEG will be present at the GaAs/AlGaAs interface in equilibrium.
phenomenon. The issue is made moot, to some extent, by the results obtained with simple pn junction storage capacitors in Section I1 and the results to be reported in the next section. D . Modulation-Doped Heterostructure DRAMS
A heterostructure capacitor employing modulation doping is illustrated in Fig. 44. This type of structure has a distinct advantage over both the undoped heterostructure capacitors considered in Section B and the quantum-well capacitors discussed in the last section. This is because the modulation-doped structure of Fig. 44 is generation limited, in the sense that it retains a two-dimensional electron gas as the equilibrium state. The non equilibrium
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
55
Access
P+ substrate
L--
Storage Capacitor
, Word Ly,
FIGURE45. Cross section of a MODFET DRAM cell. This cell consists of a rnodulationdoped heterostructure capacitor and a MODFET access transistor.
state is achieved by removing electrons, and the structure returns to equilibrium by thermal generation, just as the pn homojunction capacitors of Section 11. Thus one expects storage times in modulation-doped heterostructure capacitors to be comparable to those in p n homojunction capacitors. Figure 45 illustrates a complete one-transistor DRAM cell using a modulation-doped heterostructure (Kleine, Cooper, and Melloch, 1991). A p + GaAs layer is used as the gate of the access transistor and the top electrode of the storage capacitor. This p + layer has a higher barrier to the AlGaAs than a metallic gate, thus reducing gate leakage current in the access transistor (Priddy et al., 1987). The AlGaAs layers have an AlAs mole fraction x = 0.3. The storage capacitor is 187 x 190pmZ,while the access transistor has a gate length of 5Spm and width of 54pm. Storage times of an isolated modulation-doped storage capacitor and a complete DRAM cell are shown as a function of temperature in Fig. 46. As was the case with JFET and MESFET DRAM cells, addition of the access transistor reduces storage times by several orders of magnitude. This is due to gate leakage current flowing when the transistor is biased off. At room
56
JAMES A. COOPER, JR. Temperature ("C) 105f,'
144 .
,
'
111
'
84
'
'
'
60
39
,.
21 ,
1OOO/T (1/K)
FIGURE46. Storage times of an isolated modulation-doped storage capacitor and a complete MODFET DRAM cell as a function of temperature. The isolated capacitor has a storage time of 4.3 hr at room temperature. The storage time of the complete cell is reduced to about 2 min at room temperature because of leakage currents in the MODFET access transistor.
temperature, the storage time of an isolated modulation-doped storage capacitor is about 4.3 hr. In the complete DRAM cell, gate leakage in the access transistor reduces the storage time to about 2min at room temperature. The storage capacitor exhibits two activation energies, indicating two independent generation processes are occurring. The fact that both of these activation energies are greater than half-band-gap suggests generation through centers some distance from the middle of the band-gap. The results shown in Fig. 46 were obtained on cells that had thermally evaporated metal. The use of electron-beam metallization reduces the storage time of isolated capacitors to around 15min at room temperature. This is consistent with the results reported for pn junction storage capacitors in Section II.D.4. Figure 47 illustrates electrical writing of the MODFET DRAM cell. The charge state of the storage capacitor is monitored by measuring the capacitance between the storage gate and the substrate. A gate bias of - 2.9 V was applied to the access transistor during storage, and the gate was pulsed to 0 to write information into the cell. The arrows indicate the points where the MODFET access transistor was momentarily pulsed on. Write pulses as short as 20nsec were effective in writing the cell. Shorter pulses were not investigated due to equipment limitations. It can be seen that for this particular device the room temperature l/e capacitance recovery time is about 3 min. The bit line waveforms during reading are shown in Fig. 48. Here the potential of the bit line is monitored by a high-impedance FET probe. The 2DEG in the storage capacitor is first partially removed by pulsing the
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES 11
0.5
10
0.4
9
0.3
a 0 8 c m c
0.2
E: a v
.-O
7
0.1
Q
6
0.0
m
B -
8
-k 0
-
’ 0
=al C
2
-0.1
5
57
-0.2
4
0
200
100
300
500
400
600
Time (s)
FIGURE 47. Writing waveforms for the MODFET DRAM cell of Fig. 45. Note that the cell capacitance changes only at the instants when write pulses are applied to the word line (indicated by arrows). The storage time of this cell can be estimated from the capacitance transient to be about 3 min at room temperature.
storage gate to a negative bias for sufficient time for the electrons to recombine with substrate holes. The pulse voltage magnitude is indicated on the figure. Note that for the largest pulse voltage shown here (- 1.5V), the 2DEG is still not totally removed, since the threshold voltage for this device is - 2.08 V. The access transistor is turned on at t = 0, which is 50 msec after the end of the emptying pulse. For r > 0, charge sharing occurs between the storage capacitor and the combined capacitance of the bit line and FET probe, resulting in a voltage output proportional to the charge required to refill the storage capacitor. The decay of the output signal for r > 0 is due primarily to the conductance of the FET probe. 0.5
E
-.-m
,
,
I
,
,
,
,
,
,
,
,
,
,
,
,
. , ,
,
,
,
,
300 K
0.4
E: 0.3 al w
tc
0
.4
.=
m
0.2 0.1
0 -10
0
20 Time (ps)
10
30
40
FIGURE48. Bit line waveforms during reading of the MODFET DRAM of Fig. 45 as a function of the write pulse voltage used to empty the storage capacitor. The access transistor is turned on at time t = 0, which occurs 50msec after a I is written to the cell. The storage capacitor contains a partial 2DEG even for the - 1.5 V case, since the threshold voltage for total removal of the 2DEG is - 2.08 V.
58
JAMES A. COOPER, JR.
output
Memory Cel I S
F1
MODFET F3
F2
s
F4
D
500 nm undoped AlGaAa
-
950 nm p AlGaAs
-
360 nm p GaAs
seml-InsulatingG a b substrate
FIGURE49. A modulation-doped heterostructure DRAM cell reported by Chen et al. Electrons are stored in the 2DEG under gate F2, while gates F1 and F3 are used for isolation. The transistor formed by gate F4 is used to buffer the output. During testing, gate F3 was left on permanently. In an actual DRAM, transistors FI and F3 would be replaced by a single MODFET (reprinted with permission of Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts).
A similar modulation-doped heterostructure DRAM cell has been reported by Chen, Goodhue, and Mahoney (1991). This cell, shown in Fig. 49, utilizes a 20 nm undoped GaAs quantum-well channel grown on a fourperiod AlGaAs/GaAs superlattice buffer layer. An undoped AlGaAs layer and a p + AlGaAs barrier are placed under the superlattice to prevent electron emission to the semiinsulating substrate, and a modulation-doped barrier is grown on top of the GaAs channel. All AlGaAs layers have mole fraction x = 0.23. The primary storage gate is labeled F2, and two separate transistors, labeled Fl and F3, are used for writing and reading the cell. An output MODFET, F4, is also included to amplify the signal resulting from charge transfer when F3 is turned on. In functionality demonstrations, however, Chen et al. kept F3 biased on to avoid capacitive coupling between the read pulse and the cell and placed a 1 MQ resistor in series with the gate of F2 to minimize coupling of the write pulse applied to F1. The circuit of Fig. 49 has a storage time of only 250msec at room temperature, probably due to leakage through transistor F3, which is always left on. However, large-area isolated storage capacitors exhibit storage times as long as 5.4sec at room temperature and up to 40 sec at 77 K. The charge storage density is 4.5 x 10" electrons per cm'.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
59
V. BIPOLARDRAMs A . Introduction
In Section I1 we found that the storage time ofpn junction storage capacitors is limited by thermal generation of hole-electron pairs. This process is slow in higher band-gap materials such as GaAs, and well-made storage capacitors can have storage times of several hours at room temperature. In Sections I11 and IV we learned that the addition of a field-effect access transistor (either JFET, MESFET, or MODFET) reduced the overall storage time of the complete cell to the order of 0.1-100sec. This drastic reduction in storage time is due to unavoidable gate leakage when the access transistor is in the off state. We note that silicon DRAM cells avoid this problem because MOS transistors have essentially no gate leakage. The most straightforward way to eliminate gate leakage in the access transistor is to eliminate the gate! This can be done if, instead of a field-effect access transistor, we employ a bipolar access transistor. We should point out that bipolar DRAM cells are really not new, since DRAMs based on integrated injection logic were introduced in silicon in the early 1970s (Sander and Early, 1976; Quinn et al., 1978). These cells worked well, but they offered no particular operational advantage over MOS DRAM cells, since MOS cells in silicon are not limited by gate leakage. However, in GaAs the advantage over FET-accessed cells is enormous. In this section we will discuss the operation of a bipolar DRAM cell in GaAs. B. Concept of the Bipolar DRAM Cell A bipolar DRAM cell in GaAs (Stellwag, Cooper, and Melloch, 1991, 1992) is illustrated schematically in Fig. 50. This cell can be recognized as the basic pnp storage capacitor of Fig. 4 with an additional n-type layer on top. This n-type layer, together with the p - and n-type layers immediately beneath it, form an npn bipolar transistor. This bipolar transistor is merged with the pnp storage capacitor, as indicated in the figure. The base of the bipolar transistor is connected to the word line and the emitter to the bit line. The collector is floating and forms a p n junction with the substrate. The capacitance of this latter pn junction, together with the capacitance of the base-collector junction, stores the charge. Operation of the bipolar DRAM cell is illustrated in Fig. 51. In equilibrium, the n-type collector is at ground potential, corresponding to a stored logic 0 (part a). A logic 1 is written by removing electrons from the collector. This is done by taking both bit line and word line positive, thereby forward
60
JAMES A. COOPER. JR
Bit Line NPN Bipolar Access Transistor
Word Line
t
%
...........
.......
P GaAs N GaAs
Floating Collector
PNP
Storage Capacitor
P+ GaAs substrate
*
FIGURE50. Cross section of a bipolar DRAM cell in GaAs. An npn bipolar transistor is merged with a pnp storage capacitor to form the cell. Alternatively, the cell may be viewed as an npn bipolar transistor with a floating collector, with the collector specially constructed to have a large capacitance to ground.
biasing the collector-base junction (part b). Electrons will flow from the collector to the emitter until the collector-base voltage has been reduced to 0. The collector is now at the potential of the word line. If both bit line and word line are returned to ground, part (c), the collector remains positively charged due to the loss of electrons. The structure is now storing a logic 1. Note that all potentials applied to the cell are now at ground. As a result, the only currents that will discharge the collector are those due to generation in the depletion regions of the two reverse biased junctions. This is the same situation as the pnp storage capacitors of Section 11, where storage times of several hours were obtained at room temperature. Also, note that, since storage takes place with all terminals at ground potential, no power is dissipated in the storage state. Indeed, the memory can be considered nonvolatile, in the sense that all external power can be removed without loss of stored data, at least for times short compared to the normal storage time of the cell. The cell can be written to a logic 0 state by keeping the bit line at ground and taking the word line slightly positive, as shown in part (d). Electrons then flow from the emitter to the collector until the collector-toemitter voltage is 0. In examining the sequence of band diagrams in Fig. 5 1, we note a conflict. To empty the cell, the word line and bit line are taken several volts positive. To fill the cell, however, the bit line is kept at ground and the word line is taken only slightly positive. Since we have no way of knowing whether the bit line will be positive or at ground during a particular writing operation, how can we know to what potential to take the word line? The answer is that the writing operation must be a two-step procedure: First all cells in a word
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES Substrate
61
Floating coiiector
%?* \....
0
.
0
....
(a)
Store Zero (Equilibrlurn)
(b) Read -or-
Write One
0
0
0
(c) Store One
FIGURE 51. Band diagrams illustrating the operation of the bipolar DRAM of Fig. 50. Data consists of the presence or absence of electrons in the floating collector. Electrons are removed by taking both the word line and bit line positive, as shown in part (b). Data is stored when both the word line and bit line are at ground potential, as in parts (a) and (c). Electrons are inserted by taking the word line slightly positive while the bit line is held at ground, part (d).
must be emptied (word line and all bit lines taken several volts positive), then the cells must be selectively refilled, based on the bias state of their particular bit lines (word line taken only slightly positive). From the schematic drawing in Fig. 50, two other advantages of the bipolar cell can be seen. First, the cell conserves area, since the access transistor is vertically integrated on top of the storage capacitor. Second, the cell is inherently fast, since charge transport during reading and writing is vertical rather than horizontal. This latter point deserves further explanation. In FET-accessed cells such as shown in Fig. 21, charge transport occurs laterally along the FET channel. During reading and writing, the storage capacitor in these structures functions essentially as a long-channel FET, and the channel can pinch off, limiting current flow. This pinch-off effect is avoided in the bipolar structure.
62
JAMES A. COOPER, JR.
The bipolar DRAM of Fig. 50 can also be realized as a heterojunction bipolar transistor, or HBT. In the HBT the emitter is formed from AlGaAs, and the base and collector from GaAs. HBTs are widely used in GaAs bipolar circuits because the valence band offset at the emitter-base junction drastically reduces hole injection from the base into the emitter, improving the emitter injection efficiency. This improvement is so great that it is no longer necessary to keep the base doping lower than the emitter doping. The increase in base doping has the added advantage of reducing the base spreading resistance. To apply these ideas to the bipolar DRAM cell, we must consider the requirements on the bipolar access transistor. As illustrated in Fig. 51, the operation of the bipolar DRAM dictates that the access transistor operate in both the forward and inverse modes. When electrons are removed from the floating collector (Fig. 51(b)), the transistor is in the inverse mode, with the collector functioning as an emitter and the emitter functioning as a collector. If we construct the cell using HBT technology, it will be desirable to fabricate both the collector and emitter in AlGaAs to enhance both forward and inverse operations. Therefore, we envision a double-heterojunction bipolar transistor in which the n-type emitter and n-type collector are both AIGaAs. The presence of a heterojunction in the reverse-biased collector-base junction would have minimal effect on forward operation. A further extension would be to make all layers (except the base) AlGaAs, since this would reduce generation in the depletion region of the collectorsubstrate junction. C . Experimental Results A prototype homojunction bipolar DRAM cell is shown in cross section in Fig. 52. This cell was grown by MBE, and metalized using a thermal evaporator (Stellwag et al., 1991a, 1992b). The storage time of the cell is measured by observing the transient recovery of the base capacitance following writing a logic 1. The capacitance transient of a 36 x 48 ,urn2cell at room temperature is shown in Fig. 53. The l/e recovery time is 16,200 sec, or 4 . 5 hr. This storage time is of the same magnitude as storage times of isolated pnp capacitors reported in Section 11, indicating that the presence of the bipolar access transistor has no negative effects on storage time. Figure 54 shows storage time as a function of temperature for several bipolar DRAM cells. An activation energy of 0.88 eV is common to all cells, and larger cells have slightly longer storage times, consistent with the scaling arguments presented in Section II.D.3. The cell is electrically written in Fig. 55. The 3 V, 1 msec word line pulses are not shown, but occur at the points indicated by arrows. Note that the capacitance increases when the bit line is at ground (store 0 state), since this
63
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
p+ GaAs I I
1x10 19cm-3
Access Transistor
100 nm
I GaAs
30 nm 5x10 "cni3
p+ GaAs
I I
200 nm
1x10 '9cmi3 1000 nm
p+ GaAs Substrate
FIGURE 52. Cross section of the experimental device used to verify the operation of the 1992 IEEE). bipolar DRAM (0
returns the cell to equilibrium. When the bit line is positive (store I state), the capacitance decreases. This is because electrons have been removed from the floating collector, widening the depletion regions. The capacitance transient in the store 0 state is due to the turn-off time of the forward-biased emitterbase junction, as excess carriers are removed by recombination. This transient has no effect on operation of the memory. We should emphasize that in the high-capacitance store 0 state, the cell is actually in equilibrium, Time (hours) 1.10
G'
e 8c
m
105
0
-
0
2
.
4
,
10,000
mj. I 6
1
0
10
'
20,000
30,000
.
-
40,000
Time (sec) FIGURE 53 Capacitance recovery transient measured at the base contact of the bipolar DRAM cell of Fig 52 at room temperature A recovery time constant of 4 5 hr is observed (01992 IEEE)
64
JAMES A. COOPER, JR. Temperature ( "C ) 144
111
2.4
2.6
84
60
2.8
3.0
40
21
3.2
3.4
105
1000 / T (1/
1
K)
FIGURE54. Storage time as a function of temperature for several bipolar DRAM cells. All cells have an activation energy of about 0.88 eV. Storage time decreases slightly as the cell is 1992 scaled to smaller dimensions, as expected from the scaling discussion in Section I1 (0 IEEE).
and no further decay of capacitance will occur. The nonequilibrium condition actually corresponds to the low-capacitance store 1 state. Thus, the capacitance in the store 1 state will gradually rise (with a time constant of 4.5 hr at room temperature). No such rise is perceptible on the short time scale of this figure.
VI. FUTURE DIRECTIONS A . Introduction
In the five previous sections we have described experimental work that has led to the present state of the art in GaAs one-transistor DRAM cells. Over the past years, storage times in GaAs capacitors have increased dramatically - from about 3 min at room temperature in 1987 to over lOhr in 1991, and the trend seems likely to continue. Moreover, the use of bipolar access transistors, as described in Section V, makes it possible to construct complete DRAM cells having storage times on the same order of magnitude as the capacitors alone. The charge storage density of p n junction capacitors in GaAs is comparable to that achieved in planar storage capacitors in silicon. What next? What directions should GaAs DRAM development take from this point? What applications can be identified that would lead to commercialization of these devices? We will address some of these questions in this final section.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
-
L
c m
65
Equilibrium Capacitance
I
---
m
Store 0
c)
0
8 0
Store 1
m
iL------1
0
200
400
600
800
1000
Time (sec)
FIGURE 55. Electrical writing of the bipolar DRAM cell. For this test, the charge state of the cell is monitored by observing the base capacitance. To write the cell, 3 V, 1msec write pulses are applied to the word line at the times indicated by arrows. The capacitance decay in the store 0 state is due to the turn-off transient of the forward-biased emitter-base junction, and it has no effect on operation. The store-0 state is in fact the equilibrium condition and will never decay. The low-capacitance store 1 state is the nonequilibrium condition. This capacitance will gradually increase with a time constant of 4.5 hr at room temperature. This increase is impercept1992 IEEE). ible on the time scale of this plot (0
B. Trench Capacitors and Stacked Capacitors in GaAs One of the dramatic developments in the evolution of silicon DRAMs was the introduction of vertical structures to increase the effective charge storage density (Sunami, 1985; Lu, 1989; Sunouchi et al., 1990). These vertical structures take the form of trench capacitors and stacked capacitors, as illustrated in Fig. 56. A large number of variations on these basic ideas have been proposed, but we will not attempt to review them here. The main point is that vertical structures have become absolutely necessary in silicon DRAMs at the integration levels prevalent today. On first glance it would appear that GaAs would be unable to emulate these vertical structures, and so would be totally unable to compete for high-density DRAM applications. However, that may not be the case at all. In this section, we will describe early efforts to develop a trench capacitor
66
JAMES A. COOPER, JR. Bit Line
Word
Line
Plate Voltage
SIO,
P Silicon
Trench Capacitor Cell
Bit Line
Word Line
P Silicon
Plate Voltage
P
Stacked Capacitor Cell
FIGURE56. Two types of vertical-geometry DRAM cells in silicon. The trench capacitor cell conserves area by placing the storage capacitor on the sidewalls of a vertical trench. The trench aspect ratio can be as high as 30: 1. The stacked capacitor cell utilizes a multilayer sandwich of insulating and conducting layers formed on top of the semiconductor surface.
technology in GaAs. We will also speculate on the use of stacked capacitors in conjunction with GaAs DRAM cells. Trench capacitors and complete trench DRAM cells can be grown in GaAs using a technique known as atomic layer epitaxy (ALE) (Bedair et al., 1985). ALE is a gas-phase epitaxial growth technique similar to metal-organic chemical vapor deposition (MOCVD) except that special precautions are taken to expose the growth surface to only one species of adatom at a time. Epitaxy is carried out in a temperature range where growth is self-limiting, so that a single monolayer of either Ga or As is formed during one cycle. The growth surface is alternately exposed to ambients containing Ga and As source gases, resulting in layer-by-layer growth. This leads to unprecedented control of the growing film on an atomic level. One very useful property of this growth technique is the ability to grow high-quality layers conformally on vertical sidewalls of etched trenches. This property is exploited to build trench DRAMS in GaAs. Figure 57 is a scanning electron micrograph of four 100 x 100pm’ mesaisolated GaAs p n diodes grown by ALE over a substrate in which several square 2pm deep trenches were etched prior to growth (Neudeck et al.,
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
67
FIGURE 57. SEM photograph of four 100 x 1oOpm2mesa-isolated pn diodes grown by ALE conformally over a substrate in which 2 pm deep trenches were etched prior to growth. Two of the mesas have a single 30 x 30pm2trench each, one mesa has nine 10 x 10pm2trenches. and one is planar (no trenches). The planar mesa is at the upper right. The light-colored square regon near the center of this device is the metal ohmic contact. An SEM cross section of one of the trenches is shown at the bottom.
68
JAMES A. COOPER, JR. Area = 100 x 100 pm
0
-0.5
-1
0.5
Voltage (V)
FIGURE58. Current-voltage characteristics at 1 4 4 O C for three ALE-grown pn diodes (symbols) with and without trenches. The nine-trench diode has 360pm of trench sidewall, while the one-trench diode has 120pm of trench sidewall. The line represents one of the best MBEgrown planar diodes.
1991b). Three types of diodes are shown: the diode on the upper right has no trenches (planar diode), the diodes on the upper left and the lower right each have one 30 x 30pm’ trench, and the diode on the lower left has nine 10 x 10pm2 trenches. The surface morphology is smooth, and conformal growth of epitaxial layers over the trench sidewalls is observed. Figure 58 shows the current-voltage characteristics of these three types of structures at 144OC. Also shown for comparison is one of the best planar diodes grown by MBE. Both forward and reverse currents are larger for the diodes containing trenches, but the reverse characteristics are not significantly degraded. Figure 59 shows the dependence of reverse current on trench perimeter for the three structures at a reverse voltage of 1V. Note that the one-trench and the nine-trench diodes each have the same trench area and same total diode area,
0
100
200
300
400
Trench Perimeter (pm)
FIGURE59. Leakage current at 144°C and 1 V reverse bias for the three ALE diodes of Fig. 5 8 . The reverse leakage increases linearly with trench perimeter.
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
69
but the trench perimeter differs by a factor of three. From this plot it is apparent that the reverse leakage scales with trench perimeter. It is not possible to determine from this measurement whether the leakage is due to the sidewalls themselves or to generation at the edges where the vertical sidewalls meet the horizontal top and bottom surfaces. This question can be resolved by a study of the dependence of leakage current on trench depth. Measurements of leakage current as a function of temperature indicate that the leakage is thermally activated. The planar diodes have an activation energy of 0.713 eV while both the trenched samples have an activation energy of 0.844 eV. These samples were metalized by electron-beam evaporation. Further work is needed to determine the dependence of leakage current on trench depth and sidewall orientation. In addition, both pnp storage capacitors and bipolar DRAM cells need to be built using this technique, and storage times need to be measured as a function of trench depth and orientation. Preliminary evidence based on the diode leakage measurements suggests that the degradation of storage time caused by the trenches would be within acceptable limits. The advantages of increased charge storage in the same amount of horizontal chip area would probably far outweigh the negative effects on storage time, particularly when storage times of planar devices are now measured in terms of hours at room temperature. Another approach to achieve higher charge storage densities with nonplanar capacitor structures is the use of stacked capacitors, similar to those illustrated in Fig. 56. In silicon DRAMS these stacked capacitors are formed by alternating layers of polysilicon conductors and SiO, insulators fabricated by a complex and ingenious sequence of deposition and selective etching. There is no fundamental reason why these steps cannot be performed on GaAs substrates. In effect, we are proposing that the storage capacitor need not be integral to the GaAs substrate, but could simply be deposited on the top surface after all the GaAs active devices are fabricated. This would open the possibility for a number of different structures, including metaloxide-metal capacitors, stacked capacitors such as shown in Fig. 56, and capacitors having a ferroelectric material as dielectric. C . Nondestructive Readout Cells
Another direction that shows great promise are GaAs DRAM cells that provide nondestructive readout with internal gain. Two types of structures are known to be under investigation (Cooper, 1989; Hetherington, Klein, and Weaver, 1991). One such structure, the bipolar/field-effect (BiFET) cell (Cooper, 1989), is shown in Fig. 60. Here the basic bipolar cell of Section V has been modified by the addition of a second base contact. This second contact allows the base layer to function as the channel of a lateral JFET,
70
JAMES A. COOPER, JR
-
Gate / Emitter Source / Base
P
I 30 nm undoped
r-
Y
N GaAs P+ GaAs N+ GaAs
Drain / Base
P
I l
FIGURE 60. A proposed bipolar-field-effect (BiFET) DRAM cell. The cell operates as a bipolar storage cell as described in Section V. Once a potential is stored on the floating collector, the depletion region of the collector-base junction modulates the lateral conductivity of the base layer. By establishing two ohmic contacts to the base, it is possible to detect the charge state of the floating collector by measuring the current between the two base contacts. In effect, the base forms a lateral JFET, gated from above by the emitter and from below by the floating collector.
gated from the top by the emitter and from the bottom by the floating collector. As a result, the current in the JFET is controlled by the potential of the floating collector, providing nondestructive readout. Because the cell now has gain, a robust signal can be placed on the bit lines during readout. Data is written to the cell in the conventional way using the bipolar access transistor (see Section V). The additional requirements on the base layer place new constraints on the design of the cell. In particular, the base layer thickness and doping must be adjusted to allow significant modulation by the floating collector. This must be accomplished without sacrificing the operation of the bipolar access transistor, both in the forward and inverse modes. Work is proceeding on these design issues, but no insurmountable problems are foreseen. The design problem is made more tractable by the several degrees of freedom inherent in the structure. Adjustable parameters include the base doping and thickness, the logic voltages on the floating collector, and the bias voltage on the emitter during readout. In addition, the use of heterojunctions at the emitter-base and collector-base junctions would improve bipolar operation, further relaxing the design constraints. In addition to providing nondestructive readout for digital (binary) memories, the BiFET cell can also be used as an analog memory. This mode of operation opens the possibility for several new applications, one of which is in the field of artificial neural networks. This will be discussed in Section
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
71
D. Ultra-Long Storage Times: Quasi-Static and Nonvolatile DRAMs As pointed out in the introduction to this section, storage times in GaAs memories have increased dramatically in recent years. In simple GaAs bipolar DRAM cells, storage times in excess of 4 hr at room temperature are now routinely obtained. For many applications such as cache memory, in which paging occurs at predictable intervals, storage times of this magnitude allow the cell to be operated essentially as a static memory, without the need for refreshing of any kind. Moreover, the bipolar DRAM has the unique feature that storage is accomplished with no external bias applied to the cell. This is because the bipolar access transistor is a current-controlled device and is off when the base current is 0. Thus, bipolar DRAMs can be used in applications where data is to be retained during temporary power losses, provided such interruptions are short compared to the normal storage time of the memory. In this mode, the memory is considered “nonvolatile,” at least for limited periods of time. What if the storage time could be extended to the order of days, months, or even years? In a moment, we will show experimental evidence that such storage times may indeed be possible. But first, we should point out the potential advantages that this type of nonvolatile memory would have in comparison to nonvolatile memories available today. In present-day nonvolatile memories in silicon, a charge is injected onto a floating gate by tunneling through a thin tunnel oxide or by avalanche injection over the potential barrier of a thicker oxide (Kahng and Sze, 1967; Frohman-Bentchkowsky, 1974; Nishi and Iizuka, 1981). Storage times are measured in years, but writing operation is quite slow, typically on the order of 100psec per bit, and writing requires pulse voltages much larger than the normal 5 V supply voltage. Therefore, operation is effectively restricted to read-only memory (ROM) applications, and the devices are variously referred to as programmable ROMs (PROMS), electrically alterable ROMs (EA-XOMs or E-PROMS), or “flash” E-PROMS. The bipolar DRAM, on the other hand, achieves nonvolatile storage from its inherently long charge recovery time and does not depend on tunneling or avalanche injection across an oxide barrier. As a result, electrical writing is expected to be very fast, typically on the order of nanoseconds or less per bit, and operation as a high-speed read-write memory is not compromised. Silicon E-PROMS also suffer from a wearout mechanism that limits the number of times the memory can be reprogrammed to around 106-107times. Although this is not a limitation when the memory is used as a ROM, it does preclude use of these devices in RAM applications, where lo6 writing operations can occur in a few seconds of real time. The bipolar DRAM suffers from no comparable wearout mechanism.
72
JAMES A. COOPER, JR
As stated earlier, storage times on the order of months to years may be possible using the basic bipolar DRAM structure of Section V, provided a suitable semiconductor material is utilized. One particularly attractive material for such applications is silicon carbide (Sic) (Davis et al., 1988). This is because S i c has a band-gap almost three times as large as silicon and twice as large as GaAs. S i c occurs in both cubic and hexagonal forms. Cubic (“beta”) S i c has a lattice constant of 4.359A and a band-gap of 2.3eV. Hexagonal (“alpha”) S i c occurs in a variety of polytypes, each having a hexagonal basal plane but with different stacking sequences in the vertical direction. The most useful polytype is “6H,” with a band-gap of 2.9 eV. Both beta and 6H material have been used to fabricate electronic devices (Kong et al., 1987; Palmour et al., 1991), including MESFETs, JFETs, MOSFETs, and bipolar transistors. 6H-Sic wafers are available commercially from Cree Research, Inc., Durham, NC, and are now grown at a number of research laboratories in the United States, Europe, Japan, and the states constituting the former Soviet Union. S i c is physically robust, being one of the hardest and most chemically inert materials known to humankind. It is thermally stable, and electronic devices retain good electrical characteristics to very high temperatures. MOSFET operation has been demonstrated (Palmour, Kong, and Davis, 1987) to 65OoC, and packaged devices operate reliably for extended periods at temperatures up to 35OoC, limited by the thermal stability of the package. Therefore, a major application for S i c is high-temperature and high-power electronic devices. For further information on S i c crystal growth, fabrication techniques, and electrical properties, the reader is referred to the literature. In order to evaluate S i c for use in long-term dynamic memory applications, we have investigated the storage time of npn storage capacitors in 6H-Sic (Gardner et al., 1991). A cross section of the experimental device is shown in Fig. 61. All layers are doped in situ during epitaxy. Circular npn diodes are isolated by reactive ion etching and passivated with S O z formed by wet thermal oxidation. Ohmic contacts are annealed Ni. Capacitance recovery times are measured on various devices using the techniques described in Section 11. Referring to equations (33) and (34) of Section 11, we are reminded that the recovery time of a pn junction storage capacitor is expected to increase exponentially with band-gap energy as exp (EG/2kT), assuming that generation lifetimes in the materials are comparable. Since the band-gap energy of 6H-Sic is 1.48eV greater than the band-gap of GaAs, one expects the storage time at room temperature to be larger by a factor of exp(28.6) or approximately 12 orders of magnitude. Alternatively, we expect to observe the same storage time as GaAs at an absolute temperature that is higher by the ratio of the band-gaps, or approximately a factor of 2. This means that S i c devices should exhibit
RECENT ADVANCES IN GaAs DYNAMIC MEMORIES
73
Ni Ohmic Contact
30 nm undoped
-
N 6H Sic Substrate (Siface)
FIGURE 61. Prototype n-i-p-i-nstorage capacitor fabricated in 6H-Sic for storage time measurements. The etched surfaces are passivated by thermal SiO, grown by wet oxidation.
storage times at 600 K (3OOOC) that are comparable to those of GaAs at room temperature. Figure 62 shows storage time versus temperature for several Sic diodes (Cooper et al., 1991). As predicted, storage times on the order of 10 min are observed at 300°C. All diodes have an activation energy around 1.48 eV, close to half the band-gap. If we extrapolate these data to room temperature, we would predict a storage time of about loi3sec, or about 300,000 years! Of course, such an extrapolation is not realistic - other mechanisms having lower activation
los
b
'
.
,
lo4
I
I
I
I
,
6H-!SIC
,
,
,
,
1
,
.
,
,
I
"
' 3
/-
I
10'
loo
; '
'
'
FIGURE62. Recovery time versus temperature for storage capacitors fabricated in GaAs and in 6H-Sic. The activation energy of the Sic capacitors is about 1.48 eV, close to half the band-gap. Data on the S ic samples had to be taken above 300°C because at lower temperatures the storage times are too long to be conveniently measured.
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JAMES A. COOPER, JR.
energies (or not thermally activated at all) will become dominant before room temperature is reached. The point, however, is that thermal generation is not likely to limit storage times in these devices. How long will room temperature storage times be? That question is difficult to answer with any confidence, since it will require actual room temperature measurements over extended periods of time. Such measurements have not yet been attempted. To summarize, we have shown the possibility of one-transistor memories having exceedingly long storage times at room temperature. For practical purposes, such memories can be regarded as static. In addition, since the bipolar cell requires no external bias to retain data, these memories are also nonvolatile. Because they can be written in nanoseconds, these devices can be used in high-speed RAM applications. E. Nonconventional Applications
TOconclude this chapter, we wish to suggest some nonconventional applications for these compact storage devices. Dynamic memory is usually associated with digital electronics. However, the applications we will describe in this section use the fact that the dynamic memory is inherently an analog device. The basic elements of the dynamic memory cell, storage capacitors and access transistors, are utilized in a number of analog applications such as switched capacitor filters. In addition, the basic capacitor structure, which has been optimized for exceedingly low dark current, is ideal for use in low-light-level imagers. Perhaps the most novel application, one that has arisen only in the last few years, is in the emerging field of electronic neural networks. We will describe this particular application next. Artificial neural networks are electronic circuits that embody many of the features of biological neural systems (Hopfield, 1988; Lippmann, 1987). In particular, they are highly interconnected networks composed of a large number of very simple identical elements. The basic elements of neural networks are neurons and synapses. In electronic neural networks, neurons are simple amplifiers having saturating (or sigmoidlike) input-output characteristics. The input to each neuron is a summing node connected to a large number of surrounding neurons by resistive connections called synapses. An example of a simple electronic neural network is shown in Fig. 63. Here the network consists of a row of amplifiers (neurons) whose outputs are brought around to a matrix of resistive connections (synapses). The synapse matrix forms the interconnections between neurons. One simple way to visualize the operation of a neural network is to define an energy function for the network. This energy function depends on the output voltages of the neurons in the array. If there are n neurons, the energy function is defined on an n-dimensional space. The exact dependence of the
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FIGURE63. Illustration of a simple Hopfield neural network. The network consists of a row of amplifiers (neurons) whose outputs are brought around to a matrix of resistive connections (synapses). The synapse matrix forms the interconnections between neurons. Programming is accomplished by specifying the strengths of the resistive connections in the synapse matrix.
network energy on the individual neuron voltages is determined by the resistive weights of the synapse elements in the interconnection matrix. Thus, the information content of the network, in effect its programming, is contained in the resistive weights of the synapse connections. One use of such a neural network is in pattern recognition. Suppose that an input pattern (which could be an optical image, a fragment of speech, a radar signature, etc.) is to be classified based on a number of predetermined “example” patterns, To be specific, let us assume that the network is to identify a two-dimensional image as belonging to one of 26 possible classes: the letters of the alphabet. The weights in the synapse matrix of the neural network are selected so that the energy function of the network exhibits local minima. Each local minimum corresponds to one of the “example” patterns that are acceptable answers to the identification problem. The inputs to the neurons are then preset to potentials that correspond to the input image to be identified. This, in effect, places the network in an initial condition at some point in the n-dimensional parameter space corresponding to the input pattern. The network is then allowed to settle into the local energy minimum that is “nearest” the starting point. This minimum corresponds to one of the 26 possible “answers” - the 26 letters of the alphabet. In this way, the network performs a natural minimization function, determining which “example” pattern is the minimum distance from the input pattern.
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The question of how to specify the weights in the synapse matrix so that the local minima in the energy function are efficiently placed is a subject of current research. However, for our purposes it suffices to understand that the network is “programmed” by specifying these synapse weights. To perform a meaningful pattern recognition task, the electronic neural network must be of sufficient size. In particular, the number of local minima in the energy function grows approximately as the square root of the number of neurons. Unfortunately, the number of synapse connections grows as the square of the number of neurons. It is easy to see that simply identifying the letters of the alphabet would require perhaps a few thousand neurons and a few million synapses. How does all this relate to dynamic memories? In Section C , we described a combination bipolar-field-effect (BiFET) cell capable of nondestructive readout of stored information. We now suggest that this BiFET cell can be used to implement a very compact synapse connection for electronic neural networks. As discussed earlier, the potential on the floating collector in this device serves to back-gate the channel of the lateral JFET formed by the base layer. Thus, the conductance of this lateral JFET can be programmed to an analog value by storing the proper voltage on the floating collector. The JFET is then used to provide the desired resistive connection required of the synapse element. An illustration of the use of the BiFET cell in a synapse array is shown in Fig. 64. We assume that the weighting information is stored off-line in a conventional semiconductor memory. This weighting information is then loaded into the BiFET array using the data lines shown. Once initialized, the BiFET array is ready to provide weighted synapse connections for the neural network. Since it is important that the analog voltage in each cell does not change appreciably, the array will need to be refreshed in a time that is much shorter than the l/e storage times previously quoted for our DRAM cells. However, considering the long room-temperature storage times of GaAs bipolar cells (not to mention the storage times of S ic cells), such periodic refreshing should not be a significant problem, particularly since the normal settling time of the neural network is on the order of a few microseconds. The use of dynamic storage for the synapse weights allows the network to be reprogrammed on-the-fly to solve different classification problems, in effect becoming a general-purpose neural computer. In conclusion, we have pointed out a number of nonconventional applications for dynamic storage devices. The ultra-long storage times now being realized make possible a number of novel applications, as diverse as nonvolatile digital memory and high-density neural networks. The evolution of nonsilicon dynamic memory devices has been rapid, and a number of exciting directions are opening for future development.
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FIGURE 64. Realization of a Hopfield network using the BiFET storage cell of Fig. 60 as a programmable analog synapse element. Synapse weights are entered using the horizontal “data” lines.
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