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Recent advances in wafer bonding of silicon and alternative materials
ELSEVIER
Microelectronic Engineering 48 (1999) 313-318
I III
www.elsevier.nl/locate/mee
Recent Advances in Wafer Bonding of Silicon and Alternative Materials Dr. Scott Blackstone BCO Technologies, 5 Hannahstown Hill, Belfast, UK [email protected]
Wafer bonding technology is rapidly gaining acceptance as the technology of choice for an ever widening range of applications. In this paper I review the fundamental bonding mechanisms along with new applications. These include, pattern buried layers, high thermal conductivity buried insulators such as diamond, hetero-bonding of silicides and compound semiconductors.
1. Introduction Wafer bonding is rapidly becoming an accepted technology for the manufacture of silicon based products. Already a large number of thick film SO1 products, which incorporate wafer bonding, are commercially available (3,4,5,11,12). Many predict that in the future, thin film SOI/CMOS will also become a significant technology. Wafer bonding has migrated to include silicon compatible materials, such as glass, quartz, diamond, alumina and sapphire. It has also been extended to non-silicon materials such as GaAs, InP and SiC among others.
atomically fiat surfaces are brought into intimate contact. At some points, the space between the two surfaces will be sufficiently small to achieve VanDerWaal bonding. This point bonding will pull the two surfaces together allowing the surrounding areas to also VanDerWaal bond, creating a zipper like effect. This propagates a joining wave, which sweeps across the surface leaving the two surfaces tightly coupled. This is shown in SAM (scanning acoustic microscope) images of Fig 1. The image on the top left is only joined in the bottom, in the top right image, the joining wave has moved half way across the wafer and in bottom image on the right the joining wave is complete.
Wafer bonding technology, as understood in its present form, was In'st proposed by RCA Laboratories in a series of patents filed in the 1960's. However, 1960's standards of surface roughness and particles prevented commercial production of bonded wafers. This technology was re-evaluated in the 1980's, principally in Japan, with successful results. Commercial production of bonded wafer pressure sensors began in the mid 80's and bonded wafer electronic devices in the late 80's (12).
2. Bonding Mechanisms 2.1
Joining
Wafer bonding works by a two step process, joining and bonding. In the joining operation, two
Fig 1 Progression of Joining Wave Across Wafer This wave releases a great deal of energy, which is sufficient to "snowplow" particles, adsorbed gases
0167-9317/99/$ - see front matter © 1999 Elsevier Science B.V. All rights reserved.
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S. Blackstone / Microelectronic Engineering 48 (1999) 313-318
and other foreign material offthe wafer edge. An example of the strength of this wave can be seen in the joining of thin wafers, about half normal thickness. In this case the wave can be clearly seen on the back of the thin wafer as a distortion moving across the surface. This joining wave is the reason why wafer bonding works. Completely particle free surfaces are beyond current technology and if no particles were allowed for good bonding, then it could not be achieved. The joining wave is sufficiently strong such that it can push off relatively large numbers of particles, 100's, and relatively large particles, approx. 0.5um. These are well within current cleaning technology. If there are large particles on the surface, or an accumulation of smaller particles, the joining wave will stop and sweep around the particle, hermetically sealing it into the joined interface. This is known as a void. While voids do not exist on commercially produced bonded wafers, it is interesting to understand them for reliability purposes. Silicon is very stiff material and will not conform to the particle entrapped at the interface, but will "tentover" the particle creating a void, which is three or four orders of magnitude greater than the particle size. In other words, a l u m particle creates a void, which is about 1mm in diameter.
2.2
Bonding
wafer, as joined, will remain voidless during and after bond.
2.2.2
HydrophilicBonding
If the surfaces are hydrophilic, the wafers will join with a strong joining wave. However, because the surfaces are not water permeable, the water molecules at the interface must diffuse across the interface and exit at the edge of the wafer. Even if the wafer is voidless as joined, at about 400C, a dense array of"voids" form across the wafer. These voids are two dimensional water droplets which have agglomerated and which then migrate across the wafer exiting from the edge. These voids clear first in the middle and then the voidfree area spreads toward the edge of the wafer. The temperature at which the wafers become void free is a strong function of wafer surface roughness. After the wafer expels the interfacial water and again become voidless, the interface is composed of a thin oxide, which was the native oxide on the wafers prior to joining. At higher temperatures, this oxide also agglomerates, forming into islands of oxide. Outside these islands, the two silicon layers are directly bonded together. An example of this is shown in the following photoluminescense plan view image of the bonded interface (fig 2) courtesy ofBioRad, UK.
After the two surfaces are joined, they are heated to allow covalent bonding of the two surface materials resulting in a permanent, void free interface. As the two surfaces are heated and chemically bond, the water molecules, which were holding the two surfaces together, coalesce into water droplets and migrate away from the interface. There are basically three types of bonding within the silicon system. These are oxide bonding, in which one or both surfaces have a thermally grown oxide, hydrophilic, in which both wafers have bare hydrophilic surfaces and hydrophobic in which both wafers have bare hydrophobic surfaces.
2.2.1
OxideBonding
If one of the surfaces is an oxide, the water molecules diffuse into the oxide allowing the silicon and oxide surfaces to bond. In this case, a voidless
Fig 2 Photoluminescense Plan View of Hydrophilically Bonded Wafer.
S. Blackstone I M icroelectronic Engineering 48 (1999) 313-.318
315
In this image the thick oxide islands are shown as white in a dark background. After a sufficient anneal the entire interface becomes oxide free. 2.2.3
Hydrophobic Bonding
If the surfaces are hydrophobic, the wave, if it exists, will be weaker. The existence of a joining wave, in the absence of water vapor at the surface, is a matter of debate. Like the hydrophilic case, heating the wafer results in water agglomeration and "voids". These voids clear at a lower temperature than the hydrophilic case and higher temperature does not improve the bond as in the case of the hydrophilic case. This is probably because of the lack of a native oxide. 3.
Pre-Processed Wafers
There are a number of applications in which it is desired to process the device wafer prior to bondin~ The simplest example of this is to implant the wafer and thus create a buried layer. However this can also include deposited films, cavities and other processing. The bonding of doped layers requires special care as many standard cleaning solutions interact with the diffused layer resulting in voids. This is function of specie and dose. Patterned buried layers present additional challenges of surface topology. The implantation doping step results in a volume expansion and surface step. With careful attention to the surface, it is possible to routinely achieve successful bonding on even extensively pre-processed wafers. Fig 3 is a plan view SEM of a pre-processed wafer which has been polished back almost to the buried oxide showing a void free bond. This wafer had a deep N- and P- diffusion, followed by a deep N+ and P+ diffusion followed by a shallow N+ and P+ implant. This wafer was processed through 7 photo steps, and two high temperature diffusions. In the photo, the dark lines are from a trench, the clear
Fig 3 Preprocessed Wafer Thinned to Sub-Micron Thickness Showing Voidless Bonding and Doping Profiles. areas are the N areas, the light gray areas are the shallow P+ and the dark areas are the deep P+ areas. The polishing process decorates these P-type areas. 4. Buried Thin Film Materials There are a number of potential improvements on the SO1 structure. These include higher conductivity, both electrical and thermal, as well as improved optical properties. 4.1 Buried Silieides Forming a silicide layer between the top silicon layer and the buried oxide can have a number of interesting applications(I-7). This layer can provide a low electrical resistance path for vertical current flow, high optical reflectivity and a "channel" for doping. A TEM cross-section of a bonded Silicon-SilicideSOI ($2OI), courtesy ofDERA, Malvern, UK is shown in Fig 4.
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S. Blackstone / Microelectronic Engineering 48 (1999) 313-318
problem, a layer of polysilicon is deposited on to the diamond and then polished producing a bondable interface.
Fig 5 Cross Sectional SEM of a SOD, Silicon On Diamond Bonded Wafer. This technique is demonstrated in fig 5, courtesy of Chamlers University, Sweden. The rough diamond surface is smoothed by the polysilicon, which is then polished and bonded to the handle wafer.
Fig 4 Cross-Sectional TEM of Bonded SiliconSilicide SOI Structure. The silicide in this case is tungsten silicide, WSi. WSi silicide was chosen because it is refractory, stable and can be deposited from commercially available CVD equipment. The silicide was first deposited onto the device wafer and then the silicide layer was wafer bonded to the oxidized handle wafer. 4.2
Improved Dielectric
One of the limitations of the SO1 structure is the very limited thermal conductivity of the buried thermal silicon dioxide layer. Altemative materials such as diamond, sapphire (A1203) and aluminum nitride (A1N) have been investigated. Diamond offers a 1000 times improvement over silicon dioxide in terms of thermal conductivity. AIN is 100 and sapphire is 20 times better. Diamond appears to offer the most promising alternative to silicon dioxide and CVD techniques for depositing diamond are now becoming available. However, the surfaces are very rough, in the order of 10nm, and thus will not bond. To overcome this
Complete MOS circuits have been fabricated on this SOD (Silicon On Diamond) with excellent results. The higher thermal conductivity of the SOD device was clearly demonstrated in the device characteristics. 5.
Non-Silicon Semiconductors
In addition to the bonding of non-silicon based materials such as tungsten silicide and diamond, other semiconductor are also bondable. These are most notably the III-V and II-VI materials such as GaAs, InP and their compounds. Currently an area of great interest is not in bonding compound semiconductors to each other but to silicon. This allows the unique features of the compound semiconductors to be combined with the economy and scale of silicon technology.
Fig 6 Schematic of PIN Detector.
S. Blackstone I Microelectronic Engineering 48 (1999) 313-318
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the buried oxide as an etch stop. In order to accomplish this, the front side of the wafer must first be glued onto a suitable substrate. An example of an SOl circuit which was glued onto a glass substrate and then had the handle wafer removed is shown in Fig 8. This photo, courtesy of IMEC, Belgium, shows the circuit sitting on a printed page. This technique shows great promise for optical devices, microwave devices and high density packaging. 7. Fig 7 Cross Sectional TEM of PIN Detector Bonded Interface A simple example of this is the PIN detector shown in Fig 6, courtesy of Ciena Corp. The bonding interface is between the InGaAs layer and the silicon substrate. As seen in the crosssectional TEM, Fig 7, this is a voidless bond without an interfacial layer.
6.
MST/MEMS
No discussion of bonded wafer thick film SOI would be complete with a discussion of micromachining. Single crystal silicon is an excellent mechanical material and the buried oxide provides controlled undercutting of beams, etc. Bonded wafer MST devices are used in applications ranging from high performance gyroscopes for space applications to airbag sensors in automotive products.
Epoxy Bonding
While room temperature gluing of wafers is not considered a form of bonding, I mention it because wafer bonding has resulted in an interest in "layer transfer" which is assisted by epoxy bonding. It has only been recently possible to form a thin, voidless, continuous adhesive layer between the finished SO1 wafer and a substrate such as glass. Fig 9 Self Assembled 3-D Device An advanced version of MST design is shown in Fig 9, courtesy of Imperial College London, UK. In this structure, 2-D plates are formed in the thick film bonded SO1 and then lifted vertically using specially designed hinges. It is projected that complete micro-machines will be constructed using these techniques.
8. Conclusion Fig 8 SOI Layer Transferred Onto Glass Wafer and Laid on Newsprint. After a circuit is build on an SOI wafer, it may be desirable to "detach" it from the handle wafer, using
In conclusion, wafer bonding technology has been applied to an ever widening variety of applications and materials that go far beyond the original ideas of the inventors. It is rapidly becoming just one more
318
S. Blackstone / Microelectronic Engineering 48 (1999) 313-318
process in the "tool box", similar to oxidation, diffusion and implantation. This widespread acceptance of the technology will mean that it will continue to grow and evolve. References
1. R. Wilson, C. Quinn, B. McDonnell, S. Blackstone and K. Yallup, "Bonded and Trenched SOI with Buried Silicide Layers" in Electrochem. Soc Proc. Vol 95-7, p535 2. K. Yallup, R. Wilson, C. Quinn, B. McDonnell and S. Blackstone, "Buried WSi SOI Structure", 1995 IEEE Int'l SOI Conf. P 137 3. V. Nayar et al, "Bonded Silicon Silicide on Insulator (S2OI): A Study of Chemical, Physical and Optical Properties for Advanced Device Fabrication", In 4 th Semiconductor Bonding Symp. 192 Electrochem, Soc Conf, Paris, Sept 97 4. S. Lizotte, W. Cantarini, C. Quinn, A. Nevin and S. Blackstone "Silicided Buried Layer Smart Power Process" 4 th Semiconductor Bonding Symposium, 192 Electrochem, Soc Conf. Paris Sept 97 5. S.B. Goody, P.H. Saul, "A fully Oxide Isolated Bipolar Transistor Integrated Circuit Process", Electrochem Soc Vol 95-1, May 95 6. W.L. Goh, J.H. Montgomery, S.H. Raza, B.M. Armstrong and H.S. Gamble "Electrical Characterization of Dielectrically Isolated Silicon Substrates Containing Buried Metallic Layers", IEEE Electron Devices 7. W.L. Goh, D.L. Campbell, B.M. Armstrong and H.S. Gamble, "Buried Metallic Layers with Silicon Direct Bonding", Electrochem Soc 957,'95 8. K. Hermansson and S. Blackstone "Bonded Wafers for Use in MEMS Manufacturing", Micro Structure Workshop '98 9. M. DeCourcy, J.C Alderman, S. Blackstone, H. Gamble, "A Comparison of Bipolar Devices on Bonded and Trenched Wafers with Junction and Trench Isolated Bulk Wafers", Electrochem Soc 3 ra Semiconductor Bonding Symposium '95 10. S. Blackstone "Mechanical Thinning for SOI" 3rd Semiconductor Bonding Symposium '95 11. K. McStay, F. Smoot, D. Hariton, K Egan, D. Irvine, G. Brown. P. Edwards, S. Blackstone and H. Gamble, "A Commodity Analog Process Based on Bonded Wafers", Electrochem Soc 3 rd Semiconductor Bonding Symposium.
12. Electronic Design, July 13, 1989 "Direct Wafer Bonding Builds Rugged Rectifiers"
Microelectronic Engineering 48 (1999) 313-318
I III
www.elsevier.nl/locate/mee
Recent Advances in Wafer Bonding of Silicon and Alternative Materials Dr. Scott Blackstone BCO Technologies, 5 Hannahstown Hill, Belfast, UK [email protected]
Wafer bonding technology is rapidly gaining acceptance as the technology of choice for an ever widening range of applications. In this paper I review the fundamental bonding mechanisms along with new applications. These include, pattern buried layers, high thermal conductivity buried insulators such as diamond, hetero-bonding of silicides and compound semiconductors.
1. Introduction Wafer bonding is rapidly becoming an accepted technology for the manufacture of silicon based products. Already a large number of thick film SO1 products, which incorporate wafer bonding, are commercially available (3,4,5,11,12). Many predict that in the future, thin film SOI/CMOS will also become a significant technology. Wafer bonding has migrated to include silicon compatible materials, such as glass, quartz, diamond, alumina and sapphire. It has also been extended to non-silicon materials such as GaAs, InP and SiC among others.
atomically fiat surfaces are brought into intimate contact. At some points, the space between the two surfaces will be sufficiently small to achieve VanDerWaal bonding. This point bonding will pull the two surfaces together allowing the surrounding areas to also VanDerWaal bond, creating a zipper like effect. This propagates a joining wave, which sweeps across the surface leaving the two surfaces tightly coupled. This is shown in SAM (scanning acoustic microscope) images of Fig 1. The image on the top left is only joined in the bottom, in the top right image, the joining wave has moved half way across the wafer and in bottom image on the right the joining wave is complete.
Wafer bonding technology, as understood in its present form, was In'st proposed by RCA Laboratories in a series of patents filed in the 1960's. However, 1960's standards of surface roughness and particles prevented commercial production of bonded wafers. This technology was re-evaluated in the 1980's, principally in Japan, with successful results. Commercial production of bonded wafer pressure sensors began in the mid 80's and bonded wafer electronic devices in the late 80's (12).
2. Bonding Mechanisms 2.1
Joining
Wafer bonding works by a two step process, joining and bonding. In the joining operation, two
Fig 1 Progression of Joining Wave Across Wafer This wave releases a great deal of energy, which is sufficient to "snowplow" particles, adsorbed gases
0167-9317/99/$ - see front matter © 1999 Elsevier Science B.V. All rights reserved.
314
S. Blackstone / Microelectronic Engineering 48 (1999) 313-318
and other foreign material offthe wafer edge. An example of the strength of this wave can be seen in the joining of thin wafers, about half normal thickness. In this case the wave can be clearly seen on the back of the thin wafer as a distortion moving across the surface. This joining wave is the reason why wafer bonding works. Completely particle free surfaces are beyond current technology and if no particles were allowed for good bonding, then it could not be achieved. The joining wave is sufficiently strong such that it can push off relatively large numbers of particles, 100's, and relatively large particles, approx. 0.5um. These are well within current cleaning technology. If there are large particles on the surface, or an accumulation of smaller particles, the joining wave will stop and sweep around the particle, hermetically sealing it into the joined interface. This is known as a void. While voids do not exist on commercially produced bonded wafers, it is interesting to understand them for reliability purposes. Silicon is very stiff material and will not conform to the particle entrapped at the interface, but will "tentover" the particle creating a void, which is three or four orders of magnitude greater than the particle size. In other words, a l u m particle creates a void, which is about 1mm in diameter.
2.2
Bonding
wafer, as joined, will remain voidless during and after bond.
2.2.2
HydrophilicBonding
If the surfaces are hydrophilic, the wafers will join with a strong joining wave. However, because the surfaces are not water permeable, the water molecules at the interface must diffuse across the interface and exit at the edge of the wafer. Even if the wafer is voidless as joined, at about 400C, a dense array of"voids" form across the wafer. These voids are two dimensional water droplets which have agglomerated and which then migrate across the wafer exiting from the edge. These voids clear first in the middle and then the voidfree area spreads toward the edge of the wafer. The temperature at which the wafers become void free is a strong function of wafer surface roughness. After the wafer expels the interfacial water and again become voidless, the interface is composed of a thin oxide, which was the native oxide on the wafers prior to joining. At higher temperatures, this oxide also agglomerates, forming into islands of oxide. Outside these islands, the two silicon layers are directly bonded together. An example of this is shown in the following photoluminescense plan view image of the bonded interface (fig 2) courtesy ofBioRad, UK.
After the two surfaces are joined, they are heated to allow covalent bonding of the two surface materials resulting in a permanent, void free interface. As the two surfaces are heated and chemically bond, the water molecules, which were holding the two surfaces together, coalesce into water droplets and migrate away from the interface. There are basically three types of bonding within the silicon system. These are oxide bonding, in which one or both surfaces have a thermally grown oxide, hydrophilic, in which both wafers have bare hydrophilic surfaces and hydrophobic in which both wafers have bare hydrophobic surfaces.
2.2.1
OxideBonding
If one of the surfaces is an oxide, the water molecules diffuse into the oxide allowing the silicon and oxide surfaces to bond. In this case, a voidless
Fig 2 Photoluminescense Plan View of Hydrophilically Bonded Wafer.
S. Blackstone I M icroelectronic Engineering 48 (1999) 313-.318
315
In this image the thick oxide islands are shown as white in a dark background. After a sufficient anneal the entire interface becomes oxide free. 2.2.3
Hydrophobic Bonding
If the surfaces are hydrophobic, the wave, if it exists, will be weaker. The existence of a joining wave, in the absence of water vapor at the surface, is a matter of debate. Like the hydrophilic case, heating the wafer results in water agglomeration and "voids". These voids clear at a lower temperature than the hydrophilic case and higher temperature does not improve the bond as in the case of the hydrophilic case. This is probably because of the lack of a native oxide. 3.
Pre-Processed Wafers
There are a number of applications in which it is desired to process the device wafer prior to bondin~ The simplest example of this is to implant the wafer and thus create a buried layer. However this can also include deposited films, cavities and other processing. The bonding of doped layers requires special care as many standard cleaning solutions interact with the diffused layer resulting in voids. This is function of specie and dose. Patterned buried layers present additional challenges of surface topology. The implantation doping step results in a volume expansion and surface step. With careful attention to the surface, it is possible to routinely achieve successful bonding on even extensively pre-processed wafers. Fig 3 is a plan view SEM of a pre-processed wafer which has been polished back almost to the buried oxide showing a void free bond. This wafer had a deep N- and P- diffusion, followed by a deep N+ and P+ diffusion followed by a shallow N+ and P+ implant. This wafer was processed through 7 photo steps, and two high temperature diffusions. In the photo, the dark lines are from a trench, the clear
Fig 3 Preprocessed Wafer Thinned to Sub-Micron Thickness Showing Voidless Bonding and Doping Profiles. areas are the N areas, the light gray areas are the shallow P+ and the dark areas are the deep P+ areas. The polishing process decorates these P-type areas. 4. Buried Thin Film Materials There are a number of potential improvements on the SO1 structure. These include higher conductivity, both electrical and thermal, as well as improved optical properties. 4.1 Buried Silieides Forming a silicide layer between the top silicon layer and the buried oxide can have a number of interesting applications(I-7). This layer can provide a low electrical resistance path for vertical current flow, high optical reflectivity and a "channel" for doping. A TEM cross-section of a bonded Silicon-SilicideSOI ($2OI), courtesy ofDERA, Malvern, UK is shown in Fig 4.
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S. Blackstone / Microelectronic Engineering 48 (1999) 313-318
problem, a layer of polysilicon is deposited on to the diamond and then polished producing a bondable interface.
Fig 5 Cross Sectional SEM of a SOD, Silicon On Diamond Bonded Wafer. This technique is demonstrated in fig 5, courtesy of Chamlers University, Sweden. The rough diamond surface is smoothed by the polysilicon, which is then polished and bonded to the handle wafer.
Fig 4 Cross-Sectional TEM of Bonded SiliconSilicide SOI Structure. The silicide in this case is tungsten silicide, WSi. WSi silicide was chosen because it is refractory, stable and can be deposited from commercially available CVD equipment. The silicide was first deposited onto the device wafer and then the silicide layer was wafer bonded to the oxidized handle wafer. 4.2
Improved Dielectric
One of the limitations of the SO1 structure is the very limited thermal conductivity of the buried thermal silicon dioxide layer. Altemative materials such as diamond, sapphire (A1203) and aluminum nitride (A1N) have been investigated. Diamond offers a 1000 times improvement over silicon dioxide in terms of thermal conductivity. AIN is 100 and sapphire is 20 times better. Diamond appears to offer the most promising alternative to silicon dioxide and CVD techniques for depositing diamond are now becoming available. However, the surfaces are very rough, in the order of 10nm, and thus will not bond. To overcome this
Complete MOS circuits have been fabricated on this SOD (Silicon On Diamond) with excellent results. The higher thermal conductivity of the SOD device was clearly demonstrated in the device characteristics. 5.
Non-Silicon Semiconductors
In addition to the bonding of non-silicon based materials such as tungsten silicide and diamond, other semiconductor are also bondable. These are most notably the III-V and II-VI materials such as GaAs, InP and their compounds. Currently an area of great interest is not in bonding compound semiconductors to each other but to silicon. This allows the unique features of the compound semiconductors to be combined with the economy and scale of silicon technology.
Fig 6 Schematic of PIN Detector.
S. Blackstone I Microelectronic Engineering 48 (1999) 313-318
317
the buried oxide as an etch stop. In order to accomplish this, the front side of the wafer must first be glued onto a suitable substrate. An example of an SOl circuit which was glued onto a glass substrate and then had the handle wafer removed is shown in Fig 8. This photo, courtesy of IMEC, Belgium, shows the circuit sitting on a printed page. This technique shows great promise for optical devices, microwave devices and high density packaging. 7. Fig 7 Cross Sectional TEM of PIN Detector Bonded Interface A simple example of this is the PIN detector shown in Fig 6, courtesy of Ciena Corp. The bonding interface is between the InGaAs layer and the silicon substrate. As seen in the crosssectional TEM, Fig 7, this is a voidless bond without an interfacial layer.
6.
MST/MEMS
No discussion of bonded wafer thick film SOI would be complete with a discussion of micromachining. Single crystal silicon is an excellent mechanical material and the buried oxide provides controlled undercutting of beams, etc. Bonded wafer MST devices are used in applications ranging from high performance gyroscopes for space applications to airbag sensors in automotive products.
Epoxy Bonding
While room temperature gluing of wafers is not considered a form of bonding, I mention it because wafer bonding has resulted in an interest in "layer transfer" which is assisted by epoxy bonding. It has only been recently possible to form a thin, voidless, continuous adhesive layer between the finished SO1 wafer and a substrate such as glass. Fig 9 Self Assembled 3-D Device An advanced version of MST design is shown in Fig 9, courtesy of Imperial College London, UK. In this structure, 2-D plates are formed in the thick film bonded SO1 and then lifted vertically using specially designed hinges. It is projected that complete micro-machines will be constructed using these techniques.
8. Conclusion Fig 8 SOI Layer Transferred Onto Glass Wafer and Laid on Newsprint. After a circuit is build on an SOI wafer, it may be desirable to "detach" it from the handle wafer, using
In conclusion, wafer bonding technology has been applied to an ever widening variety of applications and materials that go far beyond the original ideas of the inventors. It is rapidly becoming just one more
318
S. Blackstone / Microelectronic Engineering 48 (1999) 313-318
process in the "tool box", similar to oxidation, diffusion and implantation. This widespread acceptance of the technology will mean that it will continue to grow and evolve. References
1. R. Wilson, C. Quinn, B. McDonnell, S. Blackstone and K. Yallup, "Bonded and Trenched SOI with Buried Silicide Layers" in Electrochem. Soc Proc. Vol 95-7, p535 2. K. Yallup, R. Wilson, C. Quinn, B. McDonnell and S. Blackstone, "Buried WSi SOI Structure", 1995 IEEE Int'l SOI Conf. P 137 3. V. Nayar et al, "Bonded Silicon Silicide on Insulator (S2OI): A Study of Chemical, Physical and Optical Properties for Advanced Device Fabrication", In 4 th Semiconductor Bonding Symp. 192 Electrochem, Soc Conf, Paris, Sept 97 4. S. Lizotte, W. Cantarini, C. Quinn, A. Nevin and S. Blackstone "Silicided Buried Layer Smart Power Process" 4 th Semiconductor Bonding Symposium, 192 Electrochem, Soc Conf. Paris Sept 97 5. S.B. Goody, P.H. Saul, "A fully Oxide Isolated Bipolar Transistor Integrated Circuit Process", Electrochem Soc Vol 95-1, May 95 6. W.L. Goh, J.H. Montgomery, S.H. Raza, B.M. Armstrong and H.S. Gamble "Electrical Characterization of Dielectrically Isolated Silicon Substrates Containing Buried Metallic Layers", IEEE Electron Devices 7. W.L. Goh, D.L. Campbell, B.M. Armstrong and H.S. Gamble, "Buried Metallic Layers with Silicon Direct Bonding", Electrochem Soc 957,'95 8. K. Hermansson and S. Blackstone "Bonded Wafers for Use in MEMS Manufacturing", Micro Structure Workshop '98 9. M. DeCourcy, J.C Alderman, S. Blackstone, H. Gamble, "A Comparison of Bipolar Devices on Bonded and Trenched Wafers with Junction and Trench Isolated Bulk Wafers", Electrochem Soc 3 ra Semiconductor Bonding Symposium '95 10. S. Blackstone "Mechanical Thinning for SOI" 3rd Semiconductor Bonding Symposium '95 11. K. McStay, F. Smoot, D. Hariton, K Egan, D. Irvine, G. Brown. P. Edwards, S. Blackstone and H. Gamble, "A Commodity Analog Process Based on Bonded Wafers", Electrochem Soc 3 rd Semiconductor Bonding Symposium.
12. Electronic Design, July 13, 1989 "Direct Wafer Bonding Builds Rugged Rectifiers"