Reconfiguration of hexagonal arrays by diagonal deletion

263

Reconfiguration of hexagonal arrays by diagonal deletion * Fabrizio Lombardi Department of Electrical and Computer Engineering, Unioersity of Colorado, Boulder, CO 80309, U.S.A.

Received 27 November 1986 Abstract. This paper describes various algorithms for dynamic reconfiguration of VLSI hexagonal arrays. These algorithms are applicable to arrays in which reconfiguration requires logical deletion of the diagonal front of computation. Initially it is proven that the intuitive, but rather naive approach of diagonal deletion is not correct, because it does guarantee the generation of the correct dimensions in the target array. A new approach based on geometrical considerations is proposed. Theorems that preserve the dimensions of the desired target array, are presented. Two reconfiguration algorithms are presented. These algorithms have linear time-complexity with respect to the dimensions of the array. The innovative features of this approach are the dependence of reconfiguration on the dimensions of the array to be reconfigured and a better exploitation of redundancy for run-time reconfiguration. Simple switching circuits are described. It is proved that silicon overhead consists of four two-by-two Banyan switches per cell. Illustrative examples are presented. Keywords. Reconfiguration, hexagonal array, reconfigurability, fault tolerance.

1. Introduction

Reconfiguration is a crucial process in the operation of Very Large Scale Integration (VLSI) systems. Reconfiguration is required at either production-time for yield improvement, or at run (application) time for fault tolerance [2,3]. Reconfiguration is accomplished by utilizing redundancy. Redundancy is allocated according to the functional specifications of the components in a system [12]. This makes reconfiguration at run-time a more complex process than redundancy allocation for sparing at production-time. Homogeneous systems are an optimal choice, because they provide modularity in redundancy allocation. * This research was supported in part by grants from AT&T, NATO and the Engineering Foundation. North-Holland INTEGRATION, the VLSI journal 6 (1988) 263-290 0167-9260/88/$3.50 © 1988, Elsevier Science Publishers B.V. (North-Holland)

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Redundancy is embedded in homogeneous VLSI systems (such as arrays) by adding extra rows and columns of cells (and associated interconnection circuitry) [3,6,8]. Eventhough on-line and off-line reconfiguration techniques employ different approaches, they share m a n y commonalities. Research in reconfiguration of VLSI arrays has been directed toward reducing reconfiguration-time while increasing the probability of reconfiguration. Sites of faulty cells are logged into a fault-map. This may is used to generate a reconfiguration-solution (whenever one exists). Different algorithms to compute a reconfiguration-solution have appeared in the literature [5,6,8]. A particular interesting approach is proposed in [15,16]. Each cell in the array is identified by a pair of physical indices denoting row and colunm. The whole array is represented by a physical index matrix, whose entries are the physical coordinates of the cells and a logical index matrix, that identifies the function of each cell at operation-time. In absence of faults, the two matrices are equal. After reconfiguration, entries of the logical index matrix may differ from the same entries of the physical index matrix. A new logical matrix must be generated. It has been proved [16] that this technique provides a good locality in the reconfigured array at a modest hardware overhead for routing and switching. Disadvantages of this approach are decreasing probability of successful reconfiguration in the presence of a large number of simultaneous faults and restricted n u m b e r of reconfiguration possibilities. A new approach is proposed in [13]. Reconfiguration consists of removing either rows or columns with faulty cells. Deletion of a row or a column is considered for process partitioning by execution in fixed size VLSI array architectures [1,13]. The novelty of this approach results from the fact that it exploits the characteristics of both the algorithm and the array architecture. In [5], a spare-efficient, but time-consuming approach for reconfiguration of VLSI is proposed. This approach, commonly referred to as the Diogenes approach, is more appropriate for off-line reconfiguration for production and yield improvement. Different criteria must be used for run-time reconfiguration. In particular, reconfiguration at run-time cannot be completely independent of processing, because stringent execution deadlines must be met. The following features must

Fabrizio Lombardi was born in Formia (Italy). He graduated in 1977 from the University of Essex (UK) with a B.Sc. (Hons.) in Electronic Engineering. In 1977 he joined the Microwave Research Unit at University College London, where he received the Master in Microwaves and Modern Optics (1978), the Diploma in Microwave Engineering (1978) and the Ph.D. (1982). He is currently an Associate Professor in the Department of Computer Science at Texas A&M University. He was the recipient of the 1985/86 Research Initiation Award from the IEEE/Engineering Foundation. Dr. Lombardi was also a co-director of the NATO Advanced Study Institute on Testing and Diagnosis of VLSI and ULSI, june 1987, Como (Italy), whose edited proceedings will soon appear in a book. His research interests are fault tolerant computing, testing, wafer scale integration and real-time systems.

F. Lombardi /Reconfiguration of hexagonal arrays

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be considered for on-fine reconfiguration: (1) Processing is usually synchronous [7,10,12]. (2) Processing proceeds along fixed directions; this permits data exchanges [12] between neighboring cells. Several measures [3,16] such as spare efficiency and silicon overheads, can be used to assess the effectiveness of redundancy for reconfiguration at run-time. To discriminate between these measures, reconfiguration can be analyzed with respect to the geometrical requirements and physical dimensions of an array chip. This type of reconfiguration is referred to as physical reconfiguration. This is different from the logical reconfiguration for algorithmic reduction of [15]. Physical reconfiguration assumes that the algorithm can be imbedded into a chip at the expense of a more geometrical and dynamic analysis of the array. In VLSI arrays, physical reconfiguration offers significant advantageous features. It avoids large overheads at Input/Output [10] by dealing with the internal array structure rather than the total reorganization of the algorithm. Correct execution is preserved by changing only the indices of the cells in the array, not involving complex switching hardware. One of the measures to assess physical reconfiguration is time required to determine a reconfiguration-solution. Approaches that can be implemented to determine reconfiguration-solutions of VLSI arrays for front reconfiguration by row/column deletion [22] have been presented. Research has dealt with reconfiguration of orthogonal arrays. However, array systems have different topologies that are more complex than the row and column connections of orthogonal arrays. A particular class of array that is particularly suitable for many known problems is the hexagonal configuration. Hexagonal arrays have been used for matrix multiplication and digital signal processing [1,7,9,17,23]. This paper deals with reconfiguration of hexagonal arrays. Reconfiguration is implemented by front reconfiguration using diagonal deletion. Preliminaries are dealt with in Section 2. In Section 3, a brief review of the front reconfiguration approach of [22] is presented. Geometrical considerations relating to diagonals in hexagonal arrays are analyzed in Section 4. Reconfiguration of hexagonal arrays is presented in Section 5. Several examples are also presented. New criteria for reconfiguration are introduced to account for a more complex interconnection network than in an orthogonal array and a simple row/column deletion. In Section 6, the conditions of diagonal deletion with respect to the dimensions of the target array are derived. These conditions are used to generate the reconfiguration-set. Section 7 establishes the criteria for reconfigurability and unreconfigurability of a hexagonal array. Reconfiguration algorithms are presented in Section 8. In Section 9, switching circuits and algorithms to implement the proposed reconfiguration techniques are described. Conclusions are addressed in the last section. 2. Preliminaries

This paper deals with two dimensional arrays with orthogonal (rows and columns) and transversal interconnections (diagonals). This type of array is

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~'~.\ ~ - ~ \ ~-..~\ ~.~,,~-~-~\ ~\ ~ ~ ~ ~ ~ ~ ~ ~~ ~ ~ ~ ~ L~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~a ~ ~ ~ ~~ ~ ~ ~ ~x~~~ ~ ~ x Fig. 1. A 16 x 16 hexagonal bussed array. commonly referred to as a hexagonal array. Figure 1 shows a 16 × 16 hexagonal array. The array is made of n cells. Cells are arranged in a two-dimensional fashion. The number of columns is given by N, while the number of rows is given by M. Therefore, n = NM. (1) The array is made of two cell banks: the operational bank and the redundant bank. The numbers of spare rows and columns are denoted to as R A and CA. The number of cells in the operational bank is given by no=(N-C~)(M-RA), (2) The number of cells (spares) in the redundant bank (equal to the m a x i m u m number of faulty cells, Ft) is Ft = n a = n - n o = N M - ( U - C A ) ( M - R A ) = N R A + MCA - RACA.

It is assumed that n 0 >~ n a,

(3) (4)

i.e.,

no<~n.

(5)

The following assumptions are made in the analysis: (1) Faults are associated with cells only. Run-time faults only are considered. Reconfiguration-controlling and switching circuits are assumed to be either self-testing [1,15], or self-checking [16]. These circuits are not hard core components. A more detailed analysis of switching circuits is presented in Section 9. No effects relating to yield are considered, since the reconfiguration analysis is not concerned with production.

F Lombardi /Reconfiguration of hexagonal arrays

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(2) Spare cells are identified by all those processing elements in excess to the ones required for a particular operational phase. (3) The reconfiguration algorithm is executed by a host computer. The host has full control over the processor array. (4) Faults occur randomly in the array, i.e., failure independence of cells is upheld. (5) Eventhough the number of simultaneous faults is small, faults can accumulate over a long period of time. Dynamic reconfiguration must be applied. It has been proved that dynamic reconfiguration offers significant advantages compared with static reconfiguration [13] for real-time processing. (6) Processing proceeds synchronously along the interconnections in a lock-step manner. (7) Each cell is identified by pairs of logical and physical indices in a fashion similar to [16]. Spare and faulty cells have null logical indices.

3. Front reconfiguration At run-time, reconfiguration of synchronous arrays is constrained by many limitations that are related to both the physical and the logical nature of processing. These limitations are: (1) Data (at inputs and outputs of the array) and processing are usually correlated [10]. Correlation is also preserved within the internal array structure. (2) Delay due to reconfiguration should be minimized for a synchronized flow of processing. Either wait-states for unreconfigured fault free cells, or complex switching circuits are required [16] to avoid uneven delay. In the first case, cell utilization is low. In the second case, hardware overhead can be significant [15]. (3) Processing (especially of a systolic nature [1]) shows a significant dependency on architectural/physical embedding of the algorithm, [10]. This is a very stringent requirement in fixed-size architectures [13] for high throughput. A new approach to array reconfiguration has been proposed in [22] to overcome the above limitations. This approach is referred to as front reconfiguration. Front reconfiguration exploits the commonalities between processing in adjacent cells found in systolic algorithms and the physical organization of the array. Front reconfiguration consists of the logical deletion of all those fault free cells that shows an algorithmic dependency with some other cells. A whole front, defined by the algorithm [13,22], is logically deleted from the array. This reconfiguration approach offers the following advantages. (1) Delay is uniform along the whole front of computation [22]. This reduces considerably hardware overhead. Switching circuits are simple and easily controllable.

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F. Lombardi / Reconfiguration of hexagonal arrays

(2) Algorithmic reduction and graceful degradation can be accomplished for many known problems [13]. (3) Reconfiguration is dynamically implemented. (4) Logical indices can be easily adjusted by the reconfiguration algorithm. The objective of physical reconfiguration is to reconfigure at least a ( M - R~) × ( N - CA) array (referred to as a target) in which cells are connected in the same fashion as in the original M × N array. This objective should be accomplished using a reconfiguration technique moderately complex to meet real-time deadlines and with fairly simple switching circuits. If reconfigurations is implemented by front deletion, it is appropriate to refer to this type of array as a bussed array [22]. The term bussed is applicable, because the array can be thought of as crossed by busses. As bus can be logically placed between connection paths. Failure of at least one of the cells connected to the bus implies its corruption. The bus and all cells attached to it must be discarded for reconfiguring the array. Equivalence of a bussed array to front reconfiguration of arrays is obvious, since both systems retain the same connectivity [25]. It will be assumed the array undergoes a t e s t i n g / d i a g n o s i s procedure [14]. The test results are represented by an M x N diagnostic matrix A = (aij). Element aij in the ith row and j t h column, is 0 (1) if the (i, j ) cell is fault free (faulty). The information supplied by the diagnostic matrix can be used to establish if spare availability is sufficient. This is referred to as reconfigurability detection. At run-time unreconfigurability of an array should be determined together with its reconfigurationsolution, because a low execution-time is highly d e p e n d e n t on an earliest detection [22]. The characterization of front deletion using r o w / c o l u m n reconfiguration is given by the following criteria [22]: (I) N o faulty cell shares either a row, or column with any other faulty cells. (II) The n u m b e r of faulty cells, that satisfy (I), exceeds the n u m b e r of spare rows and columns. This characterization is very important, because array reconfiguration is independent of the locations of faulty cells if only those cells that satisfy (I) and (II) can be used to establish an appropriate reconfiguration strategy. It has been proved [22] that if there exists a n u m b e r of faulty cells that do not share either a column a n d / o r a row with any other faulty cell and this n u m b e r exceeds the n u m b e r of spare rows and columns, the bussed array is not reconfigurable by front deletion. Equivalently, a bussed array is RA/C~-reconfigurable, if there exists a set of rows and columns (referred to as reconfiguration-solution), whose n u m b e r is less than the spare rows and columns and all nonzero elements of the diagnostic matrix are covered [22]. This covering property [19] has been used in [22] to derive the reconfiguration-set of a bussed array with r o w / c o l u m n deletion. The reconfiguration-sohition is found by refinement of the reconfiguration-set. To construct the reconfiguration-set, the leading element ai2 is defined. The leading element is the first non-zero element of A, such that the i th rQw is the first non-zero row and the (i, j)-entry is the first non-zero element of row i. The reconfiguration-set can be constructed as follows: initially, the leading element of

F. Lombardi / Reconfiguration of hexagonal arrays

269

A is selected; then all entries along either the row a n d / o r column of the leading element are replaced with zero entries. This process is repeated until the diagnostic matrix is a zero matrix. It has been possible to determine the reconfigurationsolution as function of the elements of the reconfiguration-set [22]. This process consists of finding if some of the elements in the reconfiguration-set can be deleted as faulty cells can be covered. This is accomplished by finding redundant elements in the reconfiguration-set. This process referred to as complement generation, aims at deleting from the reconfiguration-set all those elements whose covered cells can be also covered by the remaining elements. It has been proved [22] that front deletion offers the following advantages for run-time reconfiguration of VLSI orthogonal arrays: - Detection of reconfigurability/unreconfigurability and generation of the reconfiguration-solution are found at modest algorithmic complexity [22], hence reducing considerably execution-time. - Silicon overheads due to switching circuits are minimal. - Logical reconfiguration as well as physical rearrangement of the array is simple. - Locality and regularity of the interconnections are preserved. As mentioned above, the main disadvantage of front deletion in horthogonal arrays is the low spare utilization. This restricts front deletion to run-time, because at production-time high spare utilization is imperative to attain good yield.

4. D i a g o n a l s in h e x a g o n a l b u s s e d arrays

A hexagonal array is shown in Fig. 1. A set of interconnections referred to as the diagonal plane has been added to the orthogonal plane of rows and columns. Cell (i, j ) is also connected by a diagonal to cell (i - 1, j - 1), 2 ~< i ~< M and 2 ~ 0. The cardinality of D~, denoted by [D~ [, refers to the number of cells that lie along the k t h diagonal. In a M × N array, if k < min{ M, N}, [Dkl = k + 1. If min{M, N} ~ < k < m a x ( M , N}, IDkl = r a i n ( M , N}. If k > m a x { M , N}, [Dkl=min{M, N}-(k-max(M, N})-I=M+N-k-1. If [D~[ = 1 , a diagonal does not exist and it corresponds to either cell (M, 1) or (1, N). For notation consistency, cell (M, 1) is denoted by D 0, while cell (1, N) is denoted by DD+l. Figure 2 shows a 4 × 8 diagonal array and the numbering of the diagonals. The following Lemmas establish the number of diagonals in a hexagonal array. It is assumed that (max{ M, N } / m i n { M, N}) = k, where k is an integer. Lemma 1. In a right angle isosceles triangle (equal number of cells (nodes) along each side (L)), the number of diagonals is given by

D=L-1.

(6)

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F. Lombardi / Reconfiguration of hexagonal arrays DD+1 (I,N)

D9

D8

DO (M, i)

DI

D2

D3

D4

D5

D6

D7

Fig. 2. 4 x 8 hexagonalbussed array; diagonal numbering. Proof. The ith nodes on opposite sides of the triangle are connected by a diagonal. The node at the vertex of the right angle cannot be connected to any other node. Hence, (6) is obtained by definition. [] Lemma 2. The number of diagonals of a M × N array is given by

D=M+N-1.

Proof. This Lemma is proved by partitioning the rectangular array into equal square subarrays (Fig. 3). Each square subarray is a min{ M, N } × rain{ M, N }. This subarray can be partitioned into two right-angle isosceles triangles. In Fig. 3, the triangles are denoted to as T1 and T2. These triangles are of equal area and of side L = min{ M, N },

(7)

because the major diagonal is shared. By Lemma (1), each triangle has a number of diagonals given by

DT= min{ M, N } - 1.

(8)

The number of diagonals in the square subarray is DO = 2 D r + a = z m i n { M ,

U}-l.

(9)

The diagonals which generate from vertices in T1, are common to the second

Fig. 3. Array partition.

F. Lombardi /Reconfiguration of hexagonal arrays

271

square subarray by geometry. A new diagonal is generated by the node at the right angle in T1. Using L e m m a (1) and (9), the total n u m b e r of diagonals is D=DQ+max{(M,

U}-min{M,

=M+N-1. Hence, the L e m m a is proved.

U)) (10)

[]

5. Reconfiguration and diagonals In a hexagonal bussed array, redundancy is still added as r e d u n d a n t rows and columns. If reconfiguration must be accomplished by diagonal deletion, some correctness rules need to be satisfied for the generation of the target array. (1) The number of fault free cells in every row of the target array must be at least ( N - CA). (2) The number of fault free cells in every column of the target array must be at least ( M - R A). These rules restrict the number of diagonals that can be deleted. In a fashion similar to r o w / c o l u m n reconfiguration, a fault counter can be associated with each diagonal: for D k, the fault counter is denoted to as C(Dk). Naively, one may consider to delete all the diagonals whose fault counter is not equal to 0. This intuitive approach does not guarantee the generation of a target array. This is caused by deletion of certain diagonals that do not delete a cell for either each row, or column of the array. This creates a disparity in the dimensions of the target array. It is therefore imperative to consider diagonal deletion by the number of deleted cells along the same row and column. The following Theorems characterize the deleted cells for two diagonals. Theorem 1. Let D~ and D~ be two deleted diagonals, fl < a. In a M × N array, there are no deleted cells along the same rows and columns between D~ and D/~ if a-/3)

max(M, U}.

(11)

Proof. To prove the Theorem it is sufficient to show that the coordinates of the extremes of the deleted diagonals satisfy certain conditions under the constraint of (11). Assume that M < N. L e m m a (1) established the n u m b e r of diagonals. The coordinates (Fig. (4)) are either (M, 1 + a), if a ~< N - 1, or ( M - ( a - N + 1), N ) if a >~ N for the lower extreme (denoted to as cell L~). For the upper extreme (denoted to as U~) the coordinates are ( M - a, 1) if a ~< M - 1 or (1, a - M + 2) if a >~M. The coordinates of the extremes L¢ and U¢ of De are given by substituting a and /3 in the above expressions. For no deleted cells along same rows and columns between D~ and D~, XLo < X ~

(12)

lq Lombardi / Reconfiguration of hexagonal arrays

272

U

UBX ~

LB

Lo D

Fig. 4. Diagonals definitions for deletion of cells along rows and columns.

and

Y o> YLo

(13)

By substituting the values of the coordinates in (12), M-(a-N+

(14)

I)
or

N
(15)

-ft.

Since (16)

o~ - fl >~N.

(15) can be written as N < N + 1,

(17)

which is always true. By substitution, (13) can be rewritten as a

/3

M+I>0,

(18)

or

N > M - 1.

(19)

By assumption, this is always true. Hence, the Theorem is proved for N > M. The proof for M ~< N is similar and is omitted. [] Theorem 2. Let D~ and D e be two deleted diagonals, B < a. In a M x N array, there are deleted cells along the same rows (columns) between D, and D e if rain{M, N } ~ < a - f l < m a x { M ,

N},

(20)

provided that N > M (M > N).

Proof. Assume M < N and the same definition of coordinates as in the proof of Theorem (1). For deleted cells along the same row, Yu,, > Y~,,,

(21)

XL," > Xv,.

(22)

and

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F. Lombardi / Reconfiguration of hexagonal arrays ~

•

•

•

•

•

•

•

•

•

O•

~

• •

•

•

•

~

•

Fig. 5.

By substituting the coordinate val,ues into (22), a-M+2>1+/3,

(23)

N-M>O.

(24)

or (24) is always true. If the same substitutions are performed in (21), X-a-l>~-/3,

(25)

a - / 3 ~< N - 1,

(26)

or which is always true. If (26) does not hold, then XL~ <

Xu~,

(27)

or equivalently, a - / 3 > N - 1.

(28)

This contradicts the right-hand side of (20). Hence the T h e o r e m is proved for M < N. For N < M, the proof is similar and is omitted. [] This theorem is illustrated in Fig. 5. If a = 7 and fl = 1, a - / 3 = 6 < 8; (22) is satisfied. Theorem 3. Let D~ and D# be two deleted diagonals, fl < a. In a M × N array, there are deleted cells along all rows and columns between D~ and D# if a - / 3 < rain{ M, N ) .

(29)

Proof. Assume M < N and the same definition of coordinates as used in the proof of Theorem (2). For deleted cells along the same rows and columns,

xLo

(30)

Yvo ~< YL~.

(31)

and

F. Lombardi /Reconfiguration of hexagonal arrays

274

0

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

Fig. 6.

For (31), substitution yields a-M+2~
(32)

M-2-M+I~<0,

(33)

or

which is always verified. Using (30), substitution yields M-(a-N+

I)> M-/3,

(34)

or

m-l>.~a-/3.

(35)

By definition of the array, this is true. (30) and (31) can be negated if (29) is used. Hence, the Theorem is proved. [] Consider the diagonal array shown in Fig. 6; (29) is satisfied if a = 3 and /3=1. The following Corollaries hold for square hexagonal arrays (N = M). Corollary 1. Let D, and D¢ be two deleted diagonals, fl < ~. In a N x N array there are deleted cells along the same rows and columns between D~ and D¢ if

a - fl ~
(36)

Proo[. The proof of this Corollary follows from Theorem (3) and will be omitted. [] Corollary 2. In a N × N hexagonal array it is not possible to have deleted cells along either the same rows or columns between two deleted diagonals.

Proof. The proof of this Corollary follows from Theorem (12) and Corollary (1). Assume that a - / 3 >~N.

(37)

There are no deleted cells along the same columns and rows between D, and D~ by Theorem (10). If c~- / 3 < N,

(38)

F. Lombardi / Reconfiguration of hexagonal arrays

~

U

~

•

~

~

•

•

~

\

•

~

•

•

•

~

•

•

•

•

•

•

•

•

275

Fig. 7. by Theorem (3) there are deleted cells along the same rows and columns between D~ and D,. Hence, the Theorem is proved. [] Consider the square array shown in Fig. 7; a = 7, fl = 2 and N = 6. (36) is satisfied, because a - f l = 5 < 6.

6. Reconfiguration-set generation The Theorems in Section 5 can be used to determine new criteria of diagonal deletion for the selection of the elements of the reconfiguration-set in which the correctness rules in the dimensions of the target array can be satisfied. Consider the M × N diagonal array shown in Fig. 8, M < N . The rectangle can be partitioned in three subarrays: (1) T1, an isosceles triangle of side ( M - 1). (2) P1, a parallelogram of side ( N - M + 1) and height ( M - 1)v~-. (3) T2, an isosceles triangle of side M - 1, similar to T1. This partition can be used to define the implications of front deletion in a hexagonal array. These implications have been previously characterized by Theorems (1), (2) and (3).

Fig. 8. Partitions in hexagonal bussed arrays for front deletion.

F. Lombardi / Reconfiguration of hexagonal arrays

276

If D, lies either on the boundaries, or inside P1 ( a > M - 1), then a cell in certain rows will be deleted from the array. Only those columns C~, whose subscript satisfies a-M+2~
(39)

will have a cell deleted from the array. Multiple diagonals inside P1 need to be deleted for all columns to have a deleted cell. Only certain rows and columns will have a deleted cell if a D~ lies in either T~ ( a < M - 1) or T2 (~ > N - 1). A Da in T2 must be also deleted, if a D~ is deleted in T 1, to have a deleted cell in all rows, where U + (~ = r ,

(40)

by Theorem (10), since fl > a. The above conditions yield the following observations for deletion of equal number of cells in either rows, or columns. (1) Diagonals that lie in the right angle isosceles triangles, are better suited for deletion of a cell in each row (row-deletion equivalence). (2) Diagonals that lie in the parallelogram are suited for deletion of a cell in each column (column-deletion equivalence). While column-deletion equivalence can be achieved by a single diagonal deletion, row-deletion equivalence requires deletion of multiple diagonals. These diagonals contribute simultaneously to a single row-deletion equivalence and to multiple column-deletion equivalence. The above observation suggests that diagonal deletion is best applicable to arrays in which a large number of redundant columns are available, i.e., Ca >> R A. If SD denotes the reconfiguration-set (i.e., the set of deleted diagonals), the Algorithm to find the reconfiguration-set in a hexagonal array is given as follows. Algorithm 1. Reconfiguration-set with diagonals for N > M.

Step l. Initialize, SD= (

); v a r = 0 ;

C=CA; R = R A ;

ISRI=]ScI=O;

SzS=-

}. Step 2. S E = { }. Find the leading element of the diagnostic matrix A, say a,j; if C = 0, Flagc = 1; if R = 0, Flagr = 1. If C = R = 0, Flagc = Flagr = 2. Step 3. a~j lies on the a t h diagonal, D,, S c = { a}. I SE I = 1. Find the row-wise (if Flagr 4= 1) and column-wise (if Flagc 4= 1) counters. Step 4. If either Flagr = 1, or Flagc = Flagr = 2 to to Step (10). Compare R with IS~[; if R < I SEI, go to Step (10). Step 5. Compare C ~ ( a ) and c~c(~). Establish the m a x i m u m fault count Cmax and adjust S~. Step 6. Sel = 1. If C ~ ( a ) = Cma×, delete all 1-entries along the a t h diagonal and all those diagonals for row-deletion equivalence given by the set SE; go to Step (7). Otherwise continue.

F. Lombardi /Reconfiguration of hexagonalarrays

277

Step 7. Sel = 2; C~(a) = Cm~,; delete all 1-entries along the a t h diagonal and all those diagonals for column-deletion equivalence; C = C - 1; I Scl = I Sc I + 1.

IS~l ~ 0 , then S e = S e - S ~ ;

Step 8. Find S~=SoC3Se. If

R=R+

IS~l.

so=sou&. Step 9. If Sel = 1, then S~ = S~ tO Se; otherwise, S~ = S~ u Se. Go to Step (11). Step 10. Sel = 1, Cma,,= cff~(a); delete all 1-entries along D e. S E = {a}. Go to Step (8).

Step 11. If A is not a zero matrix, go back to Step (2). Step 12. The reconfiguration-set with diagonals S o has been found. In Algorithm (1), deletion of D~ postulates the following conditions as particular cases of r o w / c o l u m n equivalence deletion. (1) For single row-deletion equivalence, the single row-wise counter c~(a) must be found first. This is given by

c~(a) = Co(a) + Y'~ CD(fl), /~

(41)

where the summation terms corresponds to all those Dt~'s that satisfy (40). The row-wise counter is finally given by Cff(a) = c ~ ( a ) + Y'.c~(7), v

(42)

v ÷ / 3 ÷ 1 = ISEI.

(43)

where fl is the number of diagonals in (41), the y summation terms in (42) are given by the largest single row-wise counters. (2) For column deletion equivalence, the column-wise counter C~(a) is given by cg(a) = co(a) + Z co(i),

(44)

for all those D i that satisfy (41). Consider the fault pattern shown in Fig. 9; R,~ = 1 and C,~ = 2. The first leading element is (1, 2) which lies on D4; Co~(4) = 4 and coC(4) = 2. The first row deletion equivalence is SE = {0, 4, 8}. The other two deletions are column-deletion equivalence given by D 5 and D 6. For the fault pattern shown in Fig. 10, c ~ ( 8 ) = Co(8 ) + C o ( 0 ) = 3, while c~C(4) = Co(4 ) + Co(O) + Co(S ) = 1 + 1 + 2 = 4. The number of column-deletion in a row-deletion equivalence is dependent on the total dimension of the array including the added redundancy. For an N × M array with N > M and a single row-deletion equivalence, the number of columndeletion equivalence is given by

[ N / M ] = IS el >~ 2

(45)

F. Lombardi /Reconfiguration of hexagonal arrays

278 •

•

•

•

•

•

~\ g

•

o~

•

•

~

•

•

-

•

-

•

•

~

"~

•

Fig. 9,

•

•

•

•

•

Fig. 10.

if no diagonal lies inside the isosceles triangles; otherwise,

[ Se I = [ N / M ]

+ 1.

(46)

Without loss of correctness the following analysis will assume that

N/M = k

(47)

where k is an integer. In Fig. 10, k = 2. The dissimilarity of diagonal deletion with r o w / c o l u m n deletion is more pronounced by the implication of row-deletion equivalence. Row-deletion equivalence implies also multiple column-deletion equivalences. This characteristic is referred to as redundancy duality. It can be proved that redundancy duality applies to the smallest dimension of the array: for N > M, redundancy duality applies to row-deletion. Duality applies to column-deletion equivalence for M > N. While row- and column-deletion equivalences have different implications in rectangular arrays ( N ~ M ) , they are equivalent in square arrays. Diagonal deletion in a square array always implies a deletion of both a row and a column. This can be trivially proved by using Corollaries (1) and (2).

7. Reconfigurability and unreconfigurability Reconfigurability has been defined in [22] as the probability to correctly diagnose an array as reconfigurable prior to execution of the reconfiguration algorithm.

F. Lombardi /Reconfiguration of hexagonalarrays

279

Reconfigurability of hexagonal arrays can be established by analyzing fault counters. The number of single column-wise counters must be established for all those diagonals that lie in the two right-angle isosceles triangles of Fig. 8. The number of single column-wise counters must be added to the counters of those diagonals that lie in the parallelogram section of the array. If the number of diagonal counters whose content is greater than 0 is denoted by E and C~ denotes that total number of logically redundant columns (inclusive of the columns required for row-deletion equivalences), the following Lemmas establish the unreconfigurability and reconfigurability of diagonal arrays. Lemma 3. A bussed hexagonal array is R a / CA unreconfigurable, if z >

(48)

Proof. This Lemma will be proved by contradiction. Assume that a hexagonal array with CA/R a redundancy is reconfigurable for 2; = C~ + 1. (ISEIRA) columns can be used for /~a row-deletion equivalences. The remaining number of columns (i.e., C ~ - I S e IRa) can be used as columns-deletion equivalences. Adding these two quantities, and comparing the sum with the number of logically redundant colunms, the condition is given by

C ~ - [ S e l R a +[SEIRA < ~ .

(49)

This results in a contradiction. The array is unreconfigurable and (48) must be satisfied. [] Lemma 4. A hexagonal array is R a / C a reconfigurable if <.

and

c,~ > [sEII~a.

(Sl)

Proof. The proof follows from Lemma (3) and the constraint of (47). It is omitted due to lack of space. [] The above Lemmas give reconfigurability/unreconfigurability of hexagonal array by comparing the number of column-wise fault counters and the provided redundancy. This can be integrated into the reconfiguration algorithm for reconfigurability detection prior to the execution of Algorithm (1). In a hexagonal bussed array with Ra/Ca redundancy, provided that (51) is satisfied, the following features may be considered for front-deletion equivalence: (1) Row-deletion equivalence must be carried not to interfere with the availability of redundant rows that are required for column-deletion equivalence. (2) Row-deletion equivalence cannot be compared with only a single columndeletion equivalence, but with IS el column-deletion equivalences. (3) If a diagonal that has been already deleted, is required by a row-deletion equivalence, a further column-deletion equivalence can be added to the reconfiguration process.

F. Lombardi/Reconfigurationof hexagonalarrays

280

8. Reconfiguration algorithms The Algorithm for reconfiguration of hexagonal bussed arrays is as follows (it is assumed that (47) is satisfied). Algorithm 2. Reconfiguration by diagonal deletion for hexagonal bussed arrays (N > M).

Step 1. Calculate the number of diagonal fault counters whose content is greater than 0 and C~.

Step 2. If Lemma (6) is satisfied, go to Step (7). Otherwise continue. Step 3. Execute Algorithm (1). Step 4. If I SR I > RA, go to Step (7). Step 5. If I acl > CA, go to Step (7). Step 6. The hexagonal array is not unreconfigurable; go to Step (8). Step 7. The hexagonal bussed array is unreconfigurable. Step 8. Reconfiguration by diagonal deletion is completed. Algorithm (2) is applicable under any spare availability. This is independent of the relationship between /~A and CA (given by (51)). If (51) is known to be satisfied, a new Algorithm for reconfiguration and generation of the reconfiguration-set is possible. Algorithm 3. Reconfiguration and Reconfiguration-set Generation for Diagonal Deletion with Known Redundancy.

Step 1. Sz~ = ~ counter Cff( i).

}. For all D i (i = 1, D) in the array, find the row-wise fault

Step 2. Sort all the row-wise fault counters found in Step (1) into a list of ascending order of magnitude.

Step 3. Select the first R a entries delete all 1-entries along the select diagonals. These are the row-deletion equivalences. Adjust Sz~ accordingly.

Step 4. CA=C~ - ISEIRA; C = 0 . Step 5. Sort all single column-wise counters in a list of ascending order. Step 6. Select the first Ca entries; delete all 1-entries among the selected diagonals; C = C + Ca. Adjust SD accordingly. Step 7. Test if the diagnostic matrix A is a not-zero matrix. If so, go to Step (11). Otherwise continue.

281

F. Lombardi /Reconfiguration of hexagonal arrays

,O

•

• • Fig.11.

~N,~O, •

•

~D

Step 8. For the row-wise counters selected in Step (3), find a row-wise counter that utilizes the least number of diagonals with at least 1-entry; x = 1.

Step 9. If the number of 0-entry diagonals in the row-wise counter of Step (8) is either equal, or larger than the number of single column-wise counters left in A after deletion, then reset to their original status all those diagonals with at least a non-zero entries. Delete all 1-entries along the diagonals left in A. Adjust Sz~ accordingly and go to Step (11). Otherwise, continue.

Step 10. If the number of all 0-entry diagonals is less than the number of single column-wise counters left in A after deletion, find another row-wise counter which utilizes the least number of diagonals with at least a faulty cell; x = x + 1. If x > CA go to Step (12). Otherwise add the number of 0-entry diagonals with previous selections and go to Step (9). Step 11. The array is reconfigurable. Go to Step (13). Step 12. The array is unreconfigurable. Step 13. Reconfiguration is complete. Consider the fault pattern shown in Fig. 11. If R A = 2, CA = 1 and C~ = 5. Algorithm (3) resolves the first row-deletion equivalence by using D 3 and D 7. The second row-deletion equivalence consists of using Do, D 4 and D 8. The single column-deletion equivalence is given by D a and D 9. Note that in Steps (8)-(9), D 4 is found to have only fault free cells. The second row-deletion equivalence can be changed to a column deletion, while D 4 is kept in the reconfigured array. Algorithm (3) provides both the reconfiguration-set and array reconfiguration. It differs from Algorithm (2) by the following features. (1) Adjustment to the reconfiguration-solution due to lack of redundant columns is performed after row-deletion equivalence is implemented (Step(8)-(10)). (2) Row-deletion equivalence is carried prior to column-deletion equivalence. This avoids the complexity of Step (4) in Algorithm (1). This is required to satisfy the higher number of columns involved into a single row-deletion equivalence.

282

F. Lornbardi / Reconfiguration of hexagonal arrays •

•

•

•

•

•

•

"O

~

•

•

"O

•

~o

F~. ~ .

Consider the fault pattern shown in Fig. 12; Ca = 1 and R a = 2 (C~ = 5). If row-deletion equivalence consists of D 3 and DT, this array is unreconfigurable, because three column deletions are required (D4, Ds, and D O- D8). If a row-deletion equivalence consists of D 0, D 4 and D 8, the array is reconfigurable, because the remaining faults can be covered by deleting D 3 and D5 as column-deletion equivalences. Execution complexity of reconfiguration of hexagonal bussed arrays according to Algorithms (2) and (3) is O ( M + N ) for both algorithms. This is optimal because diagonal selection is linear with respect to the dimension of the array [11]. This complexity measure is valid provided that the redundant bank has not a larger number of cells than the operational bank.

9. Switching circuits and algorithms Front reconfiguration of hexagonal arrays requires different switching configuration than those commonly found in the literature [21,22]. In [13,22] a switch configuration has been proposed for r o w / c o l u m n deletion. This configuration is applicable to algorithmic reduction and front reconfiguration of orthogonal arrays. The proposed switch configuration is shown in Fig. 13 and 14. The basic switching element is a 2 x 2 Banyan switch [18]. The two inputs of this switch can be connected to the two outputs by either straight, or crossed connections (baseline configuration). This switch can be made fault tolerant at low hardware costs [19]. The differences between this switching configuration and commonly found interconnection networks are the sequential clocking of the D lines and the connection between adjacent Banyan switches. The D (disable) lines are used to disable all those cells that lie along elements of the reconfiguration-solution. The switch associated with each (i, j ) cell is denoted to as SW~,j. This switch consists of two parts: a row switch, denoted to as SWn(i, j ) and a column switch, denoted to as S W c ( i , j ) . The operation of SI,V~,j is shown in Table 1. Switching is controlled by the control data placed on the D lines. The D lines are loaded with the reconfiguration information provided by the host. Data is loaded in each register and shifted synchronously either along the row of the

283

F. Lombardi / Reconfiguration of hexagonal arrays a

Dlr D2r

In

>

(i,j)

~

X

~

Out

~

(i,j+1)

b

~

>

In

[~> (~-~,j-~)

(i,j)

Did

Out

~

D2d Fig. 13. (a) Row switch; (b) diagonal switch.

column. This loads the switches with the information to bypass any of the cells which lie along deleted diagonals. Row/column deletion in orthogonal bussed arrays follows the same connectivity pattern of the reconfigured array and switching is implemented in a straight(i-l,j)

,~ ~

~ ~,

SWBL

SWBR

OUtL ~

> OutR

() (i,j) Fig. 14. Column switch in hexagonal bussed arrays.

284

F. Lombardi / Reconfiguration of hexagonal arrays

Table 1

sw~(~,~)

SWc(~,~)

Connection

D1R

D2R

Connection

Dlc

(i,j)~(i,j+l)

0

0

(i,j)-~(i+l,j)

0

D2c 0

(i, j ) ~ Out In --, (i, j + 1) In ~ Out

0 1 1

l 0 1

(i, j ) --~ Out In --, (i + 1, j ) I n --, Out

0 1 1

l 0 1

forward manner [22]. Diagonal deletion however affects rows and columns without necessarily creating an immediate copy of the array as a target. This is caused by the following reasons. (1) Deleted cells lie along different rows and columns. This does not preserve the symmetry of deletion found in orthogonal arrays [22]. (2) An adjustment of the diagonals is required after reconfiguration, Switching in hexagonal bussed arrays consists of three procedures. Each procedure builds a part of the interconnection of the target array. Prior to execution of these three procedures, index mapping is performed. Logical indices are recomputed rowwise for all cells that do not lie along deleted diagonals. Cells which lie along deleted diagonals have null logical indices. These procedures use a deformation matrix D and the diagnostic matrix A. An entry (i, j ) in D is given by 0 if agj = 1, if a~j = 0, the (i, j ) entry in D contains the logical indices of this cell in the reconfigured array. The first procedure for generating row connections (using the row switch of Fig. 13(a)) is given by the following algorithm. Algorithm 4. Row switching in hexagonal bussed arrays.

Step 1. Do Step (2) i = 1 to M. Step 2. Generate the logical indices (from left to right) of all cells that do not lie along deleted diagonals (the corresponding entry in the matrix D is not 0), but they lie along the ith row.

Step 3. End of Loop i Step 4. Load the switches using the DR lines. Step 5. Row switching is finished. This procedure is shown in Fig. 15 by reconfiguring R~_ a and R i. The second procedure deals with connecting fault free cells column-wise within the fixed row assignment found by Algorithm (4). Consider the column connection between a cell with physical and logical indices (i, j ) and a cell with physical and logical indices ( i + 1, j + 1). Cells with physical indices (i, j - 1 ) and (i + , j) lay on a deleted diagonal. The column connection between cells (i, j ) and (i + 1, j + 1) consists of a connection between cells (i, j ) and (i + 1, j ) and

F. Lombardi / Reconfigurationof hexagonalarrays

\

285

\ \

\

\

\

Fig. 15. Row switching in hexagonal bussed arrays. a connection between cells (i + 1, j ) and (i + 1, j + 1). These connections are established using the column switches. The column switch of cell (i, j ) is denoted to as SWB(i, j ) . A column switch has been shown in Fig. 14. It consists of two Banyans: SWBL(i, j) and SW~R(i, j). SWnI~(i, j ) is governed b y the code on the D~c lines. This is given in Table 3. Table 4 shows the operation of SWnR(i, j). Figure 16 shows the interconnections between adjacent column switches. Switches of adjacent cells are connected in cascade, i.e., Out/~ from SWBL(i, j) is connected to InL into S W e c ( i , j - ) , Inz~ into SWnz(i,j) is connected to Out/~ from SW~L(i,j+ 1). Equivalently, Out~ from SWB~(i,j) is connected into In~

Table 3

SW~L(i,j) Connection (i, j) --, (i - 1, j) (i, j ) --, OutL

DIBL

D2~ L

0

0

In~ --, (i - 1, j )

0 1

1 0

In L -o OutL

1

1

Table 4

SWB~(i,j) Connection

D1B R

(i, j)-"(i--1, j)

0

D2BR 0

(i, j ) --~ Out R Ine ~ (i -- 1, j ) In~ -o OutR

0 1 1

1 0 1

286

F. Lombardi /Reconfiguration of hexagonal arrays (i-1,j-l)

(i-I ,j)

( ~ - i , j+1)

SWBR

;: (i,j-1)

(~,j)

(i,j+l)

Fig. 16. Column switches in hexagonal bussed arrays. from SWBR(i,j+ 1), In R into (i, j ) is connected t o O u t R from SWBR(i,j-l). This is shown in Fig. 18. The column connection between cells (i, j ) and ( i + 1, j + 1) consists of connecting S W s L ( i + 1, j + 1) to SW~L(i+ 1, j) and SWsL(i + 1, j) tO SWsL(i, j). A connection between two cells with equal column logical indices on two adjacent rows follows at worse a M a n h a t t a n strategy [20]. This consists of a bypass connection (either from left to right, or from right to left) that utilizes switching circuits of faulty cells and an upward column connection that utilizes column switches. The procedure for generating the column switching in a hexagonal bussed array in given as follows. Algorithm 5. Column switching in hexagonal bussed arrays.

Step 1. i = 1; row number. Step 2. D o Step (3) j = I to N. Step 3. For a fault free cell whose physical indices are ( M + 1 - i, j ) , find its logical index, say (i', j ' ) . Find the physical indices of a cell with logical indices a r e ( / ' - 1, j ' ) , s a y ( M - i, k). If k = j , t h e n c o n n e c t ( M ÷ 1 - i, j ) t o ( M - i, k) using the switches. If k > j ( j > k), then starting from ( M + 1 - i, j ) bypass all those cells with physical indices ( M + 1 - i, h), h = j + 1, . . . , k - 1, ( ( M + 1 - i, h'), h' -- k - 1 . . . . . j - 1). Cell ( M + 1 - i, k) is connected by using switches to cell ( M ÷ I - i, j ) . Cell ( M + 1 - i, k) is then connected to cell ( M + 1 - i, k). Step 4. i = i + 1; upgrade row number. Step 5. If i = M, continue to Step (6). Otherwise, go to Step (2).

F. Lombardi /Reconfiguration of hexagonal arrays

287

•

~

•

•

•

~

•

•

•

•

~

•

*

"~

•

•

•

•

Fig. 17. Column switching in a hexagonal bussed array.

6. Column switching is implemented by loading the matrices throughthe D~L and D~Rlines. Step 7. Columnswitchingis finished. Step

DBL

and

DBR

Figure17 showsthe switchingarrangementrequiredto reconfigurea columnin hexagonalbussedarrays. Figure18 illustratescolumnand row switchingconnections in a partiallyreconfiguredhexagonalarray. The last procedure for switchingof hexagonalbussed arrays consist of the diagonal connections.Diagonalconnectionsare establishedin a manner similar \

",~',~

~i

"

~

"~'l \ ~ _ _ O ~ \ ""

~

.r

,,~,'~ °, ! i,

,

~ ,~"

" ~

~"

N

N N

', ' . ~

N

Fig. 18. Row and column switching in a hexagonal bussed array.

N

F. Lombardi / Reconfiguration of hexagonal arrays

288

(i-I ,j-3)

(i,j-3)

\

(i-l,j-2)

(i ,j-2)

(i-I 3 - 1 )

(i-l,j)

(i,j-l)~

(i,j)

Fig. 19. Diagonal connection between (i, j) and (i - I, j - 3).

to rows. Consider for example, a diagonal connection between cells with physical indices (i, j ) and (i - 1, j - 3) with the appropriate logical indices. (i - 1, j - 2) lies on a deleted diagonal and cell (i - 1, j - 1) has not the appropriate logical indices. The diagonal connection consists of two parts: a horizontal bypass up to cell (i, j - 2) and an upward diagonal connection between cell (i, j - 2) and (i - 1, j - 3). This is shown in Fig. 19. The hardware for diagonals is similar to the one used for row switching. The diagonal switch for cell (i, j ) is denoted to as SWz~(i,j) and has been shown in Fig. 13(b). Table 5 shows the operation of SWD(i,j). The algorithm for diagonal switching in hexagonal bussed array uses the matrix DD to load the D o lines with the correct switching information. This Algorithm is as follows. Algorithm 6. Diagonal switching in hexagonal bussed arrays.

Step 1. i = M. Step 2. j = N . Step 3. If (i, j ) is faulty, go to Step (6). Find the physical indices of the cell whose physical indices are (i, j), say (i, h). Step 4. Find the physical indices of the cell whose logical indices are (i - 1, h - 1), say (i - 1, k).

Step 5. If k = h - 1, then connect these cells using SWo(i, j).

Table 5

swo~i,j) Connection

D 1D

D2 D

(i, (i, In In

0 0 1 1

0 1 0 1

j) j) --, ~

~ (i - l , j - 1 ) --, O u t (i - 1, j - 1) Out

289

F. Lombardi /Reconfiguration of hexagonal arrays

\

~ _ _ ~ - ~

\

,

~..~.~

", ~

.,,

~. , . ~'~ ~ ~ ... ~ I ~ , ,, ~ ~ " ~ ,, ~~ X

~

X

]

,~

~

~

Fig. 20. Full switc~ng in a hexagonalbussed array. Step 6. k < h - 1, then bypass all' those cells up to the cell with physical indices (i, k + 1). Using SWo(i, k + 1), connect (i, k + 1) to (i - 1, k). Step 7. j = j - 1. If j 4: 1, go to Step (3). Step 8. i = i - 1. If i 4: 1, go to Step (2). Step 9. Diagonal switching is implemented by loading DD through the D o lines. Step 10. Diagonal switching is complete.

Figure 20 shows the complete reconfigured array of Fig. 18. Hexagonal and orthogonal bussed arrays can be compared with respect to switching complexity. In a diagonal array a cell (i, j ) that does not lie on the boundary, requires four 2 × 2 Banyan switches. The same cell in an orthogonal array requires only two switches [22]. This increase in switching complexity is due to the nonsymmetric nature of front deletion along diagonals due to column switching. Diagonals and rows can be implemented along a unique switching direction. This is from left to right for rows and from right to left for diagonals. Direction of switching for diagonals depends on the logical indices of the cells. The indices cannot be guaranteed to lie on a fixed direction. Hence, two Banyans are required.

10. Conclusions

An approach to reconfiguration of hexagonal arrays has been presented. Reconfiguration is implemented by deletion of cells along the diagonal front of computation. Various algorithms have been proposed. The algorithms compute unreconfigurability, reconfigurability and reconfiguration at low execution complexity. Different techniques have been proposed. These techniques rely on manipulating information provided by counters to determine the diagonals to be deleted from the array while preserving the correct dimensions of the target array. Switching circuits that are required for implementation of the proposed reconfiguration approach, have been presented.

290

F. Lombardi / Reconfiguration of hexagonal arrays

11. References [1] Kung, H.T. and C.E. Leiserson, Algorithms for VLSL processor arrays, in: C. Mead and L. Conway, eds., Introduction to VLSI Systems, (Addison Wesley, Reading, MA, 1980) Section 8.3. [2] Uhr, L., Computer Arrays and Networks: Algorithm-structured Parallel Architectures (Academic Press, New York, NY, 1982). [3] IEEE ISSCC Digest of Technical Papers, Section on Memories and Redundancy Techniques (1981) pp. 80-87. [4] Mangir, T.E. and A. Avizienis, Fault tolerant design for VLSI: Effect of interconnection requirement on yield improvement of VLSI design, IEEE Trans. Comput. C31(7) (1982) 609-615. [5] Rosenberg, A.L., The diogenes approach to testable fault tolerant VLSI processor arrays, IEEE Trans. Comput. C32(10) (1983) 902-910. [6[ Leighton, T. and C.E. Leiserson, Wafer-scale integration of systolic arrays, IEEE Trans. Comput. C34(5) (1985) 448-461. [7] Batcher, K.Z., Architecture of a Massively Parallel Processor, Proc. 7th Syrup. Comp. Arch., (1980) 169-173. [8] Snyder, L., Introduction to the configurable highly and parallel computer, IEEE Comput 15(1) (1982) 47-56. [9] Kulkarni, A.V. and J. Vuillemin, Systolic processing and an implementation for signal and image processing, IEEE Trans. Comput. C31(10) (1982) 1000-1009. [10] Leiserson, C.E. and J.B. Saxe, Optimizing synchronous systems, Proc. A C M FOCS (198l) 23-36. [11] Garey, M.R., and D.S. Johnson, Computers and Intractability (Freeman, San Francisco, CA, 1979). [12] Kung, S.Y., Arun, K.S., Gal-Ezer, R.J. and D.V.B. Rao, Wavefront array processor: language, architecture and applications, IEEE Trans. Comput. C31(11) (1982) 1054-1066. [13] Fortes, J.A.B. and C.S. Radhavendra, Gracefully degradable processor arrays, IEEE Trans. Comput. C34(11) (1985) 1033-1044. [14] Malek, M. and Y.H. Choi, Real time diagnosis of homogeneous systems, Proc. Real-Time Systems Symp. (1985) 155-159. [15] Sami, M.G. and R. Stefanelli, Fault tolerance of VLSI processing arrays: The time redundancy approach, Proc. Real-Time Systems Symp. (1984) 200-207. [16] Negrini, R., R. Stefanelli and M.G. Sami, Fault tolerance technique for array structures used in supercomputing, IEEE Computer 19(2) (1986) 78-87. [17] Kung, H.T., Systolic algorithms for the CMU warp processor, Proc. 7th lnternat. Conf on Pattern Recogn. (1984) 570-577. [18] Goke, L.R. and G.J. Lipovski, Banyan network for partitioning multiprocessor systems, Proc. 1st Ann. Syrup. on Comp. Arch. (1973) 21-28. [19] Cherkassky, V., E. Opper and M. Malek, Reliability and fault diagnosis analysis of fault-tolerant multistage interconnection networks, Proc. FTCS (1984) 246-251. [20] Mead, C. and L. Conway, Introduction to VLS1 Systems, (Addison-Wesley, Reading, MA, 1980). [21] Katevenis, M.G.H. and M.G. Blatt, Switch design for soft configurable WSI systems, Chapel Hill Conf on VLSI (1985) 197-219. [22] Lombardi, F., Reconfiguration of VLSI/WSI arrays by row/column deletion, to appear. [23] Kung, S.Y., On supercomputing with systolic/wavefront array processors, Pro¢. IEEE 72(7) (1984) 867-884.