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Reduction of boron penetration for a p+ polycide gate by using cobalt silicides as a boron diffusion source
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Solid-State Electronics Vol. 42, No. 3, pp. 389±392, 1998 # 1998 Elsevier Science Ltd. All rights reserved Printed in Great Britain 0038-1101/98 $19.00 + 0.00 S0038-1101(97)00211-6
REDUCTION OF BORON PENETRATION FOR A p+ POLYCIDE GATE BY USING COBALT SILICIDES AS A BORON DIFFUSION SOURCE M. H. JUANG, H. C. CHENG, W. K. LAI and C. J. YANG Department of Electronics Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan (Received 22 May 1997; in revised form 8 July 1997; accepted 5 August 1997) AbstractÐA scheme for forming a p+ polycide gate is described, by using BF2 implantation into CoSi/ poly-Si bilayer ®lms and subsequent annealing. Instead of the conventional BF2 implantation into thin poly-Si ®lms, this scheme employs the CoSi layer as an implant barrier as well as a boron diusion source to retard the boron diusion. The improved gate oxide integrity and the reduced ¯at-band voltage shift can be obtained without causing other side eects. In addition, it is found that the stack layer of CoSi/a-Si can serve as an excellent implant barrier for suppressing the boron penetration through a gate oxide. # 1998 Elsevier Science Ltd. All rights reserved
1. INTRODUCTION
With the scale-down of MOSFET devices in deep submicron integration technology, the p-MOSFET using a n+ poly-Si gate is susceptible to punchthrough leakage due to buried-channel operations[1±3], unless extra well-designed drain and/or channel engineering is employed[4±6]. Therefore, the surface channel p-MOS device using a p+ polySi gate appears as a promising candidate for subquarter-micron technology. The boron penetration through thin gate oxide would cause the shift of ¯atband voltage (Vfb), the distortion of the capacitance±voltage curve, the increase of the subthreshold swing, and the deterioration of the gate oxide integrity. To suppress the boron penetration, several methods have been reported previously[7±13]. Thermally nitrided gate oxide or reoxidized nitrided oxide could act as a good diusion barrier against boron[8,9]. The large grain size formed by as-deposited amorphous silicon (a-Si) ®lms could inhibit the ¯uorine and boron diusion[10]. Suppression of boron penetration in a BF2-implanted p+ gate can be achieved by trapping of ¯uorine in an amorphous-Si gate[12]. On the other hand, CoSi2 has several performance and process advantages compared to TiSi2 which has scaling problems[14]. In addition, a selfaligned cobalt silicided shallow p+n junction can be formed by BF2 implantation into thin Co, CoSi or CoSi2 ®lms which serve as a diusion source as well as an implantation barrier[15,16]. In this paper, the scheme using CoSi as a boron diusion source as well as an implantation barrier has been undertaken to form a p+ polycide gate by reducing the rapid ¯uorine/boron diusion. 389
Electrical characterization has been done to show the feasibility of associate process conditions. 2. EXPERIMENTAL DETAILS
(100) oriented, 3±5 ohmcm, n-type Si wafers were used. Field oxides of 450 nm were grown for patterning the active regions of MOS capacitors. Thin gate oxides of 8 nm were thermally grown at 9008C in dry O2 ambient at the active area. Undoped poly-Si ®lms of 100 nm were then deposited by low-pressure-chemical-vapor-deposition (LPCVD) at 6208C and followed by gate delineation. Part of the samples, namely the poly-Si samples, were implanted by BF+ (40 keV, 2 5 1015 cmÿ2). Thin Co ®lms of about 9 and 13.5 nm, respectively, and thin Mo capping layers of about 18 nm were then sequentially sputtered onto all the samples. Two-step annealing for the Co salicide process was carried out, with the ®rst step being done by rapid thermal annealing (RTA) at 4508C for 60 s. After the annealing, the Mo and the unreacted Co layers on ®eld oxide were selectively removed in a 5:1:1 mixture of H2O:H2O2:NH4OH and a 6:1:1 mixture of H2O:H2O2:HCl, correspondingly, at 55± 608C. The bilayer ®lms of CoSi/poly-Si were formed accordingly. The resulting CoSi ®lms are about 18 or 27 nm in thickness. The samples without receiving a BF+ 2 implant previously, namely the CoSi/ poly-Si samples, were implanted by BF+ 2 (55 keV, 5 1015 cmÿ2) through the CoSi/poly-Si bilayer ®lms, instead of the poly-Si ®lms only for the above poly-Si samples. The second step annealing was done by RTA at 700±10008C for 60 s, which is for further cobalt silicidation into CoSi2 as well as for
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Fig. 1. Dependencies of breakdown ®eld strength (Ebd) on RTA temperature for the samples with poly-Si and CoSi(27 nm)/poly-Si as the implantation barrier, respectively
dopant activation and/or boron out-diusion from silicide into thin poly-Si ®lms. The resultant MOScapacitor characteristics were analyzed by C±V and I±V methods.
3. RESULTS AND DISCUSSION
From the previous shallow-junction studies[15,16], the usage of CoSi as an implant barrier as well as a boron diusion source could eectively reduce the boron diusion. Hence, this scheme is supposed to retard the boron penetration through gate oxides. Figure 1 shows the dependencies of the breakdown ®eld strength (Ebd) on RTA temperature for the poly-Si and the CoSi(27 nm)/poly-Si samples, respectively. The Ebd for the CoSi/poly-Si samples is larger than that for the poly-Si ones, re¯ecting the considerably reduced boron penetration. Moreover, the charge to oxide breakdown (Qbd) can be improved from a value lower than 0.5 C/cm2 for the poly-Si samples to become larger than 2.5 C/cm2 for this scheme. As a result, the usage of CoSi as an implant barrier as well as a boron diusion source can eectively inhibit the boron penetration which degrades gate oxides. The rapid ¯uorine/boron diusion due to the presence of defects while annealing would appear as an inevitable driving force for further boron penetration. When the CoSi implant barrier is used, the largely reduced residual defects would lessen the defectenhanced ¯uorine/boron diusion. Figure 2 shows the normalized high-frequency gate C±V pro®les for the CoSi (27 nm)/poly-Si samples annealed at various RTA temperatures. The ¯at-band voltage (Vfb) of these samples with a CoSi barrier are measured to be about 0.7, 1.0 and
Fig. 2. Variations of normalized high-frequency gate capacitance with gate voltage for the samples with CoSi(27 nm)/poly-Si as the implantation barrier
1.2 V, correspondingly, for 700, 800, and 9008C. However, for the poly-Si samples, the Vfb is about 1.3, 1.5, and 1.8 V, respectively. The Vfb shift due to boron penetration is signi®cantly reduced by using this scheme. The implant barrier for the polySi sample is just poly-Si (100 nm), whereas that for the bilayer specimen is CoSi(27 nm)/poly-Si(75 nm). On the other hand, as the CoSi thickness is thinned from 27 nm to 18 nm, the eect of retarding boron penetration is lessened. Figure 3 plots the normalized high-frequency gate C±V curves for the samples with a 18 nm CoSi barrier. The resultant Vfb values are about 0.9, 1.2, and 1.4 V, correspondingly, for 700, 800, and 9008C, which are larger than those for the samples with 27 nm CoSi barrier. This result is attributable to the degraded dopant con®nement during implantation.
Fig. 3. Normalized high-frequency gate C±V characteristics for the samples with CoSi(18 nm)/poly-Si as the implantation barrier
Reduction of boron penetration for P+ Polycide Gate
The CoSi/poly-Si bilayer ®lms can be employed to eectively retard the boron penetration. No potential contact or long-diusion-path-induced issues causing high gate resistance, such as multi-stacked structures of stacked-amorphous-silicon, etc.[12], may be present for this scheme. However, the dopant out-diusion from the silicides into the underlying poly-Si layer should be sucient to avoid a possible poly-Si gate depletion eect. Hence, given a silicide thickness, the implant condition and the annealing cycle should also be optimized to prevent boron penetration while retaining device performance. No poly-Si depletion eect is observed for the CoSi/poly-Si samples. However, as a CoSi/a-Si stack layer is used, instead of a CoSi/poly-Si, anomalous C±V characteristics are found when the RTA temperature is as low as 7008C. The undoped a-Si ®lms of 100 nm were deposited by LPCVD at about 5508C. And the ®lms were still amorphous after the CoSi formation, since the ®rst-step annealing for forming CoSi was only 4508C. Figure 4 shows the normalized gate C±V pro®les for the CoSi(27 nm)/ a-Si samples. The accumulation-mode capacitance for the sample annealed at 7008C is about 20% lower than that for the specimens annealed at temperatures higher than 8008C. In addition, the Vfb values are about 0, 0.5, and 0.6 V, correspondingly, for 700, 800, and 9008C. The a-Si ®lms have been reported to be capable of eectively trapping the ¯uorine atom and thus retarding the boron penetration[12]. According, the usage of a CoSi/a-Si stack layer would further retard the ¯uorine/boron diusion. As a result, the Vfb shift is small even at high RTA temperatures. However, owing to both the eects from the CoSi implantation barrier and the a-Si ®lm, the boron diusion is signi®cantly retarded. Therefore, when the thermal cycle is not
391
Fig. 5. Dependencies of ¯at-band voltage (Vfb) on RTA temperature for the samples with CoSi(27 nm)/a-Si and CoSi(18 nm)/a-Si as the implantation barrier, respectively
large enough, the doping concentration of the resultant poly-Si layer can be low, especially near the poly-Si/SiO2 interface, which leads to the relatively low Vfb value and small accumulation-mode gate capacitance at 7008C. On the other hand, as the CoSi(18 nm)/a-Si stack layer is employed, the dopant con®nement during implantation is reduced relative to that for the CoSi(27 nm)/a-Si, thus alleviating the occurrence of a poly-Si depletion eect at low RTA temperatures. Figure 5 shows the dependencies of Vfb on RTA temperature for the CoSi(27 nm)/a-Si and the CoSi(18 nm)/a-Si samples, respectively. The Vfb shift for the CoSi(18 nm)/a-Si sample is still small even at RTA temperatures higher than 8008C. However, the suggested poly-Si depletion eect for the sample RTA-treated at 7008C is signi®cantly suppressed, and with the accumulation-mode gate capacitance being again recovered to normal values. As a consequence, in terms of the CoSi/a-Si stack layer, in addition to the eect of the CoSi layer, the a-Si ®lms would further retard boron diusion and suppress boron penetration. Hence, in the presence of an a-Si layer, the CoSi and a-Si ®lm thickness as well as the associate process conditions should be controlled to optimize the device performance while preserving a large process window. Nevertheless, the CoSi/a-Si layer can be employed as an excellent implant barrier for suppressing boron penetration.
4. CONCLUSIONS
Fig. 4. Variations of normalized high-frequency gate capacitance with gate voltage for the samples with CoSi(27 nm)/a-Si as the implant barrier
As for the conventional way that forms a p+ polycide gate by direct BF2 implant into thin polySi ®lms, the thin gate oxides are severely deteriorated and the ¯at-band voltage shift is considerable. By using the CoSi layer as an implant barrier and a boron diusion source, the boron penetration
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M. H. Juang and C. J. Yang et al.
through the gate oxide can be signi®cantly reduced without inducing other side eects. In addition, the CoSi/a-Si stack layer is found to result in largely retarded boron diusion at a RTA temperature of 7008C, due to both eects from the CoSi barrier and the a-Si ®lms. Accordingly, the stack layer of CoSi/a-Si can be employed as an excellent implant barrier to suppress the boron penetration. AcknowledgementsÐThe research was supported in part by the Republic of China National Science Council under the Contract number NSC 86-2621-E011-007-T. In addition, the author would like to thanks W. K. Lai, N. C. Chen and Professor H. C. Cheng at National Chiao Tung University and National Nano Device Lab., Hsinchu, Taiwan, for technical support. REFERENCES
1. Hu, G. J. and Bruce, R. H., IEEE Trans. Electron Devices, 1985, 32, 584. 2. Matsuoka, F., Iwai, H., Hayashida, H. and Maeguchi, K., IEEE Trans. Electron Device, 1990, 37, 1487. 3. Tanaka, K. and Fukuma, M., in IEDM Tech. Dig., 1987, p.628.
4. Hori, T. and Kurimoto, K., in IEDM Tech. Dig., 1988, p.394. 5. Miyake, M., J. Electrochem. Soc., 1990, 137, 2860. 6. Cham, K. M. and Chang, S., IEEE Trans. Electron Dev., 1984, 31, 964. 7. Tseng, H.-H., Orlowski, M., Tobin, P. J. and Hance, R. L., IEEE Electron Device Lett., 1992, 13, 14. 8. Lo, G. Q. and Kwong, D.-L., IEEE Electron Device Lett., 1991, 12, 175. 9. Ma, Z. J., Chen, J. C., Liu, Z. H., Krick, J. T., Cheng, Y. C., Hu, C. and Ko, P. K., IEEE Electron Device Lett., 1994, 15, 109. 10. Koda, M., Shida, Y., Kawaguchi, J. and Kaneko, Y., in IEDM Tech. Dig., 1993, p.316. 11. Oikawa, K., Ando, S., Ando, N., Horie, H., Toda, Y., Tanaka, T. and Hijiya, S., in IEDM Tech. Dig., 1991, p.79. 12. Lin, C. Y., Chang, C. Y. and Hsu, C. C.-H., IEEE Trans. Electron Device, 1995, 42, 1503. 13. Lu, C. Y., Sung, J. M., Kirsch, H. C., Hillenius, S. J., Smith, T. E. and Manchanda, L., IEEE Electron Device Lett., 1989, 10, 192. 14. Maex, K., Semiconductor International, March 1995, pp.75±80. 15. Juang, M. H., Lin, C. T. and Cheng, H. C., J. Appl. Phys., 1995, 76, 1323. 16. Cheng, H. C., Juang, M. H., Lin, C. T. and Huang, L. M., IEEE Electron Device Lett., 1994, 15, 342.
Solid-State Electronics Vol. 42, No. 3, pp. 389±392, 1998 # 1998 Elsevier Science Ltd. All rights reserved Printed in Great Britain 0038-1101/98 $19.00 + 0.00 S0038-1101(97)00211-6
REDUCTION OF BORON PENETRATION FOR A p+ POLYCIDE GATE BY USING COBALT SILICIDES AS A BORON DIFFUSION SOURCE M. H. JUANG, H. C. CHENG, W. K. LAI and C. J. YANG Department of Electronics Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan (Received 22 May 1997; in revised form 8 July 1997; accepted 5 August 1997) AbstractÐA scheme for forming a p+ polycide gate is described, by using BF2 implantation into CoSi/ poly-Si bilayer ®lms and subsequent annealing. Instead of the conventional BF2 implantation into thin poly-Si ®lms, this scheme employs the CoSi layer as an implant barrier as well as a boron diusion source to retard the boron diusion. The improved gate oxide integrity and the reduced ¯at-band voltage shift can be obtained without causing other side eects. In addition, it is found that the stack layer of CoSi/a-Si can serve as an excellent implant barrier for suppressing the boron penetration through a gate oxide. # 1998 Elsevier Science Ltd. All rights reserved
1. INTRODUCTION
With the scale-down of MOSFET devices in deep submicron integration technology, the p-MOSFET using a n+ poly-Si gate is susceptible to punchthrough leakage due to buried-channel operations[1±3], unless extra well-designed drain and/or channel engineering is employed[4±6]. Therefore, the surface channel p-MOS device using a p+ polySi gate appears as a promising candidate for subquarter-micron technology. The boron penetration through thin gate oxide would cause the shift of ¯atband voltage (Vfb), the distortion of the capacitance±voltage curve, the increase of the subthreshold swing, and the deterioration of the gate oxide integrity. To suppress the boron penetration, several methods have been reported previously[7±13]. Thermally nitrided gate oxide or reoxidized nitrided oxide could act as a good diusion barrier against boron[8,9]. The large grain size formed by as-deposited amorphous silicon (a-Si) ®lms could inhibit the ¯uorine and boron diusion[10]. Suppression of boron penetration in a BF2-implanted p+ gate can be achieved by trapping of ¯uorine in an amorphous-Si gate[12]. On the other hand, CoSi2 has several performance and process advantages compared to TiSi2 which has scaling problems[14]. In addition, a selfaligned cobalt silicided shallow p+n junction can be formed by BF2 implantation into thin Co, CoSi or CoSi2 ®lms which serve as a diusion source as well as an implantation barrier[15,16]. In this paper, the scheme using CoSi as a boron diusion source as well as an implantation barrier has been undertaken to form a p+ polycide gate by reducing the rapid ¯uorine/boron diusion. 389
Electrical characterization has been done to show the feasibility of associate process conditions. 2. EXPERIMENTAL DETAILS
(100) oriented, 3±5 ohmcm, n-type Si wafers were used. Field oxides of 450 nm were grown for patterning the active regions of MOS capacitors. Thin gate oxides of 8 nm were thermally grown at 9008C in dry O2 ambient at the active area. Undoped poly-Si ®lms of 100 nm were then deposited by low-pressure-chemical-vapor-deposition (LPCVD) at 6208C and followed by gate delineation. Part of the samples, namely the poly-Si samples, were implanted by BF+ (40 keV, 2 5 1015 cmÿ2). Thin Co ®lms of about 9 and 13.5 nm, respectively, and thin Mo capping layers of about 18 nm were then sequentially sputtered onto all the samples. Two-step annealing for the Co salicide process was carried out, with the ®rst step being done by rapid thermal annealing (RTA) at 4508C for 60 s. After the annealing, the Mo and the unreacted Co layers on ®eld oxide were selectively removed in a 5:1:1 mixture of H2O:H2O2:NH4OH and a 6:1:1 mixture of H2O:H2O2:HCl, correspondingly, at 55± 608C. The bilayer ®lms of CoSi/poly-Si were formed accordingly. The resulting CoSi ®lms are about 18 or 27 nm in thickness. The samples without receiving a BF+ 2 implant previously, namely the CoSi/ poly-Si samples, were implanted by BF+ 2 (55 keV, 5 1015 cmÿ2) through the CoSi/poly-Si bilayer ®lms, instead of the poly-Si ®lms only for the above poly-Si samples. The second step annealing was done by RTA at 700±10008C for 60 s, which is for further cobalt silicidation into CoSi2 as well as for
390
M. H. Juang and C. J. Yang et al.
Fig. 1. Dependencies of breakdown ®eld strength (Ebd) on RTA temperature for the samples with poly-Si and CoSi(27 nm)/poly-Si as the implantation barrier, respectively
dopant activation and/or boron out-diusion from silicide into thin poly-Si ®lms. The resultant MOScapacitor characteristics were analyzed by C±V and I±V methods.
3. RESULTS AND DISCUSSION
From the previous shallow-junction studies[15,16], the usage of CoSi as an implant barrier as well as a boron diusion source could eectively reduce the boron diusion. Hence, this scheme is supposed to retard the boron penetration through gate oxides. Figure 1 shows the dependencies of the breakdown ®eld strength (Ebd) on RTA temperature for the poly-Si and the CoSi(27 nm)/poly-Si samples, respectively. The Ebd for the CoSi/poly-Si samples is larger than that for the poly-Si ones, re¯ecting the considerably reduced boron penetration. Moreover, the charge to oxide breakdown (Qbd) can be improved from a value lower than 0.5 C/cm2 for the poly-Si samples to become larger than 2.5 C/cm2 for this scheme. As a result, the usage of CoSi as an implant barrier as well as a boron diusion source can eectively inhibit the boron penetration which degrades gate oxides. The rapid ¯uorine/boron diusion due to the presence of defects while annealing would appear as an inevitable driving force for further boron penetration. When the CoSi implant barrier is used, the largely reduced residual defects would lessen the defectenhanced ¯uorine/boron diusion. Figure 2 shows the normalized high-frequency gate C±V pro®les for the CoSi (27 nm)/poly-Si samples annealed at various RTA temperatures. The ¯at-band voltage (Vfb) of these samples with a CoSi barrier are measured to be about 0.7, 1.0 and
Fig. 2. Variations of normalized high-frequency gate capacitance with gate voltage for the samples with CoSi(27 nm)/poly-Si as the implantation barrier
1.2 V, correspondingly, for 700, 800, and 9008C. However, for the poly-Si samples, the Vfb is about 1.3, 1.5, and 1.8 V, respectively. The Vfb shift due to boron penetration is signi®cantly reduced by using this scheme. The implant barrier for the polySi sample is just poly-Si (100 nm), whereas that for the bilayer specimen is CoSi(27 nm)/poly-Si(75 nm). On the other hand, as the CoSi thickness is thinned from 27 nm to 18 nm, the eect of retarding boron penetration is lessened. Figure 3 plots the normalized high-frequency gate C±V curves for the samples with a 18 nm CoSi barrier. The resultant Vfb values are about 0.9, 1.2, and 1.4 V, correspondingly, for 700, 800, and 9008C, which are larger than those for the samples with 27 nm CoSi barrier. This result is attributable to the degraded dopant con®nement during implantation.
Fig. 3. Normalized high-frequency gate C±V characteristics for the samples with CoSi(18 nm)/poly-Si as the implantation barrier
Reduction of boron penetration for P+ Polycide Gate
The CoSi/poly-Si bilayer ®lms can be employed to eectively retard the boron penetration. No potential contact or long-diusion-path-induced issues causing high gate resistance, such as multi-stacked structures of stacked-amorphous-silicon, etc.[12], may be present for this scheme. However, the dopant out-diusion from the silicides into the underlying poly-Si layer should be sucient to avoid a possible poly-Si gate depletion eect. Hence, given a silicide thickness, the implant condition and the annealing cycle should also be optimized to prevent boron penetration while retaining device performance. No poly-Si depletion eect is observed for the CoSi/poly-Si samples. However, as a CoSi/a-Si stack layer is used, instead of a CoSi/poly-Si, anomalous C±V characteristics are found when the RTA temperature is as low as 7008C. The undoped a-Si ®lms of 100 nm were deposited by LPCVD at about 5508C. And the ®lms were still amorphous after the CoSi formation, since the ®rst-step annealing for forming CoSi was only 4508C. Figure 4 shows the normalized gate C±V pro®les for the CoSi(27 nm)/ a-Si samples. The accumulation-mode capacitance for the sample annealed at 7008C is about 20% lower than that for the specimens annealed at temperatures higher than 8008C. In addition, the Vfb values are about 0, 0.5, and 0.6 V, correspondingly, for 700, 800, and 9008C. The a-Si ®lms have been reported to be capable of eectively trapping the ¯uorine atom and thus retarding the boron penetration[12]. According, the usage of a CoSi/a-Si stack layer would further retard the ¯uorine/boron diusion. As a result, the Vfb shift is small even at high RTA temperatures. However, owing to both the eects from the CoSi implantation barrier and the a-Si ®lm, the boron diusion is signi®cantly retarded. Therefore, when the thermal cycle is not
391
Fig. 5. Dependencies of ¯at-band voltage (Vfb) on RTA temperature for the samples with CoSi(27 nm)/a-Si and CoSi(18 nm)/a-Si as the implantation barrier, respectively
large enough, the doping concentration of the resultant poly-Si layer can be low, especially near the poly-Si/SiO2 interface, which leads to the relatively low Vfb value and small accumulation-mode gate capacitance at 7008C. On the other hand, as the CoSi(18 nm)/a-Si stack layer is employed, the dopant con®nement during implantation is reduced relative to that for the CoSi(27 nm)/a-Si, thus alleviating the occurrence of a poly-Si depletion eect at low RTA temperatures. Figure 5 shows the dependencies of Vfb on RTA temperature for the CoSi(27 nm)/a-Si and the CoSi(18 nm)/a-Si samples, respectively. The Vfb shift for the CoSi(18 nm)/a-Si sample is still small even at RTA temperatures higher than 8008C. However, the suggested poly-Si depletion eect for the sample RTA-treated at 7008C is signi®cantly suppressed, and with the accumulation-mode gate capacitance being again recovered to normal values. As a consequence, in terms of the CoSi/a-Si stack layer, in addition to the eect of the CoSi layer, the a-Si ®lms would further retard boron diusion and suppress boron penetration. Hence, in the presence of an a-Si layer, the CoSi and a-Si ®lm thickness as well as the associate process conditions should be controlled to optimize the device performance while preserving a large process window. Nevertheless, the CoSi/a-Si layer can be employed as an excellent implant barrier for suppressing boron penetration.
4. CONCLUSIONS
Fig. 4. Variations of normalized high-frequency gate capacitance with gate voltage for the samples with CoSi(27 nm)/a-Si as the implant barrier
As for the conventional way that forms a p+ polycide gate by direct BF2 implant into thin polySi ®lms, the thin gate oxides are severely deteriorated and the ¯at-band voltage shift is considerable. By using the CoSi layer as an implant barrier and a boron diusion source, the boron penetration
392
M. H. Juang and C. J. Yang et al.
through the gate oxide can be signi®cantly reduced without inducing other side eects. In addition, the CoSi/a-Si stack layer is found to result in largely retarded boron diusion at a RTA temperature of 7008C, due to both eects from the CoSi barrier and the a-Si ®lms. Accordingly, the stack layer of CoSi/a-Si can be employed as an excellent implant barrier to suppress the boron penetration. AcknowledgementsÐThe research was supported in part by the Republic of China National Science Council under the Contract number NSC 86-2621-E011-007-T. In addition, the author would like to thanks W. K. Lai, N. C. Chen and Professor H. C. Cheng at National Chiao Tung University and National Nano Device Lab., Hsinchu, Taiwan, for technical support. REFERENCES
1. Hu, G. J. and Bruce, R. H., IEEE Trans. Electron Devices, 1985, 32, 584. 2. Matsuoka, F., Iwai, H., Hayashida, H. and Maeguchi, K., IEEE Trans. Electron Device, 1990, 37, 1487. 3. Tanaka, K. and Fukuma, M., in IEDM Tech. Dig., 1987, p.628.
4. Hori, T. and Kurimoto, K., in IEDM Tech. Dig., 1988, p.394. 5. Miyake, M., J. Electrochem. Soc., 1990, 137, 2860. 6. Cham, K. M. and Chang, S., IEEE Trans. Electron Dev., 1984, 31, 964. 7. Tseng, H.-H., Orlowski, M., Tobin, P. J. and Hance, R. L., IEEE Electron Device Lett., 1992, 13, 14. 8. Lo, G. Q. and Kwong, D.-L., IEEE Electron Device Lett., 1991, 12, 175. 9. Ma, Z. J., Chen, J. C., Liu, Z. H., Krick, J. T., Cheng, Y. C., Hu, C. and Ko, P. K., IEEE Electron Device Lett., 1994, 15, 109. 10. Koda, M., Shida, Y., Kawaguchi, J. and Kaneko, Y., in IEDM Tech. Dig., 1993, p.316. 11. Oikawa, K., Ando, S., Ando, N., Horie, H., Toda, Y., Tanaka, T. and Hijiya, S., in IEDM Tech. Dig., 1991, p.79. 12. Lin, C. Y., Chang, C. Y. and Hsu, C. C.-H., IEEE Trans. Electron Device, 1995, 42, 1503. 13. Lu, C. Y., Sung, J. M., Kirsch, H. C., Hillenius, S. J., Smith, T. E. and Manchanda, L., IEEE Electron Device Lett., 1989, 10, 192. 14. Maex, K., Semiconductor International, March 1995, pp.75±80. 15. Juang, M. H., Lin, C. T. and Cheng, H. C., J. Appl. Phys., 1995, 76, 1323. 16. Cheng, H. C., Juang, M. H., Lin, C. T. and Huang, L. M., IEEE Electron Device Lett., 1994, 15, 342.