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Reduction of defects in TSV filled with Cu by high-speed 3-step PPR for 3D Si chip stacking
Microelectronics Reliability 51 (2011) 2228–2235
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Reduction of defects in TSV filled with Cu by high-speed 3-step PPR for 3D Si chip stacking Sung Chul Hong a, Wang Gu Lee a, Won Joong Kim a, Jong Hyeong Kim b, Jae Pil Jung a,⇑ a b
Dept. of Materials Sci. and Eng., University of Seoul, Seoul 130-743, Republic of Korea Seoul Nat’l University of Science & Technology, Seoul 139-743, Republic of Korea
a r t i c l e
i n f o
Article history: Received 30 March 2011 Received in revised form 24 June 2011 Accepted 27 June 2011 Available online 23 July 2011
a b s t r a c t The reduction of defects and high-speed copper filling into a through-silicon-via (TSV) for the threedimensional stacking of Si chips were investigated. The via, with a diameter and depth of 30 lm and 60 lm, respectively, was prepared on a Si wafer by a deep reactive ion etching (DRIE) process. SiO2, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a 3-step periodic-pulse-reverse (PPR) current waveform was suggested for electroplating. The 3-step PPR consisted of low, medium and high current densities for the 1st, 2nd and 3rd steps, respectively. After Cu filling, in order to estimate defects in the Cu-filling, the via was cross-sectioned and observed by field emission scanning electron microscopy (FE-SEM), and also an X-ray radiographic test was performed for non-destructive inspection. The experimental results showed the via was fully filled without a serious defect by the 3-step PPR process after 80 min of plating, specifically, by current densities of 1.24, 3.22, and 9.89 mA/cm2 (1st/2nd/3rd step, respectively). The 3-step PPR filling was a kind of bottom-up filling process of Cu into the via, and it was effective for Cu filling in a short time. Defects, like voids in the Cu-filled TSV, were identified by the X-ray radiographic test, which can be useful for ensuring the reliability of a fragile thin Si wafer for 3D packaging. Ó 2011 Elsevier Ltd. All rights reserved.
1. Introduction Recently, electronic devices tend to be light in weight, and have high performance with low power consumption and low prices. In order to satisfy this tendency, these devices require miniaturization with respect to their packaging technology [1]. Three-dimensional (3-D) chip stacking is a popular candidate to meet such miniaturization needs. It has the advantages of volume reduction compared to conventional planar chip arrays as well as reduction of their power consumption, due to its shorter conduction path between the stacked chips. However, 3-D chip packaging also has some problems, such as difficulty to identify the presence of tiny internal defects in the stacked chips, fast via formation, high-speed via filling with conductive material, the formation of uniform bumps, and mechanical and thermal issues caused by the chip thinning [2]. Therefore, studies on 3-D chip stacking are ongoing at various levels [3–9]. Among the various 3-D packaging technologies, the most promising one is through-silicon-via (TSV) technology [2,10]. 3-D packaging with TSV consists of via (TSV) formation, the filling of a conductive material into the via, wafer thinning, and chip stacking using a metal bump [11,12]. Cu electroplating is a commonly used process for via filling [13,14]. However, shortcomings of the Cu ⇑ Corresponding author. E-mail address: [email protected] (J.P. Jung). 0026-2714/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2011.06.031
electroplating are the very long process time, about 15 h, to fill the via [15], as well as the difficulty to get a fully filled via for a small via width or large aspect ratio. Thus, many studies have been conducted in an attempt to shorten the Cu-filling time with achieving fewer defects [16,17]. To reduce the Cu-filling time and defect ratio in electroplating, a pulse-reverse (PR) current waveform [16,18,19] modified from the pulse current [20] (see Fig. 1a) or the addition of inhibitors and accelerator to the plating solution has been reported [21–25]. However, the PR current waveform has a slow filling speed compared to the constant current waveform. Many studies have been performed about the addition of an inhibitor and accelerator, such as polyethylene glycol (PEG), halide ions, and sulfur-containing organic compounds, to the electrolyte to establish a bottom-up Cu filling process [21–25], which can reduce void defects in the Cufilled via. However, it is difficult to find the optimal combination of inhibitor and accelerator. The authors’ previous study [26] demonstrated that a periodicpulse-reverse (PPR) current waveform was useful for the high-speed filling of Cu into a straight via. The PPR waveform is characterized by the addition of a current-off duration after the oxidation current (i.e. prior to the reduction current) during electroplating (see Fig. 1b). However, the PPR current waveform is still not satisfactory in terms of its filling ratio, due to frequent defects caused by the non-bottomup Cu-filling.
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2. Experimental A h1 0 0i p-type Si wafer, having a diameter of 100 mm and thickness of 525 lm, was selected as the substrate. In order to produce via holes on the wafer surface, a photo resist (PR, model: AZ4620) was spin-coated with a thickness of 10 lm. A via array pattern with a 30 lm diameter and a 200 lm pitch was produced by exposing the PR to ultraviolet (UV) rays. Each wafer was composed of 240 chips with a size of 5 5 mm and 192 vias were prepared in each chip. Subsequently, the wafer was etched by the deep reactive ion etching (DRIE) method and cylindrical shaped vias were produced which had a diameter of 30 lm and depth of 60 lm. As an insulation layer, SiO2 was formed by high density plasma chemical vapor deposition (HDP CVD). Ti and Au layers were deposited by sputtering in the via wall as adhesion and seed layers, respectively. However, a barrier layer against the Au seed layer was not considered in order to simplify the Cu-filling process. The Si wafer was cut into chips by a diamond saw. The diced chip was used as the cathode for Cu filling by electroplating, and a Pt sheet (size; 10 10 0.3 mm) was used as the anode. The distance between the electrodes was 30 mm. The electroplating solution for Cu filling was composed of 103.08 g/L of CuSO45H2O, 32 ml/L of H2SO4, 0.24 ml/L of HCl, and 4 g/L of an additive. The chloride ion (HCl in this study) reduces the polarization of the anode and the sulfur containing organic (H2SO4 in this study) plays the role of an accelerator [27]. The additive used in this study was one of the suppressors studied by Mendez et al. [28]. The electrolyte in the plating bath was stirred continuously by a magnetic bar with a rotating speed of 200 rpm (revolutions per minute), and the electrolyte was kept at room temperature during electroplating. A commercial pulse-plating unit (EPP-4000 from Princeton Applied Research) was used as a power supply for the electroplating. The reference electrode was a standard calomel electrode (SCE). The current waveform of the 3-step PPR was applied to the cathode of the Si chip for electroplating. The 3-step PPR consisted of a low current density duration (1st step), medium current density duration (2nd step), and high current density duration (3rd step) (see Fig. 1c). The Cu-filled via was examined by field emission scanning electron microscopy (FE-SEM) to investigate the filling ratio of the vias. Using the FE-SEM images, the Cu-filled area was measured by the Carl Zeiss Axiovision program. The Cu filling ratio was calculated according to the relation [(Cu filled area in the via/via area) 100%] [26]. Non-destructive inspection by the X-ray radiographic test was applied to the Cu-filled vias to check for the presence of defects such as voids.
3. Results and discussion 3.1. Functional layers
Fig. 1. Current waveform of pulse-reverse (PR); (a), periodic pulse reverse (PPR) current, (b) [26], and 3-step PPR current methods (c) for Cu filling into a via.
In this study, the 3-step PPR current waveform was suggested to reduce defects in the Cu filling of the via and to increase the via filling speed by establishing a bottom-up Cu-filling process. The X-ray radiographic test was also employed for the non-destructive inspection of the defects in Cu filling. However, the issue of the high aspect ratio of the via was not considered, because the purpose of this study was to confirm if the bottom-up process could be successfully achieved by optimizing the current waveform.
Before Cu filling into the via, functional layers consisting of dielectric, adhesion, and seed layers were coated on the via wall. Fig. 2a shows a cross-section view of the via hole fabricated by DRIE on a Si wafer which has a depth of 60 lm and a diameter of 30 lm. On the via wall, Ti and Au layers were found as adhesion and seed layers, respectively (see Fig. 2b–d). As a seed layer, Cu is popularly used due to its low cost and low electrical resistivity. However, the Cu layer has the disadvantages of surface oxidation and dissolution into the electrolyte based of sulfuric acid. Meanwhile, Au atoms may diffuse into the Si if a sufficient barrier layer is not supplied. The Au seed layer, however, has better stability than Cu layer in the electrolyte and good oxidation resistance. Therefore, for the feasibility study, the Au layer was selected as the seed layer, due to its advantages rather than direct practical
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Fig. 2. Cross-sections of a via with Ti/Au deposited layers; (a) whole via, (b) enlarged upper part, (c) enlarged middle part, and (d) enlarged bottom part.
application. The thicknesses of the functional layers, SiO2, Ti, and Au, exhibited inconsistency with the via depth. The thicknesses of the Ti and Au layers at the upper point (at a depth of 5 lm from the via opening) were confirmed to be 268 and 495 nm (see Fig. 2b), respectively, and 106 and 198 nm at the middle point (at a depth of 30 lm) (see Fig. 2c). At the lower point (at a depth of 50 lm), the Ti and Au thicknesses were 62 and 116 nm (Fig. 2d), respectively. The thickness of the SiO2 coated by HDP CVD was not clear in Fig. 2, but it was reported to decrease with increasing depth of the via in the author’s previous work [29]. The Ti/Au layer at the upper point was 4.3 times thicker than that at the lower point. The difference in the thickness of the functional layer can affect the subsequent Cu filling ratio into the via [33]. To improve the plating ratio of the bottom in the via, an additional process such as seed-layer enhancement [30,31] has generally been used. In electroplating, two factors are regarded as essential to influence the plating speed of Cu into the via hole. One factor is the current density change caused by the difference in the thickness of the seed layer. The other is the mass transport of copper ions in the electroplating solution [27,32–34]. The difference in the thickness of the seed layer results in a large difference in the electrical conductivity, which is related to the current density. Namely, the conductivity is inversely proportional to the resistance, and the resistance is related to the thickness of the seed layer. The via opening part is more conductive than the via bottom because the via opening has a thicker seed layer than the bottom, which results in a difference in the Cu plating speed in the via hole. A reason for the difference in the thickness of the Au seed layer according to the position in the via wall can be explained by different hitting probabilities of Au atoms during sputtering. The Au atoms drive straight to the via with random directions. In the straight via, the bottom part has less probability of being hit by the Au atoms than the via opening. By increasing the aspect ratio of the via, the probability further decreases at the via bottom and results in a thinner deposition layer. The average thicknesses of the Au seed layer deposited by sputtering in this study were 485, 200, and 115 nm at depths of 5, 30,
and 50 lm from the via opening, respectively. The sheet resistance (X/sq) of the Au layer can be calculated using the thickness of the metal film (t) and resistivity (X cm) at each point as follows. From the relationship between the thickness of the metal film and sheet resistance [35], the sheet resistance can be obtained by applying the already known resistivity and thickness of the metal film, as shown in Eq. (1) [36]. This is useful for a high purity material whose resistivity has already been known.
t ¼ q=Rs
ð1Þ
where t represents the sheet thickness (cm), q is the resistivity (X cm), and Rs is the sheet resistance (X/sq). The resistivity value of Au is 2.04 lX cm at 0 °C and 2.20 lX cm at 20 °C. Eq. (1) can be rewritten as Eq. (2)
Rs ¼ q=t
ð2Þ
From Eq. (2), the sheet resistance of Au at 20 °C, that is the same temperature as Cu electroplating, can be calculated using the measured Au layer thickness and resistivity value of 2.20 lX cm. For example, in the case of a via depth of 30 lm, the thickness of the seed layer was 200 nm. Thus, the sheet resistance can be calculated from Eq. (2), specifically, it is 2.20 lX cm (q) divided by 200 107 cm (t), and is therefore equal to 0.011 107 lX (namely, Rs; 110 mX in Fig. 3). In the calculation, the correction factor, which depends on the sample size, thickness and temperature, was not considered, because the sample size and temperature are fixed in this study. The calculated sheet resistance of the Au layer is illustrated in Fig. 3. In the figure, the sheet resistance at the top of the via is lower than that at the bottom. Specifically, the sheet resistance at a depth of 4 lm is only about 20% compared to that at a depth of 60 lm. Thus, under certain plating conditions, when the electroplating voltage is constant, the current density at the top of the via is relatively higher than that at the bottom. This situation will lead to a higher plating speed on the top compared to the deeper part of the via. Thus, void defects can be produced at the center of the Cu filling, which is caused by the rapid electroplating at the via opening [26].
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Fig. 3. Thickness of seed layer and sheet resistance vs. depth of via.
3.2. High-speed Cu filling
Fig. 5. Relationship between Cu filling ratio and electroplating time with different current waveforms, where Tb indicates the Cu thickness (lm) at the bottom, and Tw indicates the Cu thickness (lm) at the via wall.
In order to prevent via blocking due to rapid electro-deposition at the via opening, the plating rate around the via opening needs to be suppressed, while the plating at the via bottom should be activated. As a possible way to solve this problem, in the author’s previous study [26], the PPR current waveform was investigated, and it was effective to enhance the Cu filling speed without via blocking in the straight via. Namely, the via was fully filled by Cu at the average current density of 5.85 mA/cm2 for a plating time of 60 min. However, problems, such as a narrow process window and lower deposition ratio on average, still existed in the PPR waveform. For example, when the current density was lower than 5.85 mA/cm2, the filling ratio became quite low (average filling ratio: 78%) because of the slow plating speed. And when the
current density was higher than 5.85 mA/cm2, the incidence of defects became relatively high, due to the via blocking caused by the rapid electroplating around the via opening (average filling ratio: 90%). In this study, the 3-step PPR current waveform was designed to solve this problem and to increase the Cu filling ratio in a short time. The 3-step PPR waveform was composed as follows. The 1st step of PPR ensures that Cu is mainly plated on the via bottom using a low current density (for example, average current density of 1.24 mA/cm2). The 2nd step of PPR with a medium current density (e.g. 3.22 mA/cm2 on average) aims to achieve electrodeposition mostly at the middle part of the via where most of
Fig. 4. Cu filling into TSV by 3-step PPR current (current type II); (a) by 1st step, (b) by 2nd step, (c) by 3rd step (total plating time from 1st to 3rd; 80 min), and (d) interface between via wall.
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the voids are produced. The 3rd step fills the remaining part of the via by applying a higher current density (e.g. 9.89 mA/cm2 on average) (refer to Fig. 1c).
Fig. 4a–c shows the results of Cu filling at each step, and d shows the via interface between the Si chip and Cu filling after the completion of electroplating by the 3-step PPR. In Fig. 4a, the via was plated with Cu by the 1st step PPR and the Cu thickness on the via bottom (point s) was approximately 8.9 lm. This is 1.6 times thicker than the upper part (point r) which a thickness of around 5.6 lm. The Cu filling ratio in the via calculated by the commercial program, Carl Zeiss Zxiovision, was 22%. Fig. 4b shows the cross section of the via electroplated by the 1st and 2nd steps of PPR. As shown in Fig. 4b, the Cu was filled to the middle part of the via without via blocking around the via opening, and the calculated filling ratio was 72%. This indicates that Cu deposition on the via bottom using current control like the 3-step PPR gives as good result as the process of seed-layer enhancement [30,31] and the process of bottom-up filling [21–25] which uses multiple additives such as PEG, halide ions, and sulfur containing organic compounds. Fig. 4c shows the cross section of the Cu-filled via after completion of the 3-step PPR at 80 min. The Cu-filling exhibits a sound state without serious defects, such as voids or seams, created by via blocking. Fig. 4d shows the interface between the Cu filling and the via wall. Cu was plated along the curved Au layer on the scallop-shaped wall. In spite of the uneven thickness of the seed layers, as shown in Fig. 2, a serious defect at the interface between Cu and the seed layer was not found. Thus, the 3-step PPR process of Cu filling seems not to be significantly affected by the uneven thickness of the functional layers, Ti and Au, in the via wall. Generally, it takes quite a long time to achieve Cu-filling into a via, about 2.5–15 h [15,37]; in this study, however, a shorter filling time of about 80 min was confirmed by the application of the 3-step PPR process. Fig. 5 shows the comparison of the plating ratio according to the waveforms of the PR, PPR, and 3-step PPR with the plating time (see the waveform in Fig. 1). The plating ratio achieved by the PR process is very low, because plating was performed at a low current density (average current density of 1.24 mA/cm2) to prevent the blocking of the via at the via opening. Meanwhile, the plating ratios achieved by the PPR (average current density of 4.74 mA/ cm2) and 3-step PPR were quite high. The total plating times by the PPR [26] and 3-step PPR were 60 and 80 min, respectively. The PPR waveform gives a higher filling ratio (e.g., 37.35% at 40 min.) than the 3-step PPR (e.g., 22% at 40 min.) until 60 min. This is caused by the lower current density of the 1st step (1.24 mA/cm2) and 2nd step PPR (3.22 mA/cm2) than that of the PPR (4.74 mA/cm2). In the 3rd step, however, the current density of the 3-step PPR (9.89 mA/cm2) was higher than that of the PPR process and resulted in a higher filling ratio. Consequently, the 3-step PPR yielded more stable filling, namely full Cu-filling without defects. Table 1 Comparison of average filling ratios of vias for the different combinations of current density in the 3-step PPR and their individual current densities.
Fig. 6. Cu filling into TSV according to 3-step PPR current densities with (a) current combination type I, (b) current combination type III, and (c) current combination type IV (the numbers in each photo indicates current density of the 1st /2nd /3rd step, respectively).
Current type
Step
Average current density (mA/cm2)
Current type I
1st Step 2nd Step 3rd Step
1.24 3.22 8.78
92
Current type II
1st Step 2nd Step 3rd Step
1.24 3.22 9.89
100
Current type III
1st Step 2nd Step 3rd Step
1.24 4.33 8.78
91
Current type IV
1st Step 2nd Step 3rd Step
1.24 5.44 8.78
99
Filling ratio (%)
S.C. Hong et al. / Microelectronics Reliability 51 (2011) 2228–2235
3.3. Defects in Cu-filled Vias and non-destructive X-ray inspection Fig. 6 shows the defects produced by different combinations of current densities. Each current density and its corresponding filling ratio are summarized in Table 1. From Table 1, the optimal combination of current density which gave perfect Cu filling was current type II (see Fig. 4). Fig. 6a shows the result of plating using current type I. Comparing the current combination of type I to type II, the current densities of the 1st and 2nd steps were same, but that of the 3rd step of type I was lower (type I: 8.78; type II: 9.89 mA/cm2). Due to the lower current density of type I in the 3rd step, the Cu plating was not sufficient, and a seam was created around the top of the via. Fig. 6b and c are composed of higher current densities for the 2nd steps and lower current densities for the
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3rd steps compared with current type II, as shown in Table 1, respectively. In the case of Fig. 6b (current type III) and c (current type IV), a defect, like a seam, was still found inside the Cu filling, despite the higher current density of the 2nd step than that of current type I (Fig. 6a) and type II. This defect is considered to be caused by the low current density of the 3rd step. And the Cu filling ratio of 99% for current type IV was relatively higher than those of current types I and III, because the current density in the 2nd step was higher. The Cu filling ratio achieved by this 3-step PPR waveform (95.5% on average) was higher than that obtained by PPR (80% on average) [26], and most of the defects occurred not around the bottom of the via, but around the top. This characteristic of Cu-filling is similar to the bottom-up filling achieved by controlling the chemistry of the electrolyte [21–25].
Fig. 7. Images from X-ray inspection and FE-SEM for Cu fillings with and without defects: (a) cross-section of the via including a defect, (b) X-ray result including a defect, (c) magnified X-ray image of the defect, (d) cross-section of the via without defect, (e) X-ray result without defect, and (f) magnified X-ray image for the defect-free Cu-filling. Cu filled into via (a) by PPR current at 6.73 mA/cm2 for 60 min and (d) by 3-step PPR current type II for 80 min.
Fig. 8. Cu filling into via holes electroplated by 3-step PPR current waveform for 80 min.
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The non-destructive X-ray radiography test was applied to a Cufilled Si chip to observe the defects in the Cu fillings. Generally, destructive inspection by a microscope including SEM or optical microscopy has been used to find the defects from the cross-sections of the Cu fillings. However, with destructive methods, specimen cutting, grinding and polishing are required, and these processes can cause damage to a fragile Si-chip specimen. In the non-destructive X-ray test, defects can be identified by the difference in contrast between the defects and the filled part without damage to the thin chip. Fig. 7 shows the results obtained from the X-ray test and FESEM for the vias with and without defects. Fig. 7a and d show the FE-SEM images of the via cross-sections with and without defects, respectively. Fig. 7b and e show the results obtained from the X-ray tests, and c and f are the magnifications of images b and e, respectively. From Fig. 7b and c, it is clear that the presence of internal defects in TSV can be confirmed through the X-ray inspection. That is, the defects were identified as white spots due to the difference in contrast from the other parts. In Fig. 7e and f, difference in contrast does not exist, and only black is observed in the Xray images, which indicates the absence of defects, shown in the FE-SEM image of Fig. 7d. Fig. 8 presents the cross-sections of the Cu-filled vias without defects prepared by the 3-step PPR method for 80 min. Fig. 8b shows an enlarged portion of the via after complete filling, and the middle part (displayed as a broken line), which is slightly lower than the other Cu deposits, indicates that it is the last electrodeposited area after gradual filling from the via bottom. The Cu filling by the PPR process [26] is not bottom-up filling, but filling from all sides of the walls in the via simultaneously (see photos in Fig. 5), and it is easier to produce defects. Meanwhile, the 3-step PPR process in this study is composed of a combination of appropriate PPR waveforms in 3-steps to overcome the problem of via blocking before complete via filling. Thus, the Cu filling can be controlled as a bottom-up process by an optimal current waveform, which leads to sound via filling in a short time such as 80 min.
4. Conclusions The 3-step PPR (periodic pulse reverse) current waveform was suggested to reduce the Cu-filling time in a TSV (through-siliconvia) and to lower defects in the Cu filling. This method is applicable to Cu electroplating for 3-dimensional Si-chip stacking. The results are summarized as follows. 1. Full Cu filling into the TSV without defects was obtained by the 3-step PPR current waveform which was composed of current densities of 1.24, 3.22, and 9.89 mA/cm2 as the 1st, 2nd, and 3rd steps, respectively, by plating for 80 min. 2. The 1st, 2nd, and 3rd steps of the 3-step PPR process involve low, medium, and high current densities, respectively. The 1st step plays the role of plating Cu mainly on the via bottom, the 2nd filled Cu in the middle of the via, and the 3rd step plated Cu on the upper part of the via. A bottom-up filling process was established by the control of the current waveform. 3. The presence of defects, such as voids, created during the Cufilling, was confirmed by the non-destructive X-ray radiographic test, which can be helpful to ensure the reliability of a fragile thin Si wafer for 3D packaging. 4. The thickness of the Ti/Au layers around the via opening was 4.3 times larger than that around the via bottom. However, a serious defect at the interface between the via wall and Cu filled by the 3-step PPR was not found despite the uneven thickness of the seed layer.
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S.C. Hong et al. / Microelectronics Reliability 51 (2011) 2228–2235 [29] Jun JH, Kim IR, Mayer M, Zhou YN, Jung SB, Jung JP. A new non-PRM bumping process by electroplating on Si die for three dimensional packaging. Mater Trans 2010;51(10):1887–92. [30] Lee SW, Shi FG, Lopatin SD. New copper seed-layer enhancement process metrology for advanced dual-damascene interconnects. J Electron Mater 2003;32(04):272–7. [31] Lim JM, Lee CM. Enhancement of Cu nucleation in Cu-MOCVD by Pd sputtering pretreatment. Solid-State Electron 2001;45:2083–8. [32] Yang X, Ling H, Ding D, Li M, Yu X, Mao D. Through-silicon via filling process using pulse reversal plating. In: International conference on electronic packaging technology and high density packaging (ICEPT-HDP); 2009. [33] Zhang Y, Richardson T, Chung S, Wang C, Kim B, Rietmann C. Fast copper plating process for TSV fill, microsystems, packaging, assembly and circuits technology. IMPACT 2007. International; 2007. p. 219–22.
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Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Reduction of defects in TSV filled with Cu by high-speed 3-step PPR for 3D Si chip stacking Sung Chul Hong a, Wang Gu Lee a, Won Joong Kim a, Jong Hyeong Kim b, Jae Pil Jung a,⇑ a b
Dept. of Materials Sci. and Eng., University of Seoul, Seoul 130-743, Republic of Korea Seoul Nat’l University of Science & Technology, Seoul 139-743, Republic of Korea
a r t i c l e
i n f o
Article history: Received 30 March 2011 Received in revised form 24 June 2011 Accepted 27 June 2011 Available online 23 July 2011
a b s t r a c t The reduction of defects and high-speed copper filling into a through-silicon-via (TSV) for the threedimensional stacking of Si chips were investigated. The via, with a diameter and depth of 30 lm and 60 lm, respectively, was prepared on a Si wafer by a deep reactive ion etching (DRIE) process. SiO2, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a 3-step periodic-pulse-reverse (PPR) current waveform was suggested for electroplating. The 3-step PPR consisted of low, medium and high current densities for the 1st, 2nd and 3rd steps, respectively. After Cu filling, in order to estimate defects in the Cu-filling, the via was cross-sectioned and observed by field emission scanning electron microscopy (FE-SEM), and also an X-ray radiographic test was performed for non-destructive inspection. The experimental results showed the via was fully filled without a serious defect by the 3-step PPR process after 80 min of plating, specifically, by current densities of 1.24, 3.22, and 9.89 mA/cm2 (1st/2nd/3rd step, respectively). The 3-step PPR filling was a kind of bottom-up filling process of Cu into the via, and it was effective for Cu filling in a short time. Defects, like voids in the Cu-filled TSV, were identified by the X-ray radiographic test, which can be useful for ensuring the reliability of a fragile thin Si wafer for 3D packaging. Ó 2011 Elsevier Ltd. All rights reserved.
1. Introduction Recently, electronic devices tend to be light in weight, and have high performance with low power consumption and low prices. In order to satisfy this tendency, these devices require miniaturization with respect to their packaging technology [1]. Three-dimensional (3-D) chip stacking is a popular candidate to meet such miniaturization needs. It has the advantages of volume reduction compared to conventional planar chip arrays as well as reduction of their power consumption, due to its shorter conduction path between the stacked chips. However, 3-D chip packaging also has some problems, such as difficulty to identify the presence of tiny internal defects in the stacked chips, fast via formation, high-speed via filling with conductive material, the formation of uniform bumps, and mechanical and thermal issues caused by the chip thinning [2]. Therefore, studies on 3-D chip stacking are ongoing at various levels [3–9]. Among the various 3-D packaging technologies, the most promising one is through-silicon-via (TSV) technology [2,10]. 3-D packaging with TSV consists of via (TSV) formation, the filling of a conductive material into the via, wafer thinning, and chip stacking using a metal bump [11,12]. Cu electroplating is a commonly used process for via filling [13,14]. However, shortcomings of the Cu ⇑ Corresponding author. E-mail address: [email protected] (J.P. Jung). 0026-2714/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2011.06.031
electroplating are the very long process time, about 15 h, to fill the via [15], as well as the difficulty to get a fully filled via for a small via width or large aspect ratio. Thus, many studies have been conducted in an attempt to shorten the Cu-filling time with achieving fewer defects [16,17]. To reduce the Cu-filling time and defect ratio in electroplating, a pulse-reverse (PR) current waveform [16,18,19] modified from the pulse current [20] (see Fig. 1a) or the addition of inhibitors and accelerator to the plating solution has been reported [21–25]. However, the PR current waveform has a slow filling speed compared to the constant current waveform. Many studies have been performed about the addition of an inhibitor and accelerator, such as polyethylene glycol (PEG), halide ions, and sulfur-containing organic compounds, to the electrolyte to establish a bottom-up Cu filling process [21–25], which can reduce void defects in the Cufilled via. However, it is difficult to find the optimal combination of inhibitor and accelerator. The authors’ previous study [26] demonstrated that a periodicpulse-reverse (PPR) current waveform was useful for the high-speed filling of Cu into a straight via. The PPR waveform is characterized by the addition of a current-off duration after the oxidation current (i.e. prior to the reduction current) during electroplating (see Fig. 1b). However, the PPR current waveform is still not satisfactory in terms of its filling ratio, due to frequent defects caused by the non-bottomup Cu-filling.
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2. Experimental A h1 0 0i p-type Si wafer, having a diameter of 100 mm and thickness of 525 lm, was selected as the substrate. In order to produce via holes on the wafer surface, a photo resist (PR, model: AZ4620) was spin-coated with a thickness of 10 lm. A via array pattern with a 30 lm diameter and a 200 lm pitch was produced by exposing the PR to ultraviolet (UV) rays. Each wafer was composed of 240 chips with a size of 5 5 mm and 192 vias were prepared in each chip. Subsequently, the wafer was etched by the deep reactive ion etching (DRIE) method and cylindrical shaped vias were produced which had a diameter of 30 lm and depth of 60 lm. As an insulation layer, SiO2 was formed by high density plasma chemical vapor deposition (HDP CVD). Ti and Au layers were deposited by sputtering in the via wall as adhesion and seed layers, respectively. However, a barrier layer against the Au seed layer was not considered in order to simplify the Cu-filling process. The Si wafer was cut into chips by a diamond saw. The diced chip was used as the cathode for Cu filling by electroplating, and a Pt sheet (size; 10 10 0.3 mm) was used as the anode. The distance between the electrodes was 30 mm. The electroplating solution for Cu filling was composed of 103.08 g/L of CuSO45H2O, 32 ml/L of H2SO4, 0.24 ml/L of HCl, and 4 g/L of an additive. The chloride ion (HCl in this study) reduces the polarization of the anode and the sulfur containing organic (H2SO4 in this study) plays the role of an accelerator [27]. The additive used in this study was one of the suppressors studied by Mendez et al. [28]. The electrolyte in the plating bath was stirred continuously by a magnetic bar with a rotating speed of 200 rpm (revolutions per minute), and the electrolyte was kept at room temperature during electroplating. A commercial pulse-plating unit (EPP-4000 from Princeton Applied Research) was used as a power supply for the electroplating. The reference electrode was a standard calomel electrode (SCE). The current waveform of the 3-step PPR was applied to the cathode of the Si chip for electroplating. The 3-step PPR consisted of a low current density duration (1st step), medium current density duration (2nd step), and high current density duration (3rd step) (see Fig. 1c). The Cu-filled via was examined by field emission scanning electron microscopy (FE-SEM) to investigate the filling ratio of the vias. Using the FE-SEM images, the Cu-filled area was measured by the Carl Zeiss Axiovision program. The Cu filling ratio was calculated according to the relation [(Cu filled area in the via/via area) 100%] [26]. Non-destructive inspection by the X-ray radiographic test was applied to the Cu-filled vias to check for the presence of defects such as voids.
3. Results and discussion 3.1. Functional layers
Fig. 1. Current waveform of pulse-reverse (PR); (a), periodic pulse reverse (PPR) current, (b) [26], and 3-step PPR current methods (c) for Cu filling into a via.
In this study, the 3-step PPR current waveform was suggested to reduce defects in the Cu filling of the via and to increase the via filling speed by establishing a bottom-up Cu-filling process. The X-ray radiographic test was also employed for the non-destructive inspection of the defects in Cu filling. However, the issue of the high aspect ratio of the via was not considered, because the purpose of this study was to confirm if the bottom-up process could be successfully achieved by optimizing the current waveform.
Before Cu filling into the via, functional layers consisting of dielectric, adhesion, and seed layers were coated on the via wall. Fig. 2a shows a cross-section view of the via hole fabricated by DRIE on a Si wafer which has a depth of 60 lm and a diameter of 30 lm. On the via wall, Ti and Au layers were found as adhesion and seed layers, respectively (see Fig. 2b–d). As a seed layer, Cu is popularly used due to its low cost and low electrical resistivity. However, the Cu layer has the disadvantages of surface oxidation and dissolution into the electrolyte based of sulfuric acid. Meanwhile, Au atoms may diffuse into the Si if a sufficient barrier layer is not supplied. The Au seed layer, however, has better stability than Cu layer in the electrolyte and good oxidation resistance. Therefore, for the feasibility study, the Au layer was selected as the seed layer, due to its advantages rather than direct practical
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Fig. 2. Cross-sections of a via with Ti/Au deposited layers; (a) whole via, (b) enlarged upper part, (c) enlarged middle part, and (d) enlarged bottom part.
application. The thicknesses of the functional layers, SiO2, Ti, and Au, exhibited inconsistency with the via depth. The thicknesses of the Ti and Au layers at the upper point (at a depth of 5 lm from the via opening) were confirmed to be 268 and 495 nm (see Fig. 2b), respectively, and 106 and 198 nm at the middle point (at a depth of 30 lm) (see Fig. 2c). At the lower point (at a depth of 50 lm), the Ti and Au thicknesses were 62 and 116 nm (Fig. 2d), respectively. The thickness of the SiO2 coated by HDP CVD was not clear in Fig. 2, but it was reported to decrease with increasing depth of the via in the author’s previous work [29]. The Ti/Au layer at the upper point was 4.3 times thicker than that at the lower point. The difference in the thickness of the functional layer can affect the subsequent Cu filling ratio into the via [33]. To improve the plating ratio of the bottom in the via, an additional process such as seed-layer enhancement [30,31] has generally been used. In electroplating, two factors are regarded as essential to influence the plating speed of Cu into the via hole. One factor is the current density change caused by the difference in the thickness of the seed layer. The other is the mass transport of copper ions in the electroplating solution [27,32–34]. The difference in the thickness of the seed layer results in a large difference in the electrical conductivity, which is related to the current density. Namely, the conductivity is inversely proportional to the resistance, and the resistance is related to the thickness of the seed layer. The via opening part is more conductive than the via bottom because the via opening has a thicker seed layer than the bottom, which results in a difference in the Cu plating speed in the via hole. A reason for the difference in the thickness of the Au seed layer according to the position in the via wall can be explained by different hitting probabilities of Au atoms during sputtering. The Au atoms drive straight to the via with random directions. In the straight via, the bottom part has less probability of being hit by the Au atoms than the via opening. By increasing the aspect ratio of the via, the probability further decreases at the via bottom and results in a thinner deposition layer. The average thicknesses of the Au seed layer deposited by sputtering in this study were 485, 200, and 115 nm at depths of 5, 30,
and 50 lm from the via opening, respectively. The sheet resistance (X/sq) of the Au layer can be calculated using the thickness of the metal film (t) and resistivity (X cm) at each point as follows. From the relationship between the thickness of the metal film and sheet resistance [35], the sheet resistance can be obtained by applying the already known resistivity and thickness of the metal film, as shown in Eq. (1) [36]. This is useful for a high purity material whose resistivity has already been known.
t ¼ q=Rs
ð1Þ
where t represents the sheet thickness (cm), q is the resistivity (X cm), and Rs is the sheet resistance (X/sq). The resistivity value of Au is 2.04 lX cm at 0 °C and 2.20 lX cm at 20 °C. Eq. (1) can be rewritten as Eq. (2)
Rs ¼ q=t
ð2Þ
From Eq. (2), the sheet resistance of Au at 20 °C, that is the same temperature as Cu electroplating, can be calculated using the measured Au layer thickness and resistivity value of 2.20 lX cm. For example, in the case of a via depth of 30 lm, the thickness of the seed layer was 200 nm. Thus, the sheet resistance can be calculated from Eq. (2), specifically, it is 2.20 lX cm (q) divided by 200 107 cm (t), and is therefore equal to 0.011 107 lX (namely, Rs; 110 mX in Fig. 3). In the calculation, the correction factor, which depends on the sample size, thickness and temperature, was not considered, because the sample size and temperature are fixed in this study. The calculated sheet resistance of the Au layer is illustrated in Fig. 3. In the figure, the sheet resistance at the top of the via is lower than that at the bottom. Specifically, the sheet resistance at a depth of 4 lm is only about 20% compared to that at a depth of 60 lm. Thus, under certain plating conditions, when the electroplating voltage is constant, the current density at the top of the via is relatively higher than that at the bottom. This situation will lead to a higher plating speed on the top compared to the deeper part of the via. Thus, void defects can be produced at the center of the Cu filling, which is caused by the rapid electroplating at the via opening [26].
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Fig. 3. Thickness of seed layer and sheet resistance vs. depth of via.
3.2. High-speed Cu filling
Fig. 5. Relationship between Cu filling ratio and electroplating time with different current waveforms, where Tb indicates the Cu thickness (lm) at the bottom, and Tw indicates the Cu thickness (lm) at the via wall.
In order to prevent via blocking due to rapid electro-deposition at the via opening, the plating rate around the via opening needs to be suppressed, while the plating at the via bottom should be activated. As a possible way to solve this problem, in the author’s previous study [26], the PPR current waveform was investigated, and it was effective to enhance the Cu filling speed without via blocking in the straight via. Namely, the via was fully filled by Cu at the average current density of 5.85 mA/cm2 for a plating time of 60 min. However, problems, such as a narrow process window and lower deposition ratio on average, still existed in the PPR waveform. For example, when the current density was lower than 5.85 mA/cm2, the filling ratio became quite low (average filling ratio: 78%) because of the slow plating speed. And when the
current density was higher than 5.85 mA/cm2, the incidence of defects became relatively high, due to the via blocking caused by the rapid electroplating around the via opening (average filling ratio: 90%). In this study, the 3-step PPR current waveform was designed to solve this problem and to increase the Cu filling ratio in a short time. The 3-step PPR waveform was composed as follows. The 1st step of PPR ensures that Cu is mainly plated on the via bottom using a low current density (for example, average current density of 1.24 mA/cm2). The 2nd step of PPR with a medium current density (e.g. 3.22 mA/cm2 on average) aims to achieve electrodeposition mostly at the middle part of the via where most of
Fig. 4. Cu filling into TSV by 3-step PPR current (current type II); (a) by 1st step, (b) by 2nd step, (c) by 3rd step (total plating time from 1st to 3rd; 80 min), and (d) interface between via wall.
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the voids are produced. The 3rd step fills the remaining part of the via by applying a higher current density (e.g. 9.89 mA/cm2 on average) (refer to Fig. 1c).
Fig. 4a–c shows the results of Cu filling at each step, and d shows the via interface between the Si chip and Cu filling after the completion of electroplating by the 3-step PPR. In Fig. 4a, the via was plated with Cu by the 1st step PPR and the Cu thickness on the via bottom (point s) was approximately 8.9 lm. This is 1.6 times thicker than the upper part (point r) which a thickness of around 5.6 lm. The Cu filling ratio in the via calculated by the commercial program, Carl Zeiss Zxiovision, was 22%. Fig. 4b shows the cross section of the via electroplated by the 1st and 2nd steps of PPR. As shown in Fig. 4b, the Cu was filled to the middle part of the via without via blocking around the via opening, and the calculated filling ratio was 72%. This indicates that Cu deposition on the via bottom using current control like the 3-step PPR gives as good result as the process of seed-layer enhancement [30,31] and the process of bottom-up filling [21–25] which uses multiple additives such as PEG, halide ions, and sulfur containing organic compounds. Fig. 4c shows the cross section of the Cu-filled via after completion of the 3-step PPR at 80 min. The Cu-filling exhibits a sound state without serious defects, such as voids or seams, created by via blocking. Fig. 4d shows the interface between the Cu filling and the via wall. Cu was plated along the curved Au layer on the scallop-shaped wall. In spite of the uneven thickness of the seed layers, as shown in Fig. 2, a serious defect at the interface between Cu and the seed layer was not found. Thus, the 3-step PPR process of Cu filling seems not to be significantly affected by the uneven thickness of the functional layers, Ti and Au, in the via wall. Generally, it takes quite a long time to achieve Cu-filling into a via, about 2.5–15 h [15,37]; in this study, however, a shorter filling time of about 80 min was confirmed by the application of the 3-step PPR process. Fig. 5 shows the comparison of the plating ratio according to the waveforms of the PR, PPR, and 3-step PPR with the plating time (see the waveform in Fig. 1). The plating ratio achieved by the PR process is very low, because plating was performed at a low current density (average current density of 1.24 mA/cm2) to prevent the blocking of the via at the via opening. Meanwhile, the plating ratios achieved by the PPR (average current density of 4.74 mA/ cm2) and 3-step PPR were quite high. The total plating times by the PPR [26] and 3-step PPR were 60 and 80 min, respectively. The PPR waveform gives a higher filling ratio (e.g., 37.35% at 40 min.) than the 3-step PPR (e.g., 22% at 40 min.) until 60 min. This is caused by the lower current density of the 1st step (1.24 mA/cm2) and 2nd step PPR (3.22 mA/cm2) than that of the PPR (4.74 mA/cm2). In the 3rd step, however, the current density of the 3-step PPR (9.89 mA/cm2) was higher than that of the PPR process and resulted in a higher filling ratio. Consequently, the 3-step PPR yielded more stable filling, namely full Cu-filling without defects. Table 1 Comparison of average filling ratios of vias for the different combinations of current density in the 3-step PPR and their individual current densities.
Fig. 6. Cu filling into TSV according to 3-step PPR current densities with (a) current combination type I, (b) current combination type III, and (c) current combination type IV (the numbers in each photo indicates current density of the 1st /2nd /3rd step, respectively).
Current type
Step
Average current density (mA/cm2)
Current type I
1st Step 2nd Step 3rd Step
1.24 3.22 8.78
92
Current type II
1st Step 2nd Step 3rd Step
1.24 3.22 9.89
100
Current type III
1st Step 2nd Step 3rd Step
1.24 4.33 8.78
91
Current type IV
1st Step 2nd Step 3rd Step
1.24 5.44 8.78
99
Filling ratio (%)
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3.3. Defects in Cu-filled Vias and non-destructive X-ray inspection Fig. 6 shows the defects produced by different combinations of current densities. Each current density and its corresponding filling ratio are summarized in Table 1. From Table 1, the optimal combination of current density which gave perfect Cu filling was current type II (see Fig. 4). Fig. 6a shows the result of plating using current type I. Comparing the current combination of type I to type II, the current densities of the 1st and 2nd steps were same, but that of the 3rd step of type I was lower (type I: 8.78; type II: 9.89 mA/cm2). Due to the lower current density of type I in the 3rd step, the Cu plating was not sufficient, and a seam was created around the top of the via. Fig. 6b and c are composed of higher current densities for the 2nd steps and lower current densities for the
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3rd steps compared with current type II, as shown in Table 1, respectively. In the case of Fig. 6b (current type III) and c (current type IV), a defect, like a seam, was still found inside the Cu filling, despite the higher current density of the 2nd step than that of current type I (Fig. 6a) and type II. This defect is considered to be caused by the low current density of the 3rd step. And the Cu filling ratio of 99% for current type IV was relatively higher than those of current types I and III, because the current density in the 2nd step was higher. The Cu filling ratio achieved by this 3-step PPR waveform (95.5% on average) was higher than that obtained by PPR (80% on average) [26], and most of the defects occurred not around the bottom of the via, but around the top. This characteristic of Cu-filling is similar to the bottom-up filling achieved by controlling the chemistry of the electrolyte [21–25].
Fig. 7. Images from X-ray inspection and FE-SEM for Cu fillings with and without defects: (a) cross-section of the via including a defect, (b) X-ray result including a defect, (c) magnified X-ray image of the defect, (d) cross-section of the via without defect, (e) X-ray result without defect, and (f) magnified X-ray image for the defect-free Cu-filling. Cu filled into via (a) by PPR current at 6.73 mA/cm2 for 60 min and (d) by 3-step PPR current type II for 80 min.
Fig. 8. Cu filling into via holes electroplated by 3-step PPR current waveform for 80 min.
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The non-destructive X-ray radiography test was applied to a Cufilled Si chip to observe the defects in the Cu fillings. Generally, destructive inspection by a microscope including SEM or optical microscopy has been used to find the defects from the cross-sections of the Cu fillings. However, with destructive methods, specimen cutting, grinding and polishing are required, and these processes can cause damage to a fragile Si-chip specimen. In the non-destructive X-ray test, defects can be identified by the difference in contrast between the defects and the filled part without damage to the thin chip. Fig. 7 shows the results obtained from the X-ray test and FESEM for the vias with and without defects. Fig. 7a and d show the FE-SEM images of the via cross-sections with and without defects, respectively. Fig. 7b and e show the results obtained from the X-ray tests, and c and f are the magnifications of images b and e, respectively. From Fig. 7b and c, it is clear that the presence of internal defects in TSV can be confirmed through the X-ray inspection. That is, the defects were identified as white spots due to the difference in contrast from the other parts. In Fig. 7e and f, difference in contrast does not exist, and only black is observed in the Xray images, which indicates the absence of defects, shown in the FE-SEM image of Fig. 7d. Fig. 8 presents the cross-sections of the Cu-filled vias without defects prepared by the 3-step PPR method for 80 min. Fig. 8b shows an enlarged portion of the via after complete filling, and the middle part (displayed as a broken line), which is slightly lower than the other Cu deposits, indicates that it is the last electrodeposited area after gradual filling from the via bottom. The Cu filling by the PPR process [26] is not bottom-up filling, but filling from all sides of the walls in the via simultaneously (see photos in Fig. 5), and it is easier to produce defects. Meanwhile, the 3-step PPR process in this study is composed of a combination of appropriate PPR waveforms in 3-steps to overcome the problem of via blocking before complete via filling. Thus, the Cu filling can be controlled as a bottom-up process by an optimal current waveform, which leads to sound via filling in a short time such as 80 min.
4. Conclusions The 3-step PPR (periodic pulse reverse) current waveform was suggested to reduce the Cu-filling time in a TSV (through-siliconvia) and to lower defects in the Cu filling. This method is applicable to Cu electroplating for 3-dimensional Si-chip stacking. The results are summarized as follows. 1. Full Cu filling into the TSV without defects was obtained by the 3-step PPR current waveform which was composed of current densities of 1.24, 3.22, and 9.89 mA/cm2 as the 1st, 2nd, and 3rd steps, respectively, by plating for 80 min. 2. The 1st, 2nd, and 3rd steps of the 3-step PPR process involve low, medium, and high current densities, respectively. The 1st step plays the role of plating Cu mainly on the via bottom, the 2nd filled Cu in the middle of the via, and the 3rd step plated Cu on the upper part of the via. A bottom-up filling process was established by the control of the current waveform. 3. The presence of defects, such as voids, created during the Cufilling, was confirmed by the non-destructive X-ray radiographic test, which can be helpful to ensure the reliability of a fragile thin Si wafer for 3D packaging. 4. The thickness of the Ti/Au layers around the via opening was 4.3 times larger than that around the via bottom. However, a serious defect at the interface between the via wall and Cu filled by the 3-step PPR was not found despite the uneven thickness of the seed layer.
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