Reliability improvement of aluminium-based contact and interconnect systems for VLSI applications by grain structure modification

Microelectronic Engineering 18 (1992) 327-331 Elsevier

327

Reliability improvement of aluminium-based contact and interconnect systems for VLSI applications by grain structure modification T. Streil, B. Sauer, K. Frommhagen, Ch. Kunath, P. Huebler and M. Kotzerke Fraunhofer Institut fiir Mikroelektronische Schaltungen und Systeme, 0-8080 Dresden, Germany Received October 27, 1991 Accepted July 15, 1992

Abstract. The reliability of narrow aluminium-based metal lines has become an essential factor in very large scale integration integrated circuits (VLSI ICs). After theoretical considerations, a new developed experimental procedure is presented. This so-called cold deposition with immediate in-situ annealing leads to a modified metal system of high reliability, resulting in enhancement of the lifetime. Mechanical stress and electromigration as driving forces for void formation are examined. It is shown how an intentional change of Al-alloy microstructure significantly improves metallization reliability. Keywords. Reliability improvement, multilevel VLSI aluminium metallization, in-situ rapid thermal annealing, stress relaxation, electromigration.

1. Introduction

Highly reliable multilevel VLSI metallization schemes in the range of 1 lzm require a great electromigration resistance in combination with a minimized or prevented hillock formation. It is known that grain structure as well as the use of different aluminium alloys (e.g. A1/Si or A1/Si/Cu) significantly influences the contact and interconnect system reliability.

Correspondence to: T. Streil, Fraunhofer Institut f/Jr Mikroelektronische Schaltungen und Systeme, Institutsteil Dresden, Grenzstral~e 28, 0-8080 Dresden, Germany. 0167-9317/92/$05.00 © 1992 Elsevier Science Publishers B.V. All fights reserved

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2. Concept Most failures in AI/Si and AI/Si/Cu interconnects are caused by stressinduced void formation resulting in open-circuit failures. We can distinguish two major driving forces for void formation-mass transport induced by mechanical stress and by electromigration. Consequently a direct relation to Al-alloy film structure and top passivation exists. After Groothuis and Schroen [1] void formation depends on the vacancy concentration (which is a function of temperature) and on the vacancy diffusion velocity. Considering these facts, increased reliability should be achieved by the following measures: -Deposition and annealing conditions in combination with the vertical layer structure of the intermediate insulator and top passivation must be optimized. - The medium grain size in interconnect metallization lines must be enlarged so as to minimize the role of grain boundary diffusion (activation energy 0.4=0.5 eV). As the interconnects become narrower and thinner and as the mean grain size of the Al-alloy becomes larger, fewer grain boundaries will run parallel to the interconnection line (longitudinal). Thus bulk diffusion with significant higher activation energy (about 1.4eV) will become dominant. - T h e addition of at least 0.2% copper to AISi causes a trapping of vacancies inside the grain (and at the grain boundary) by Cu atoms. For that reason the lateral diffusion coefficient is dramatically reduced [2].

3. Experimental I.

'A1Si(lwt%) and AISi(lwt%)/Cu(0.5wt%) films of 800 nm thickness were sputter-deposited at room temperature. Grains of 0.5-0.6 Ixm and 0.2-0.3 ~m medium size, respectively, were grown. One possibility to enlarge the grain dimensions is by deposition on a hot substrate. An insufficient step coverage of this method was shown by Pramanik and Saxena [3]. Another way is to anneal the deposited A1 after metal patterning. Generally a strong hillock formation accompanies the furnace annealing. In our process the A1 film is sputtered on a substrate held at room temperature. This is followed by a rapid thermal processing step without leaving the vacuum (UHV) environment (so called in-situ procedure). Normally, the heater in a second deposition chamber of the sputtering machine is used to heat up the metallized wafer up to 623-723 K with heating rates in the range off 2 - 2 0 K / s . After holding at this high temperature level for 30-240 s, the substrate is quickly cooled down by moving the wafer from the heater into the next U H V chamber. Metal patterning takes place after this complete thermal treatment. Optimal conditions in relation to electromigration strength of the patterned interconnection lines and hillock growth induced by thermal stress during the post-metallization process steps are achieved with a upper level between 673

T. Streil et al. I Reliability o f Al-based contact systems

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and 723 K, plateau holding times of 70 s and heating rates of 5 K/s. This "cold" deposition with immediate in-situ annealing leads to lower Si(Cu) precipitates while achieving the same grain size as obtained by hot deposition. Furthermore a better step coverage and tighter grain boundaries (smaller tendency for slit-void formation) are observed.

4. Stress and stress relaxation

The internal stress in the vacuum-deposition metallization layers has been determined by X-ray diffraction. The stress o- of the AI film can be deduced from the wafer curvature before and after metal deposition. For the curvature measurement, a special stress-free wafer support is necessary. If the curvature K is known, the biaxial film stress or is given by o- -

EKs 2 (1)

6 ( 1 - v)h '

where E is Young's modulus for single crystalline silicon, v is Poisson's ratio for Si, s is the thickness of the wafer (substrate) and h is the thickness of the film. Figure 1 shows the stress behaviour of A1SiCu over a timespan of about 3 months. The relaxation profile depends on the metal history. Cold-deposited A1SiCu exhibits a stronger relaxation compared to in-situ annealed A1SiCu. After patterning, this relaxation process promotes slit-void formation in the metal conducting lines. In-situ rapid annealing reduces the relaxation phenomena, leading to higher metal reliability.

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time [ in days ] Fig. 1. Stress relaxation in AISiCu metallization.

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T. Streil et al. / Reliability o f Al-based contact systems

The lowering of internal stress of this alloy results from a lowering of the plastic strain of the metal film. Deviations from an exponential decrease of stress are caused by segregation processes inside the alloy.

5. Electromigration The following electrical characterization and test procedures have been developed to predict the reliability of the metal films: - D C electromigration stress (I > 107 A / c m 2, T = 50°C); - A C electromigration stress (used for elimination of temperature gradients in interconnection lines); - D C electromigration stress (I < 5 x 106 A / c m 2, T = 125, 150, 175°C); - m o d i f i e d BEM method; -temperature stress (125°C and 175°C for longer than 1000 h). Figure 2 shows the influence of the film structure for the A l / S i ( l w t % ) and Al/Si(lwt%)/Cu(O.5wt.%) metallization systems on the electromigration resistance. The following top passivations have been used: - LP = 1500 nm 420°C LP-PSG; - A P / L P = 300 nm 410°C AP-PSG + 1200 nm 420°C LP-PSG. In-situ annealing allows modification of the A1 alloy grain size over a wide range. Using the Leyboldt ZV 4000 machine, process temperatures in the range from 275 to 375°C yield grain sizes between 1.4---0.2 Ixm and 3.8 ± 1.0 ixm. Other test methods have given comparable reliability results (see Table 1).

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(T=50°C) Fig. 2. Electromigration resistance of different metallization systems (12 ixm linewidth, 2000 p.m length. I = 5 x 106 A/cm2).

T. Streil et al. / Reliability of Al-based contact systems

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Table 1 Reliability results of different metallization systems Alloy

Conditions

Failure rate Aa

A1/Si AI/Si AI/Si/Cu AI/Si/Cu

RT + Ar implantation in situ 275°C RT in situ 330°C

4x <5 x <5 x <5 x

10 -6 10 -s 10 -s 10 -8

6. Conclusion T h r e e d e v i c e t y p e test p r o c e d u r e s o f the p r e s e n t p r o d u c t i o n t e c h n o l o g y ( i n c l u d i n g in-situ a n n e a l i n g A1Si 275°C + A P / L P - P S G top passivation) f o r a 1MdRAM have indicated the absence of contact and interconnect scheme failures. T h i s leads to a life-time failure r a t e o f h B < 3 x 10 -7. T h e s a m e tests as d e s c r i b e d a b o v e a p p l i e d to A I S i C u i n t e r c o n n e c t s i n d i c a t e a failure r a t e l o w e r t h a n 1 x 10 -7. T h e results o f d e v i c e t y p e tests as well as the e l e c t r o m i g r a t i o n r e s i s t a n c e tests (Fig. 2) s h o w t h a t an i n t e n t i o n a l c h a n g e o f the A1 s t r u c t u r e can result in significant i m p r o v e m e n t o f m e t a l l i z a t i o n a n d c o n s e q u e n t l y d e v i c e reliability.

References [1] S.K. Groothuis and W.H. Schroen, Stress-related failures causing open metallization, I E E E Int. Reliability Physics Symp., 1988, pp. 1-8. [2] S. Mayuimi, T. Umemoto, M. Shishino, H. Nanatsue, S. Ueda and M. Inoue, The effect of Cu addition to AI-Si interconnects on the stress-induced open-circuit failures, I E E E Int. Reliability Physics Symp., 1988, pp. 15-21. [3] D. Pramanik and A.N. Saxena, Aluminium metallization for VLSI, Solid State Technol. 3 (1990) 73-79.