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Reliability of chemically vapor deposited (CVD) copper interconnections
MATERIALS CHEM;STRTR$dD Materials Chemistry and Physics 4 1 ( 1995) 229-233
ELSEVIER
Review
Reliability of chemically vapor deposited (CVD) copper interconnections S. Simon Wong, James S. Cho, Ho-kyu Kang, Changsup Ryu Centerfor
Integrated Systems, Stanford University, Stanford, CA 94305, USA
Received 5 January 1995; accepted 25 January 1995
Abstract The reliability issues of chemically vapor deposited copper interconnections for applications in integrated circuits are discussed. The voidfree conformal deposition of copper films into high aspect ratio trenches and via holes is demonstrated. The effectiveness of various dielectrics and metals as diffusion and drift barriers is compared. The electromigration properties of different copper interconnection structures and the
dependence on microstructures, current densities and temperatures are evaluated. Keywords:
Reliability; Copper interconnections; Chemically vapor deposited copper interconnections
1. Introduction Copper (Cu), which has a high conductivity, is a promising metal for future integrated circuits. Cu is also expected to provide improved reliability. This paper will describe the components that are needed for a reliable Cu interconnection technology.
0.005 has been estimated. Simulation results, as illustrated in Fig. 3, predict that conformal coverage can be obtained in trenches with an aspect ratio as high as 4. The sticking coefficient does not depend strongly on the deposition pressure, but increases for deposition temperatures higher than 150 “C, as summarized in Fig. 4. This also coincides with an increase in the film resistivity. These results indicate that surface reaction and impurity incorporation become more significant at high deposition temperatures.
2. Step coverage of CVD Cu films Owing to the difficulty of dry etching Cu, the most promising method for implementing Cu interconnections is to form a planarized buried structure [ 1,2]. As illustrated in Fig. 1, this process circumvents the etching problem by defining the interconnections with trenches that are etched into a dielectric layer. After Cu is deposited to overfill the trenches, the excess metal is removed by chemo-mechanical polishing. This also leaves a fully planarized structure in which the interconnection is buried in the dielectric. To ensure the reliability of these buried interconnections, voids must not be allowed to form during the deposition process and hence good conformality is essential. A cantilever test structure, as shown in Fig. 2, was used to investigate the conformality of the deposition process, and the resulting profile was modeled with SPEEDIE to determine a sticking coefficient [ 31. With the metal organic precursor Cuf (tmvs) (hfac) [4], excellent conformality of the Cu films has been observed and a sticking coefficient as low as 0254-0584/95/$09.50 0 1995 Elsevier Science S.A. All rights reserved SSDIO254-0584(95)01526-Z
3. Diffusion and drift barriers Cu is a deep level acceptor in Si. The presence of Cu will degrade carrier lifetimes and cause excessive leakage currents. Metal and dielectric barriers will be needed to ensure that Cu does not reach active devices. To evaluate the effectiveness of TiW as a diffusion barrier, n + lp diodes with a 250 nm deep junction, as shown in Fig. 5, were fabricated. Diodes with only TiW and diodes without TiW were also fabricated as controls. Various thicknesses of TiW, 100, 50 and 25 nm, were studied. The diodes were annealed at 450 or 500 “C in a vacuum ambient for 30 min. Diodes with an area as large as 0.1 X 0.1 cm and a perimeter as long as 100 cm were tested. Leakage currents at a reverse bias of 5 V were collected using an automated tester. No additional leakage currents were observed in the perimeter intensive diodes. The results for the largest area diodes are summarized in the histograms presented in Fig. 6. The TiW-
230
S.S. Wang et al. /Materials
Chemistry and Physics 41 (1995) 229-233
(a)
Substrate
(b)
Substrate
Fig. 1. Process sequence for forming buried Cu interconnections.
.
Silicon
.
.._ . ..
Fig. 2. Cantilever test structure for studying the conformality
of CVD Cu.
Cu diffuses into Si and significantly degrades the leakage characteristic. TiW is an excellent diffusion barrier even up to 500 “C. However, for the 25 nm thick TiW, there are some occurrences of excessive leakage after an anneal at 500 “C, which may be related to defects in the TiW layer. Our previous work has confirmed that Cu does not diffuse through most dielectrics [5]. To investigate the drift characteristics of positively charged Cu ions through dielectrics [6], capacitors were fabricated on n-type Si wafers with about 150 nm of various dielectrics on top of 50 nm of thermal oxide. The thin thermal oxide was grown to ensure a good interface between the dielectric and Si. CVD Cu was deposited and patterned to form the top electrodes. The 0.1 X 0.1 cm capacitors were then subjected to biased temperature stressing with a d.c. bias ranging from - 10 to + 20 V for 1 h at 250 “C. This experiment was performed in a nitrogen box to prevent oxidation of the Cu. The high frequency C-V characteristics of the capacitors were then measured after the stressing, and the results are summarized in Fig. 7. Both LTO and PSG show significant shifts in the threshold voltage due to the drift of Cu ions through the dielectric. PECVD oxynitride has a very small amount of threshold shift. CVD nitride shows no shift. Fig. 8 gives the results of SIMS analysis performed on the LTO and PECVD oxynitride samples, which confirm that a significant amount of Cu ions has drifted through LTO and accumulated at the dielectric-Si interface, whereas no significant amount of Cu ions is present in the PECVD oxynitride. The drift behavior of Cu ions through PECVD oxynitride has been studied thoroughly. Fig. 9 summarizes the shift in threshold voltage under a constant field of 1 MV cm- ’ as a function of the stress temperature and time. There is an initial rapid change in the threshold voltage which saturates at about 1.3 V. This shift is believed to be due to alkaline ions, as no special precautions were taken to minimize ionic contamin; .on during the patterning and etching of the Cu electrodes. T. : shift is saturated once all the alkaline ions have accur’ Jlated at the dielectric4 interface. The slower shift in
0
00 IO0
125
150
175
200
0
Temperature('Cl
0
0.2 0.4 06
0.8
Fig. 4. Sticking coefficient as a function of the deposition
conditions
Fig. 3. Simulated step coverage ofCVD Cu film in deep trenches with various aspect ratios; sticking coefficient 0.005.
only diodes confirm that low leakage currents are obtained ( < 10 nA cm-’ on average) without Cu. Without a barrier,
Fig. 5. Diode test .xrvcture :‘or evaluating
1.0 1.2
Pressure(Torr)
the barrier metal
S.S. Wang et al. /Materials
Chemistry and Physics 41 (1995) 229-233
231
Cull00
Leakage
Current
Leakage
(A)
Current
Leakage
(A)
nm TiW
Current
(A)
z
x G/50
I50
a
nm TiW
Cu/25
nm TiW
-6 100 $ 5 z
50 n
l~~1210~lo
Leakage
Current
03
(A)
Leakage
Fig. 6. Histograms
(a)
1o-6
Current
lo-4
,~-1210-lo
(8)
(A)
,150 8 BICXJ .d Y ma 50 u
m 0-30
IO
5v
-10
PSG 4% -20 -10 0 Voltage (V)
@cl :: 5 loo .s 0 P 50 u -20 -10 0 Voltage (V)
Fig. 7. C-V characteristics biased temperature stress.
Current
X
10~4 0)
(A)
Leakage
IO
of Cu capacitors
with various dielectrics
after
threshold voltage at longer stress times is due to the Cu ions. This shift will not saturate, as there is an essentially unlimited supply of Cu ions. The shift can be extrapolated to determine the reliability under normal operation conditions, Fig. 10 shows that even under a high constant field of 1 MV cm- ’
Various Cu interconnection structures, as illustrated in Fig. 11, including Cu/SiOz, Cu/TiW, TiW/Cu/TiW, selectiveW/Cu/TiW, SiO,/Cu/TiW, and a buried CulTiW by chemo-mechanical polishing were prepared, and their electromigration properties were compared under d.c. stress conditions [ 71. 100 nm thick thermal oxide was grown and 500 nm thick CVD Cu was deposited either on a sputtered TiW seed layer (100 nm) or directly on thermal oxide. Cu film was then patterned and wet etched (Fig. 11 (a), (b)). Some of the samples were annealed at 400 “C for 1 h to achieve larger grains (Fig. 11 (c) ). On some wafers, 100 nm thick TiW was sputtered on the Cu before patterning and etching (Fig. 11 (d) ) to study the effect of a capping metal on the lifetime. 80 nm thick selective LPCVD W was also deposited as a
G- 10‘9 1ol8
.s ‘J $
10’7
B B
,016
3 10 I5
.”
(A)
reliability
106
E =
Current
0.1 cm diodes
4. Electromigration
IO
200
0 -30
Leakage
,O~f’
at 125 “C for 10 years, there will be less than 10’” cm-’ Cu ions that have drifted through the PECVD oxynitride, which confirms its effectiveness as a barrier.
0 2ov
10~8
of leakage currents measured on 0.1
200 ,I
G
(b)
10~8
0.0
10’ E 0.1
0.2
0.3
0.4 I”
10’5 .-
0.0
0.1
Depth ( W Fig. 8. SIMS analysis of (a) LTO and (b) PECVD oxynitride
capacitors
0.2 0.3 Depth (pm)
after biased temperature
0.4 .”
stress
S.S. Wong et al. /Materials Chemistry and Physics 41 (1995) 229-233
232
Stress T,mc (Ilour) Fig.
9. Shift in threshold 1X106Vcm-‘).
voltage for PECVD oxynitride
capacitor
(E-field:
three-step chemo-mechanical polishing followed (Fig. 11 (g) ) Cu was first polished using a slurry containing A1,03 powder, H,O and HNO,. Next, TiW was polished using a slurry with Al,O, powder, Hz0 and H,O,. Finally, a thin Cu oxide, formed by the reaction with H,O, during the second step, was quickly removed with the Cu polishing slurry. The electromigration stress was performed in a nitrogen box to protect Cu lines from oxidation. The current density dependence of the time-to-failure was measured at 200 “C. A stress current density of 8 X lo6 A cm-* was used to determine the temperature dependence of the time-to-failure. The CVD Cu film exhibits a normal electromigration behavior: a gradual increase in resistance due to the formation of voids and hillocks, until a catastrophic failure occurs. Time-to-failure (TTF) is defined as the time when the line resistance has increased by 50%. Fig. 12 summarizes the c
‘”
35
25
21)
40
I/kT3;,,“,
Fig. 10. Extrapolated concentration of Cu ions that have drifted through PECVD oxynitride under an electric field of 1 MV cm-’ for 10 years. 10
Annealing
/
--t
100
ai
I
-
u
(d)
W Selective w deposition
--)
(e)
*
1 1
’ 106
IO8
IO 7 Current Density(Alcm
TiWsputtering
and pauern,ng
SKI-
’
*)
Fig. 12. Time-to-failure at 200 “C for various interconnection structures: (0) CVDCu/TiW,as-deposited; (Cl) CVDCu/TiW,annealed; (a) selective-W/CVD Cu/TiW; (0) buried CVD Cu/TiW; ( + ) buried sputtered Cu/TiW; (A) Al-l%Si/TiW.
=
(b)
T,WSi02-
Fig. 11. Schematic process flow and final CVD Cu interconnection structures: (a) as-depositedCu/TiW; (b) Cu/SiOz; (c) annealed Cu/TiW; (d) TiW/Cu/TiW; (e) selective-W/Cu/TiW; (f) SiO,/Cu/TiW; (g) buried CufTiW.
capping metal without an extra patterning (Fig. 11 (e) ) . A passivation layer of 0.8 pm PECVD SiOz was deposited on some wafers to investigate its effect (Fig. 11 (f) ) . For the buried Cu interconnections, 600 nm of thermal oxide was grown, and 500 nm deep trenches were reactive-ion etched. About 100 nm thick TiW was then deposited, followed by 800 nm thick CVD Cu. An anneal at 400 “C for 1 h was used to enhance the adhesion of Cu with the underlying TiW. A
1.7
I .8
I .9
2.0
Imemperature(
2.1
2.2
2.3
2.4
IO-‘/K)
Fig. 13. Arrhenius plot of time-to-failure for various interconnection structures (J= 8 x Q?” A cm-‘): (0) CVD Cu/TiW, as-deposited; (0) CVD Cu/TiW, annealed; (0) SiO,/CVDCu/TiW; (U) selective-W/CVD Cu/ TiW; (0) burred CVD Cu/TiW; ( + ) buried sputtered Cu/TiW; (A) All%Si/TiW.
S.S. Wong ef al. /Materials
Chemistry and Physics 41(1995)
current density dependence of the lTF at 200 “C for various key CVD Cu interconnection structures. The lifetime of sputtered Al-l%Si/TiW is also shown for comparison. The TTF decreases rapidly for current densities higher than 10’ A cm-* because of Joule heating. At 200 “C, the ‘RF of CVD Cu/TiW is at least two orders of magnitude longer than that of sputtered Al-l%Si/TiW. Buried Cu/TiW shows a TTF slightly longer than that of the etched Cu/TiW structure. This proves that chemo-mechanical polishing does not degrade the lifetime of Cu interconnections. Capping the buried Cu/ TiW structure with selective W further improves the TTF. Fig. 13 shows the temperature dependence of the TTF. The activation energy is about 0.5 eV for the various Cu structures, and 0.43 eV for Al-l%Si/TiW. The activation energy for Cu structures is lower than expected [ 81. Nevertheless, all Cu structures exhibit TTF values over two orders of magnitude longer than that of Al-l%Si/TiW throughout the range of typical device operation temperatures.
233
interconnections can be fabricated on device wafers without causing undesirable device degradation or failure. References [ I] E. Broadbent, J. Planner, W. Van der Hoek and I. Connick, High-density
[21
[3]
[41
[51
[61 [71
5. Conclusions [81
This work has shown that with the proper deposition conditions, metal and dielectric barriers, highly reliable CVD Cu
229-233
high-reliability tungsten interconnection by filled interconnect groove metallization, IEEE Trans. Elecrron Devices, 35 (1988) 952-956. A. Krishnan, C Xie, N. Kumar, J. Curry, D. Duane and S. Mu&a, Copper metallization for VLSI application, Proc. VMIC, Santa Clara, CA, USA, June 1992, pp. 226231. J. McVittie, J. Rey, L. Cheng, M. IslamRaja and K. Saraswat, LPCVD profile simulation using a re-emission model, IEDM Tech. Digest, San Francisco, CA, USA, Dec. 1990, pp. 917-920. J. Norman, B. Muratore, P. Dyer, D. Roberts and A. Hochberg, New OMCVD precursors for selective copper metallization, Proc. VMIC, Santa Clara, CA, USA, June 1991, pp. 123-129. J. Cho, H. Kang, I. Asano and S. Wong, CVD Cu interconnections for ULSI, IEDM Tech. Digest, San Francisco, CA, USA, Dec. 1992, pp. 297-300. J. McBrayer, R. Swanson and T. Sigmon, Diffusion of metals in silicon dioxide, J. Electrochem. Sot.. 133 ( 1986) 1242-1246. H. Kartg. I. Asano, C. Ryu, S. Wong and J. Norman, Grain structure and electromigration properties of CVD Cu metallization, Proc. VMlC, Santa Clara, CA, USA, June 1993, pp. 223-229. T. Ohmi, T. Hoshi, T. Yoshie, T. Takewaki. M. Otsuki, T. Shibata and T. Nita, Large-electromigration-resistance copper interconnect technology for sub-half-micron ULSI’s, IEDM Tech. Digest, Washington, DC, USA, Dec. 1991, pp. 285-288.
ELSEVIER
Review
Reliability of chemically vapor deposited (CVD) copper interconnections S. Simon Wong, James S. Cho, Ho-kyu Kang, Changsup Ryu Centerfor
Integrated Systems, Stanford University, Stanford, CA 94305, USA
Received 5 January 1995; accepted 25 January 1995
Abstract The reliability issues of chemically vapor deposited copper interconnections for applications in integrated circuits are discussed. The voidfree conformal deposition of copper films into high aspect ratio trenches and via holes is demonstrated. The effectiveness of various dielectrics and metals as diffusion and drift barriers is compared. The electromigration properties of different copper interconnection structures and the
dependence on microstructures, current densities and temperatures are evaluated. Keywords:
Reliability; Copper interconnections; Chemically vapor deposited copper interconnections
1. Introduction Copper (Cu), which has a high conductivity, is a promising metal for future integrated circuits. Cu is also expected to provide improved reliability. This paper will describe the components that are needed for a reliable Cu interconnection technology.
0.005 has been estimated. Simulation results, as illustrated in Fig. 3, predict that conformal coverage can be obtained in trenches with an aspect ratio as high as 4. The sticking coefficient does not depend strongly on the deposition pressure, but increases for deposition temperatures higher than 150 “C, as summarized in Fig. 4. This also coincides with an increase in the film resistivity. These results indicate that surface reaction and impurity incorporation become more significant at high deposition temperatures.
2. Step coverage of CVD Cu films Owing to the difficulty of dry etching Cu, the most promising method for implementing Cu interconnections is to form a planarized buried structure [ 1,2]. As illustrated in Fig. 1, this process circumvents the etching problem by defining the interconnections with trenches that are etched into a dielectric layer. After Cu is deposited to overfill the trenches, the excess metal is removed by chemo-mechanical polishing. This also leaves a fully planarized structure in which the interconnection is buried in the dielectric. To ensure the reliability of these buried interconnections, voids must not be allowed to form during the deposition process and hence good conformality is essential. A cantilever test structure, as shown in Fig. 2, was used to investigate the conformality of the deposition process, and the resulting profile was modeled with SPEEDIE to determine a sticking coefficient [ 31. With the metal organic precursor Cuf (tmvs) (hfac) [4], excellent conformality of the Cu films has been observed and a sticking coefficient as low as 0254-0584/95/$09.50 0 1995 Elsevier Science S.A. All rights reserved SSDIO254-0584(95)01526-Z
3. Diffusion and drift barriers Cu is a deep level acceptor in Si. The presence of Cu will degrade carrier lifetimes and cause excessive leakage currents. Metal and dielectric barriers will be needed to ensure that Cu does not reach active devices. To evaluate the effectiveness of TiW as a diffusion barrier, n + lp diodes with a 250 nm deep junction, as shown in Fig. 5, were fabricated. Diodes with only TiW and diodes without TiW were also fabricated as controls. Various thicknesses of TiW, 100, 50 and 25 nm, were studied. The diodes were annealed at 450 or 500 “C in a vacuum ambient for 30 min. Diodes with an area as large as 0.1 X 0.1 cm and a perimeter as long as 100 cm were tested. Leakage currents at a reverse bias of 5 V were collected using an automated tester. No additional leakage currents were observed in the perimeter intensive diodes. The results for the largest area diodes are summarized in the histograms presented in Fig. 6. The TiW-
230
S.S. Wang et al. /Materials
Chemistry and Physics 41 (1995) 229-233
(a)
Substrate
(b)
Substrate
Fig. 1. Process sequence for forming buried Cu interconnections.
.
Silicon
.
.._ . ..
Fig. 2. Cantilever test structure for studying the conformality
of CVD Cu.
Cu diffuses into Si and significantly degrades the leakage characteristic. TiW is an excellent diffusion barrier even up to 500 “C. However, for the 25 nm thick TiW, there are some occurrences of excessive leakage after an anneal at 500 “C, which may be related to defects in the TiW layer. Our previous work has confirmed that Cu does not diffuse through most dielectrics [5]. To investigate the drift characteristics of positively charged Cu ions through dielectrics [6], capacitors were fabricated on n-type Si wafers with about 150 nm of various dielectrics on top of 50 nm of thermal oxide. The thin thermal oxide was grown to ensure a good interface between the dielectric and Si. CVD Cu was deposited and patterned to form the top electrodes. The 0.1 X 0.1 cm capacitors were then subjected to biased temperature stressing with a d.c. bias ranging from - 10 to + 20 V for 1 h at 250 “C. This experiment was performed in a nitrogen box to prevent oxidation of the Cu. The high frequency C-V characteristics of the capacitors were then measured after the stressing, and the results are summarized in Fig. 7. Both LTO and PSG show significant shifts in the threshold voltage due to the drift of Cu ions through the dielectric. PECVD oxynitride has a very small amount of threshold shift. CVD nitride shows no shift. Fig. 8 gives the results of SIMS analysis performed on the LTO and PECVD oxynitride samples, which confirm that a significant amount of Cu ions has drifted through LTO and accumulated at the dielectric-Si interface, whereas no significant amount of Cu ions is present in the PECVD oxynitride. The drift behavior of Cu ions through PECVD oxynitride has been studied thoroughly. Fig. 9 summarizes the shift in threshold voltage under a constant field of 1 MV cm- ’ as a function of the stress temperature and time. There is an initial rapid change in the threshold voltage which saturates at about 1.3 V. This shift is believed to be due to alkaline ions, as no special precautions were taken to minimize ionic contamin; .on during the patterning and etching of the Cu electrodes. T. : shift is saturated once all the alkaline ions have accur’ Jlated at the dielectric4 interface. The slower shift in
0
00 IO0
125
150
175
200
0
Temperature('Cl
0
0.2 0.4 06
0.8
Fig. 4. Sticking coefficient as a function of the deposition
conditions
Fig. 3. Simulated step coverage ofCVD Cu film in deep trenches with various aspect ratios; sticking coefficient 0.005.
only diodes confirm that low leakage currents are obtained ( < 10 nA cm-’ on average) without Cu. Without a barrier,
Fig. 5. Diode test .xrvcture :‘or evaluating
1.0 1.2
Pressure(Torr)
the barrier metal
S.S. Wang et al. /Materials
Chemistry and Physics 41 (1995) 229-233
231
Cull00
Leakage
Current
Leakage
(A)
Current
Leakage
(A)
nm TiW
Current
(A)
z
x G/50
I50
a
nm TiW
Cu/25
nm TiW
-6 100 $ 5 z
50 n
l~~1210~lo
Leakage
Current
03
(A)
Leakage
Fig. 6. Histograms
(a)
1o-6
Current
lo-4
,~-1210-lo
(8)
(A)
,150 8 BICXJ .d Y ma 50 u
m 0-30
IO
5v
-10
PSG 4% -20 -10 0 Voltage (V)
@cl :: 5 loo .s 0 P 50 u -20 -10 0 Voltage (V)
Fig. 7. C-V characteristics biased temperature stress.
Current
X
10~4 0)
(A)
Leakage
IO
of Cu capacitors
with various dielectrics
after
threshold voltage at longer stress times is due to the Cu ions. This shift will not saturate, as there is an essentially unlimited supply of Cu ions. The shift can be extrapolated to determine the reliability under normal operation conditions, Fig. 10 shows that even under a high constant field of 1 MV cm- ’
Various Cu interconnection structures, as illustrated in Fig. 11, including Cu/SiOz, Cu/TiW, TiW/Cu/TiW, selectiveW/Cu/TiW, SiO,/Cu/TiW, and a buried CulTiW by chemo-mechanical polishing were prepared, and their electromigration properties were compared under d.c. stress conditions [ 71. 100 nm thick thermal oxide was grown and 500 nm thick CVD Cu was deposited either on a sputtered TiW seed layer (100 nm) or directly on thermal oxide. Cu film was then patterned and wet etched (Fig. 11 (a), (b)). Some of the samples were annealed at 400 “C for 1 h to achieve larger grains (Fig. 11 (c) ). On some wafers, 100 nm thick TiW was sputtered on the Cu before patterning and etching (Fig. 11 (d) ) to study the effect of a capping metal on the lifetime. 80 nm thick selective LPCVD W was also deposited as a
G- 10‘9 1ol8
.s ‘J $
10’7
B B
,016
3 10 I5
.”
(A)
reliability
106
E =
Current
0.1 cm diodes
4. Electromigration
IO
200
0 -30
Leakage
,O~f’
at 125 “C for 10 years, there will be less than 10’” cm-’ Cu ions that have drifted through the PECVD oxynitride, which confirms its effectiveness as a barrier.
0 2ov
10~8
of leakage currents measured on 0.1
200 ,I
G
(b)
10~8
0.0
10’ E 0.1
0.2
0.3
0.4 I”
10’5 .-
0.0
0.1
Depth ( W Fig. 8. SIMS analysis of (a) LTO and (b) PECVD oxynitride
capacitors
0.2 0.3 Depth (pm)
after biased temperature
0.4 .”
stress
S.S. Wong et al. /Materials Chemistry and Physics 41 (1995) 229-233
232
Stress T,mc (Ilour) Fig.
9. Shift in threshold 1X106Vcm-‘).
voltage for PECVD oxynitride
capacitor
(E-field:
three-step chemo-mechanical polishing followed (Fig. 11 (g) ) Cu was first polished using a slurry containing A1,03 powder, H,O and HNO,. Next, TiW was polished using a slurry with Al,O, powder, Hz0 and H,O,. Finally, a thin Cu oxide, formed by the reaction with H,O, during the second step, was quickly removed with the Cu polishing slurry. The electromigration stress was performed in a nitrogen box to protect Cu lines from oxidation. The current density dependence of the time-to-failure was measured at 200 “C. A stress current density of 8 X lo6 A cm-* was used to determine the temperature dependence of the time-to-failure. The CVD Cu film exhibits a normal electromigration behavior: a gradual increase in resistance due to the formation of voids and hillocks, until a catastrophic failure occurs. Time-to-failure (TTF) is defined as the time when the line resistance has increased by 50%. Fig. 12 summarizes the c
‘”
35
25
21)
40
I/kT3;,,“,
Fig. 10. Extrapolated concentration of Cu ions that have drifted through PECVD oxynitride under an electric field of 1 MV cm-’ for 10 years. 10
Annealing
/
--t
100
ai
I
-
u
(d)
W Selective w deposition
--)
(e)
*
1 1
’ 106
IO8
IO 7 Current Density(Alcm
TiWsputtering
and pauern,ng
SKI-
’
*)
Fig. 12. Time-to-failure at 200 “C for various interconnection structures: (0) CVDCu/TiW,as-deposited; (Cl) CVDCu/TiW,annealed; (a) selective-W/CVD Cu/TiW; (0) buried CVD Cu/TiW; ( + ) buried sputtered Cu/TiW; (A) Al-l%Si/TiW.
=
(b)
T,WSi02-
Fig. 11. Schematic process flow and final CVD Cu interconnection structures: (a) as-depositedCu/TiW; (b) Cu/SiOz; (c) annealed Cu/TiW; (d) TiW/Cu/TiW; (e) selective-W/Cu/TiW; (f) SiO,/Cu/TiW; (g) buried CufTiW.
capping metal without an extra patterning (Fig. 11 (e) ) . A passivation layer of 0.8 pm PECVD SiOz was deposited on some wafers to investigate its effect (Fig. 11 (f) ) . For the buried Cu interconnections, 600 nm of thermal oxide was grown, and 500 nm deep trenches were reactive-ion etched. About 100 nm thick TiW was then deposited, followed by 800 nm thick CVD Cu. An anneal at 400 “C for 1 h was used to enhance the adhesion of Cu with the underlying TiW. A
1.7
I .8
I .9
2.0
Imemperature(
2.1
2.2
2.3
2.4
IO-‘/K)
Fig. 13. Arrhenius plot of time-to-failure for various interconnection structures (J= 8 x Q?” A cm-‘): (0) CVD Cu/TiW, as-deposited; (0) CVD Cu/TiW, annealed; (0) SiO,/CVDCu/TiW; (U) selective-W/CVD Cu/ TiW; (0) burred CVD Cu/TiW; ( + ) buried sputtered Cu/TiW; (A) All%Si/TiW.
S.S. Wong ef al. /Materials
Chemistry and Physics 41(1995)
current density dependence of the lTF at 200 “C for various key CVD Cu interconnection structures. The lifetime of sputtered Al-l%Si/TiW is also shown for comparison. The TTF decreases rapidly for current densities higher than 10’ A cm-* because of Joule heating. At 200 “C, the ‘RF of CVD Cu/TiW is at least two orders of magnitude longer than that of sputtered Al-l%Si/TiW. Buried Cu/TiW shows a TTF slightly longer than that of the etched Cu/TiW structure. This proves that chemo-mechanical polishing does not degrade the lifetime of Cu interconnections. Capping the buried Cu/ TiW structure with selective W further improves the TTF. Fig. 13 shows the temperature dependence of the TTF. The activation energy is about 0.5 eV for the various Cu structures, and 0.43 eV for Al-l%Si/TiW. The activation energy for Cu structures is lower than expected [ 81. Nevertheless, all Cu structures exhibit TTF values over two orders of magnitude longer than that of Al-l%Si/TiW throughout the range of typical device operation temperatures.
233
interconnections can be fabricated on device wafers without causing undesirable device degradation or failure. References [ I] E. Broadbent, J. Planner, W. Van der Hoek and I. Connick, High-density
[21
[3]
[41
[51
[61 [71
5. Conclusions [81
This work has shown that with the proper deposition conditions, metal and dielectric barriers, highly reliable CVD Cu
229-233
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