Reliability of copper low-k interconnects

Microelectronic Engineering 87 (2010) 348–354

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Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee

Reliability of copper low-k interconnects } kei *, Kristof Croes, Gerald P. Beyer Zsolt To IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

a r t i c l e

i n f o

Article history: Received 23 March 2009 Received in revised form 14 May 2009 Accepted 22 June 2009 Available online 28 June 2009 Keywords: Reliability Low-k Copper Interconnects

a b s t r a c t For the implementation of copper and low-k materials into a tight pitch damascene interconnect architecture it is important to understand and correctly describe the underlying degradation mechanisms during reliability testing. Based on the understanding solutions can be proposed for avoiding fast degradation. While the physical understanding of electromigration mechanisms is less of a debate, technological challenges towards the fabrication of metal wires/vias able to carry the ever increasing current densities are enormous. Recently a number of novel metallization schemes including ruthenium and its alloys or self-forming barriers were proposed. As a consequence, some of the thermodynamic and kinetic behavior of the system can be modified when compared to the conventional Ta-based metallization. Another important component of the system is the insulating low-k dielectric. When scaling the critical dimensions into 50 nm ½ pitch and beyond, the impact of layout and line edge roughness becomes important. If a double patterning approach is used for printing a tight metal pitch, then misalignment between the different photos will exacerbate the layout induced effects. The choice of dielectric material, test structure design and damascene process steps will contribute on top of these effects. Based on recent understanding we review some aspects of novel metallization schemes and tight pitch copper/low-k interconnects from a reliability standpoint. Ó 2009 Elsevier B.V. All rights reserved.

1. Introduction It is important to identify the fundamental reliability limits of scaled copper/low-k interconnect schemes and correctly describe the active degradation mechanisms. An interconnect system is composed of the isolating dielectric material, copper or its alloys as a conducting material and diffusion barriers to prevent copper migration into the dielectric. Each of these components plays an important role in the reliability of the system. The implementation of today’s copper low-k interconnects is strongly impacted by the acquired understanding of their overall reliability both for metals and dielectrics. Metal reliability is generally assessed by studying electro-migration (EM) and stress induced voiding (SIV), while dielectric reliability is often assessed by leakage and time dependent dielectric breakdown (TDDB) or triangular voltage (TVS) sweep measurements. Numerous novel barrier metals, alloys of copper and copper cap layers were recently proposed in order to cope with the increasing current density that conductors have to carry. While the theoretical description of the EM phenomenon is well-understood, due to the large number of possible combinations careful testing of these schemes is very important in order to identify the active failure mechanisms. As for the insulating low-k materials [1] the typical industrially adopted low-k materials are * Corresponding author. Tel.: +32 16 28 17 78; fax: +32 16 28 15 76. } kei). E-mail address: [email protected] (Z. To 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.06.025

silica based. They can be derived from the silica matrix by exchanging Si–O bonds to less polar Si–CH3 (or Si–H) bonds, which leads to a reduction of the k-value. These materials are often referred to as carbon doped oxide (CDO) or SiOC:H materials. While covalent bonds have lower polarizability when compared to ionic bonds, the less polar bonds in low-k materials come on the expense of weaker bonds as compared to Si–O. This is shown in Table 1, which summarizes polarizability and bond energy [2–4]. Therefore, low-k materials in general are mechanically weaker than SiO2, which raises numerous questions to the overall reliability of these materials. In the subsequent sections we discuss some aspects of novel metallization schemes and tight pitch copper/low-k interconnects from a reliability standpoint. 2. Metal reliability: electromigration In order to describe mass transport (Jmass) related to copper migration the following general equation is used [5–7]:

J mass ¼ D  rC þ

DC  ½Z  qqje  X  rr: kT

ð1Þ

It is composed of three terms. The first term (D  rC) is a diffusion term, which describes the backflow of atoms due to build-up of a concentration gradient. D is the diffusion coefficient and rC is the concentration gradient. The second term (Z*qqje) relates to the electron wind, which is often referred to as

}kei et al. / Microelectronic Engineering 87 (2010) 348–354 Z. To Table 1 Bond-type, polarizability and average bond energy [2–4].

Top: CuGeN or Mn-oxide

Bond

Polarizability (Å3)

Average bond energy (kcal/mole)

C–C C–F C–O C–H O–H

0.531 0.555 0.584 0.652 0.706

347.3 485.3 351.5 414.2 426.8

C@O C@C C„C C„N

1.020 1.643 2.036 2.239

736.4 610.9 836.8 891.2

Si–C Si–H Si–Si Si–N Si–O Si–F Si–Cl Si–Br

349

SiC(N)

Cu

dielectric

or Cu-alloy SiC

451.5 6299.2 326.8 ± 10.0 470 ± 15 799.4 ± 13.4 552.7 ± 21 406 367.8 ± 10.0

SiC(N)

dielectric

Cu 120nm or 50nm SiC

MTTF ¼ A

 n   1 Ea ; exp j kT

ð2Þ

where A is an empirical constant, k the Boltzmann constant, n the current exponent and T the temperature. On one hand when copper interconnects are scaled into sub100 nm dimensions the resistivity of the metal lines significantly increases, which is caused by grain boundary and surface scattering as it was detailed in numerous publications. A recent summary on copper resistivity was compiled by Gignac et al. [8] and Josell et al. [9]. On the other hand as lines are getting narrower the EM lifetime degrades, because the failure time is roughly proportional to the product of the width and height of the interconnect lines. In practice the reliability margin decreases with each novel technology generation as the relative importance of the interfaces surrounding copper increases. The copper wire is wrapped into metallic and dielectric diffusion barriers in order to prevent copper migration into the neighbouring dielectric. Typically the sidewall barrier is Ta or Ti based, while the top cap is a dielectric (e.g. Si3N4, SiC(N), etc.). The dominant failure mechanism for EM is top interface related in most cases. Improving the adhesion at that interface does improve EM lifetime, but does not change the physics for degradation. Introducing novel cap materials, which reduce the top surface mobility does improve the strong mode EM performance. For example, CoWP, CoWB, CuSiN, CuGeN, MnSixOy, etc. have been proposed for alleviating the EM challenge at that interface. Moreover, as the capability of filling aggressively scaled copper wires is challenged in the sub-50 nm region several other sidewall barriers were proposed such as Ru or its alloys, self-forming Cu–Mn, Cu–Ti based barriers, etc. In general, one observes a trend of attempting to replace the conventional interfaces with other potentially better ones [10–30]. Of course, when novel interfaces are introduced this calls for careful investigation of the EM response. Fig. 1 shows the schematic cross-section cartoon of the investigated metallization options. Single damascene 120 nm wide passivated copper lines were embedded into a SiOC:H dielectric

Metal barrier: Ta(N)/Ta or Ru-alloy Fig. 1. Schematic cross-section cartoon of the investigated metallization schemes.

using 300 mm silicon wafers. General processing details are documented elsewhere [16,23,27]. Here we only focus on the differences between the various copper interfaces, which were systematically varied. In the case of the conventional TaN/Ta metal barrier 50 nm and 120 nm wide lines were compared in order to illustrate the effect of the dimensional scaling. Examples relating to the top interface layer include SiC(N), CuGeN and Mn-oxide. The top CuGeN layer was formed by using a GeH4/NH3 soak treatment [16]. The top Mn-oxide interface was generated by using a TaN/Ta/CuMn barrier/seed stack deposition, followed by copper electroplating and removal of the excess metal. Subsequently an anneal treatment at 420 °C for 40 min in a helium ambient with traces of oxygen was performed and finally the structures were passivated. The sidewall barrier quality was also varied and the conventional Ta(N)/Ta/Cu stack and a Ru-alloy/Cu stack were compared. Fig. 2 shows at the same experimental condition (315 °C, 2 MA/ cm2) the observed drift curves. It is evident that the longest lifetime is observed for a CuGeN top layer, because the top interface diffusion is reduced. This reduction in diffusion is in good

20

Resistance Drift (A.U.)

electromigration term. Z* is the effective charge number, q the electronic charge, je the electron current density. The third term describes the driving force arising from mechanical stress gradients and relates to stress migration. X is the atomic volume and rr is the stress gradient. In practical cases for describing EM the semi-empirical Black’s formula is used, which relates the median time to failure (MTTF) with the current density (j) and the thermal activation energy (Ea).

50nm TaN/Ta+Cu

120nm Ru-alloy+Cu 120nm TaN/Ta +CuGeN on top

15 10

120nm TaN/Ta+Cu

5 0

-5 -10 -15

120nm TaN/Ta+ Mn-oxide on top

-20 0

200

400

600

800

1000

1200

1400

1600

Failure Times (A.U.) Fig. 2. Drift curves at 315 °C and 2 MV/cm2 using different metallization schemes. The investigated linewidth is given in the legend as well as the type of the metal barrier and/or top cap layer below SiCN. Inset in the bottom right corner shows the schematic top–down cartoon of the investigated layout.

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agreement with the increased activation energy for CuGeN as compared to TaN/Ta; for CuGeN 1.3 ± 0.3 eV is measured, while for TaN/Ta 0.75 ± 0.2 eV with 95% confidence bounds. For a Mn-oxide (likely MnO2) identical lifetime to the conventional SiC(N) interface is observed. It is argued that due to the high temperature treatment a porous Mn-oxide layer was formed and the top interface copper migration was not changed compared to SiC(N)/Cu. In fact, through the porous Mn-oxide the dominating interface was still that of Cu/SiC(N). Furthermore, a strong line resistance decrease during the EM testing is also seen, which is attributed to residual Mn in the copper wire after fabrication. The manganese progressively moves to the interfaces during the EM testing itself, which then results in the decreasing resistance. When comparing 50 nm and 120 nm wide lines with a TaN/Ta sidewall barrier it is apparent that the EM lifetime is significantly reduced for the narrower wire, because the dimensional scaling naturally results in lifetime reduction [31,32]. In fact it is a simple manifestation that the relative importance of the interfaces indeed increases for narrower dimensions. Furthermore, voidless filling of lines with reduced dimensions becomes increasingly difficult. When comparing a single trace obtained for the Ru-alloy liner a slightly longer lifetime is observed in this example. In the subsequent section we will compare the EM performance of Ru and Ta based metallization more in detail. Fig. 3 shows a number of typical drift curves for TaN/Ta and Rualloy. In the case of the Ta-based metallization significant current shunting through the barrier is observed at the investigated dimensions. After the first void formation a jump in the resistance is observed, but it does not go to infinity, because the barrier can still conduct the current. Gradually, the void size increases and eventually more voids are formed in the line resulting in further resistance increase. In the case of the Ru-based liner the failures appear more abrupt. Apparently, this liner cannot shunt the current. On one hand the investigated Ru-based liner was only 4 nm thick, while the TaN/Ta barrier was 6 nm thick. On the other hand the difference is only 2 nm and the lower resistivity of Ru should compensate for that. Hence, we cannot exclude that the observa-

tion is in fact linked to the selective oxidation of the alloying element in Ru after the copper voiding starts. The measurements also show that void formation is slowed down for Ru-alloy when compared to TaN/Ta, i.e. the incubation time is longer, but void growth proceeds faster. Failure analysis (insets in Fig. 3) shows that in both cases similar void size is generated in the copper line. It appears, that in both cases the mobility along the SiC(N) interface, which is common in both considered schemes, governs the void formation. The fact that the Ta-based metallization shows a gradual wearout (i.e. current shunting) implies that the failure time will strongly depend on the failure criteria used. Two different failure criteria were considered for analyzing the data. The first criterion considered (FC1) reflects the first sudden change in the resistance value, while the second criterion used (FC2) is defined as 20% increase in the resistance value. Based on FC1 the Ta-based metallization is characterized by a somewhat shorter lifetime, but it has to be pointed out that when FC1 is reached the interconnect is not completely dysfunctional, because the barrier has the capability to conduct the current. For Ru-based metallization the resistance change is more abrupt. If FC2 is used, one observes identical failure distributions and lifetimes (Fig. 4). Therefore, we conclude that the EM lifetime of Ru-based interconnects is not worse than that of Tabased ones, but a higher lifetime from this experiment can only be deduced if the most conservative failure criterion representing the first jump is adopted. 3. Intrinsic properties of metallic barriers and intermetal dielectrics 3.1. Barrier properties of metals An essential component of the interconnect structures is the metallic diffusion barrier that confines the copper into the wire 99 90

TaN/Ta

2200

% Failed

Resistance (Ohm)

2300

2100

4nm Ru_1st jump

70 50 30

2000 10

1900 1800

1

1700 1600 1850

100

0

200

400

600

Failure Time (h)

1000

800 99

4nm Ru-alloy

1800 1750

6nm TaNTa_20% 4nm Ru_20%

90

1700

% Failed

Resistance (Ohm)

6nm TaNTa_1st jump

1650 1600 1550 1500

70 50 30 10

1450 1400

0

200

400

600

800

Time (h) Fig. 3. Comparative EM test for a 6 nm TaN/Ta (top) and a 4 nm Ru-alloy liner (bottom) at 315 °C and 2 MA/cm2. The insets show top–down SEM images after failure.

1

100

Failure Time (h)

1000

Fig. 4. Comparison of failure times for Ta and Ru-based copper metallization with two different failure criteria. FC1: failure is triggered at the first increase in resistance (top); FC2: failure is triggered at 20% resistance increase.

}kei et al. / Microelectronic Engineering 87 (2010) 348–354 Z. To

on the recess sidewalls. The intrinsic barrier properties are often put in question for diffusion barriers and it is of great importance to be able to assess the barrier efficiency. On one hand damascene test vehicles are not ideally suited for this purpose, because several interfaces contribute to the observations, which are difficult to deconvolute. On the other hand, fully passivated metal-oxide-semiconductor (MOS) capacitors are ideally suited [33,34]. The general processing details of such capacitors are described elsewhere [34]. Here we focus on the comparison of TaN/Ta [34], MnSixOy [23] and Ru-alloy barriers that were put on top of a 30 nm thermally grown silicon dioxide on n-type silicon. By choosing thermal oxide as the dielectric layer truly intrinsic properties can be monitored. Fig. 5 shows the result of TDDB measurements at various electric field values conducted at 100 °C. For reference purposes a capacitor without diffusion barrier is also included. It is clearly seen that the field acceleration is strongly linked to the barrier properties. At the intrinsic breakdown field of SiO2 (10 MV/cm) all investigated capacitors give similarly immediate and short failure times. At that field the failure time of the oxide itself is extremely short and copper cannot drift into the dielectric. Hence, simply the properties of the oxide itself are obtained. At lower field strength values there is significant difference between the pure copper sample and the diffusion barrier layers. When copper is injected into the dielectric it acts as a defect centre resulting in a significant reduction of the failure time of the oxide. In other words the voltage or field acceleration is strongly reduced for inadequate diffusion barriers. Under these truly ideal and defect free conditions, one can see that all barriers investigated here are performing excellent and in principle all of them can prevent the migration of copper into the underlying dielectric. 3.2. Electronic properties of intermetal dielectrics Besides copper and diffusion barriers the third very important ingredient of an interconnect system is the intermetal dielectric. While the integrated property of damascene dielectrics is often investigated, truly intrinsic properties are rarely assessed. The intrinsic electronic properties of these dielectric materials can be ideally studied by combining internal photoemission (IPE) and electron spin resonance (ESR) techniques. IPE is suited for measuring the energy barriers at dielectric/metal interfaces, while ESR is ideally placed to study the bulk electronic defects in the dielectrics. We have shown earlier [35] that the IPE threshold is almost independent of the metal electrode (Ti, Ta, Au, Al), the dielectric material (SiO2, SiOC:H, p-MSQ, spin-on polymer) and plasma treatments

1010

no barrier 10

6nm TaNTa

8

TTF [s]

2-3nm MnSixOy 4nm Ru-alloy

106

351

(He, NH3, O2/CF4/CH2F2/Ar). ESR measurements show that the bulk defect structure is significantly different for different classes of the dielectric materials [35]. The presence of a universal adsorbate (e.g. moisture related) or defect at the interface was used for explaining these observations. Recently, other researchers have also studied the defect properties of low-k materials using photoemission [36]. The energy barriers are in good agreement with our studies, but Atkin et al. also determined the defect density from measuring transient currents after the photo excitation was stopped. A value of approximately 6  1016 traps/cm3 was obtained for the defect density, which is orders of magnitude higher than typical trap densities in silicon dioxide. From these studies it is apparent that low-k dielectrics are ‘‘intrinsically defective”, when compared to SiO2. 4. Dielectric reliability of damascene interconnects The reliability margin of damascene dielectrics is of central debate nowadays. While a large number of factors and mechanisms have already been identified the physical understanding is far from complete [37–42]. The role of the chemical mechanical polishing (CMP) interface was recognized early and analyzed in great detail [43–47]. Accordingly, plasma treatments were optimized to allow for copper-oxide reduction left after an exposed CMP surface. Recently Heylen et al. established a quantitative relationship between the amount of copper residues and dielectric reliability using partially patterned damascene wafers [48]. It was found that at least 1012 at/cm2 residual copper is necessary for observing a noticeable copper induced degradation. In these investigations the degradation itself was not linked to copper migration during the electrical stress, but simply to the presence of a small amount of copper residue before even starting any reliability testing. Another well documented damascene low-k integration issue relates to the degradation of the intermetal dielectric during the patterning steps. When CDO (or SiOC:H) dielectrics are exposed to patterning plasmas unwanted modifications, such as carbon depletion and the incorporation of silanol groups can occur. This then leads to degradation of the dielectric reliability margin [40,49– 52]. Typical single damascene TDDB test structures are shown schematically in Fig. 6. While meander-fork (MF) and fork–fork (FF) structures are being extensively used for reliability evaluation in numerous research groups, the recently proposed parallel line (PL) structures are less widespread [53]. PLs can be regarded as the most ideal damascene capacitors that already encompass the damascene integration issues, since they are fabricated the same way as the ultimate interconnect, but they do not suffer from unwanted layout induced field enhancement. The structure length typically varies between a few hundred nm and several thousands of lm. The short structures are ideally suited for locating failures, while longer structures enable model investigations on damascene lines. An added advantage of the parallel line structures is that they offer a unique opportunity to study layouts generated by double patterning. Indeed, for narrow pitch interconnects double patterning has to be introduced as conventional lithography in a single

104

102

100

6

7

8

9

10

11

E [MV/cm] Fig. 5. The result of TDDB measurements conducted on fully passivated MOS capacitors at 100 °C with various metal diffusion barriers.

Fig. 6. Typical layout of single damascene test structures; the black and the grey lines are printed in two different lithography steps.

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print cannot keep up with the pace of current pitch scaling. In order to avoid any unwanted variation in the test structure we have added a large number of assist features next to the two central electrically connected lines. The dielectric thickness between the two central lines is (approximately) constant regardless of the particular double patterning approach adopted. If MF of FF structures are printed using double patterning then they suffer from a dual distribution of dielectric spacing, because of the misalignment between the different photos and thereby making model investigations cumbersome. Fig. 7 shows top–down optical microscope images from 50 nm ½ pitch damascene lines fabricated by double patterning after voltage ramp breakdown. In the case of MF structures the failures preferentially occur at the electrical connection, where the transition between the densely patterned area and the bonding pad takes place, which from the optical images appear to be weak points. In the case of FF structures the fork-endings are particularly vulnerable due to local field enhancement at that place. This is corroborated by the observed preferential failures at those locations (Fig. 7b). PLs on the other hand show random failures along the line. Typically under optical microscope burn marks are not detected or only rarely seen (Fig. 7c), because the extent of damage caused to the structure is much less pronounced. More careful SEM analysis shows that the failures are located randomly along the lines (Fig. 8), which is a natural consequence of the uniform field distribution across dielectric along the entire investigated length. This is very important if one aims to contribute in establishing, for example, acceleration models that to date are a matter of strong debate. In our opinion, if layout sensitive test structures are used it becomes very difficult to de-convolute the layout contribution. Based on our observations, MF and FF test structures are particularly layout sensitive especially in combination with double patterning approaches and aggressively scaled interconnects. Layout induced breakdown was studied in several publications and in all cases it is linked to a dielectric field enhancement at specific location within the test array, which then distorts the associated breakdown distributions [54,55]. In Fig. 8, 50 nm ½ pitch copper lines that were covered by an SiC(N) moisture barrier prior to conducting the voltage ramp experiment are shown. In this example the two central lines were connected electrically and the other lines are simply assist features. It is seen that the failure is somewhere along the line, but certainly not at line ends; i.e. it occurs randomly along the test structure. It is noted that in order to induce visible failures under SEM several voltage ramps were necessary to generate the failed lines shown in Fig. 8b.

Fig. 7. Top–down optical microscope images of MF (a), FF (b) and PL (c) test patterns with 50 nm ½ pitch k = 2.5 low-k interconnects after voltage ramp breakdown at 100 °C. The length of the test structures is indicated in the figures.

Fig. 8. 50 nm ½ pitch copper lines embedded into a CDO k = 2.5 low-k material; (a) test structure before breakdown, (b) test structure after breakdown.

Recently, ample attention was given to the influence of line edge roughness (LER) on interconnect performance and reliability [56–58]. The magnitude of LER is not primarily defined by the layout, but rather by the properties of the photoresist and by the interaction of lithography and etch processes. As such, LER induced protrusions are randomly distributed along the wires. LER also causes electric field enhancement within the test structure by a factor as high as 1.5–2 [58]. Another important factor that causes field enhancement in a dual damascene architecture at preferential locations is the presence of misaligned vias. It was shown that for short lines (typically on the order of 10 lm or shorter) the effect of misaligned vias dominates in a dual damascene architecture. For lines above a critical length it depends on the precision of the lithography overlay whether line-edge roughness induced field enhancement or via misalignment induced field enhancement dominates. For a detailed discussion of this subject the reader is referred elsewhere [58]. In the subsequent section we focus our attention to the combination of various materials together with narrow dielectric spacing. Fig. 9 compares tungsten lines and copper lines embedded into silicon dioxide as well as copper lines in combination with a 50 nm ½ pitch low-k integration. The details of the integration process can be found elsewhere [27,55,59]. The dielectric spacing in all cases was kept at around 50 nm. In the case of W-metallization the liner is a Ti/TiN stack, while for copper metallization a TaN/Ta diffusion barrier is used. After full passivation both MF and PL structures were tested in TDDB at 100 °C using wafer level testing. The median failure times are plotted in Fig. 10. When comparing W and Cu lines embedded into SiO2 we observe a lifetime reduction for copper, which is interpreted in terms of a small amount of copper residue induced by the CMP process as discussed above. Indeed, for tungsten lines little difference is detected between 1000 lm and

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data indicate that copper metallization in combination with a double patterning approach is extendible below 50 nm ½ pitch. From a reliability standpoint the example shows that one has to critically review the current approach to dielectric reliability testing especially in terms of test/qualification patterns. While conventional MF structures provide invaluable help in optimizing yield and reducing defect density, they may not be the most ideally suited if one attempts to use them for lifetime extraction. We believe that PLs are better suited for such a purpose. 5. Summary

Fig. 9. Cross-sectional TEM pictures with 50 nm dielectric spacing using parallel line structures in combination with double patterning. In the case of SiO2 samples the metal lines are about 150 nm wide. For low-k samples 50 nm half pitch structures are shown. (a) W-embedded into SiO2, (b) Cu embedded into SiO2, (c) Cu embedded into CDO k = 3.0, (d) Cu embedded into CDO k = 2.5.

MF: 10000µm Cu/CDO k=3.0

1010

MF: 10000µm Cu/CDO k=2.5 PL: 1000µm Cu/CDO k=2.5 10

PL: 2500µm Cu/SiO2

8

PL: 1000µm W/SiO2 MTTF [s]

PL: 2500µm W/SiO2

We have considered several reliability aspects of metals, barriers and dielectrics of advanced interconnects. Both intrinsic as well as integrated properties were detailed. Experimental examples included a comparison of the reliability of a Ta-based and a Ru-based metallization. While the intrinsic barrier properties of TaN/Ta and Ru-alloy are identical, in electromigration either equivalent performance or slightly better performance for Ru-based schemes was observed depending on the failure criterion used. The failure mechanism was found to be identical in both cases and was initiated on the top SiC(N)/Cu interface. In terms of dielectric reliability we geared our discussion towards dielectric spacing values of 50 nm in combination with a double patterning approach. While significant progress was made in the understanding of the intrinsic electrically active defect properties of intermetal dielectrics the relation of those to the integrated damascene dielectric reliability is not yet fully described. A number of key detractors were already identified (such as CMP influence, dielectric degradation in patterning, variability across the wafer, line edge roughness, via misalignment etc.), but in order to make further progress in failure analysis and understanding of the governing equations we argue that parallel line structures are better suited than conventional meander-fork test patterns.

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Acknowledgements Cu/SiO2

Cu/CDO

104

The authors wish to acknowledge the entire BEOL team for numerous fruitful discussions and debates, the IMEC pilot line for timely processing of the test wafers, the materials analysis group for sample analysis and the Amsimec measurement lab.

W/SiO2

102

References 10

0

0

1

2

3

4

5

6

7

E [MV/cm] Fig. 10. TDDB results obtained on 50 nm dielectric spacing using PL and MF test structures at 100 °C. SiO2 lines are compared to CDO k = 3.0 and CDO k = 2.5.

2500 lm long PLs, while for copper, an order of magnitude lifetime decrease is seen for 2500 lm long lines. We note here that the purpose of the experiment was by far not to achieve an optimized copper/SiO2 scheme, but rather to illustrate the impact of copper for a 50 nm dielectric spacing. For the 50 nm half pitch low-k structures the TDDB results obtained for MF and PL structures are plotted. What is interesting is that only a slight difference is seen between the investigated k = 2.5 and k = 3.0 materials in terms of dielectric reliability. While the shortest lifetime is obtained for MF structures in combination with the CDO k = 2.5 material, from the above discussion it is obvious that besides materials properties also the layout played an important role. Indeed for the same dielectric spacing on a parallel line test structure, which is shorter though, a higher lifetime is obtained. From a technological standpoint these

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