- Email: [email protected]
Reliability problems in TTL-LS devices
Microelectron.Reliab..Vol.22. No. 4. pp. 895-91I. 1982. Printedin Great Britain.
0026-2714/82/040895-17503.00/0 © 1982PergamonPressLtd.
W O R L D ABSTRACTS O N M I C R O E L E C T R O N I C S A N D RELIABILITY The abstracts below are given in reasonable detail where necessary so that an appreciation can be made of the co~,erage of the article. They are probably the most comprehensive detailed abstracts published in these two fields and in general are all of articles published within the last 12 months. They are classified into the following sections. Subjects 1. Reliability--General. 2. Reliability of Components, Tubes, Transistors and ICs. 3. Circuit and Systems Reliability, Maintenance and Redundancy. 4. Microelectronics--General. 5. Microelectronics--Design and Construction. 6. Microelectronics--Components, Systems and Equipments. 7. Semiconductor Integrated Circuits, Devices and Materials. 8. Thick- and Thin-Film Components, Hybrid Circuits and Materials. 9. Electron, Ion and Laser Beams.
1. R E L I A B I L I T Y - - G E N E R A L The mission profile. ROBERT BERNARD and NICOLAS MOKHOEF. IEEE Spectrum, 47 (October 1981 ). Satisfying the "customer" entails balancing a product's reliability with availability and maintainability. 2. R E L I A B I L I T Y
OF COMPONENTS,
An evaluation of plastic coatings for high reliability microcircuits. NIHAL SINNADURAI. Microelectronics J. 12 (6), 30 (1981). A systematic evaluation of a range of plastic coatings, to identify those suitable for use on bare microcircuit dice for high reliability applications, has been conducted by materials analyses and by damp heat overstress of coated special test vehicles. Some promising junction coatings were first selected and then used in subsequent tests with added top coatings in order to evaluate a range of composite coatings. Over 4000 hours of overstress have been accumulated from tests on some 500 test vehicles and over 15 different coatings examined. The materials analyses provided a coarse screen and roughly correlated with the damp heat test results, which proved to be more discriminating. While some junction coatings gave excellent results, it was very apparent that their performance could be severely impaired by the addition of poor top coatings. Nevertheless the outcome from this exercise has been the identification of a number of promising pairs of coatings, with the caution that evaluations with more sensitive active elements have yet to be done. A note on lC-yield statistics. R. M. WARNER,JR. Solid-State Electronics 24 (11 ), 1045 (1981). Expressions given by Moore and by Dingwall for relating integrated-circuit yield to area are compared and are given a common interpretation in terms of the composite model. The issue of large-chip yield projection is discussed, a subject that is still unclear because of the concave-up projections of the empirical curves, the linear projection of the composite model, and the concavedown projections of recent analytical models. BS9000 components and reliability quality factors: suggested use of MIL-HDBK-217C factors based on a comparative product assurance analysis. J. G. GISSING, Microelectron. Reliab. 21 (5), 683 (1981). The calculation of electronic component failure rates using the MIL-HDBK-217C failure 895
Overlooking the obvious. ROBERT BERNARD.IEEE Spectrum, 85 (October 1981 ). In large, complex systems, even the most careful designer can lose sight of an obvious error.
TUBES,
TRANSISTORS
AND
ICs
rate model requires an assessment of component quality-the rcQ factor. Quality factors are not directly available for BS9000/CECC components and application of the MILHDBK-217C model becomes difficult. The paper makes a comparative analysis of the product assurance programmes of MIL-SPEC and BS/CECC components and suggests that quality factors as published in the MIL-HDBK can be assigned to UK approved components. Quality factors relevant to UK product assurance levels are tabled for all active and passive devices.in the BS9000 series. A more detailed comparison between UK passives and MIL-SPEC Established Reliability devices will require a Certified Test Record (CTR) analysis. Such an analysis is now becoming possible as CTR data is assembled on the M O D U S data bank of the University of Sheffield. Some of the problems and limitations of a CTR analysis are briefly mentioned. Reliability problems in TTL-LS devices. C. CANALI, F. FANTINI, S. GAVIRAGHI and A. SENIN. Microelectron. Reliab. 21 (5), 637 (1981). An analysis of the possible failure modes of TTL-LS was carried out, with particular emphasis on long term thermal stability of Schottky diodes, all realized by PtSi-Ti/W-AI metallization system. Only from one supplier were there diodes in which changes in the characteristics, due to metallization defects, were observed during accelerated thermal cycles. On the contrary, once its uniformity is guaranteed, the Ti/W barrier layer inhibits the Si-AI interdiffusion up to 550°C, 1 hr thermal annealing. Sensitivity to negative input pulses and electrical overstresses were also investigated. Scanning electron microscope and microprobe, and voltage contrast techniques seem to be more suitable instruments to investigate the reliability of such devices than the conventional life tests.
896
World Abstracts on Microelectronics and Reliability
The technology employed today seems to provide suitable reliability for T T L Low-Power Schottky devices,
dependent, which if not taken into account, results in erroneous reliability projections.
Migration of silver from silver-loaded polyimide adhesive chip bonds at high temperatures. ROGER J. CHAFFIN. IEEE Trans. Components, Hybrids, Mfi3 Teclmol. Chmt-4, (2) p. 214 (June
Reliability of D H Gal_~AI,As LEDs for lightwave communications. C. L. ZIPEEL, A. K. CHIN, V. G. KERAMIDASand R. H. SAUL. IEEE/Proc. IRPS 124 (1981). Double heterostructure Ga~_xAlxAs LEDs operated at high current densities (3 x 103 A/cm 2) are being used as sources in lightwave communication systems, for example in optical data links. This paper discusses the reliability of these devices, distinguishing between catastrophic degradation due to Dark Line Defect (DLD) formation and gradual aging mechanisms. Two modes of D L D formation are observed: ( 1) A certain percentage of devices fail in relatively short times by D L D formation at threading dislocations. The growth of these D L D s is strongly current dependent, but independent of temperature. A 100h, 100mA burn-in eliminates all of the devices which fail by this mode. Burn-in failures can be kept as Iow as 5%. (2) Under accelerated aging as many as 257"o of the devices which passed the burn-in fail after 103h by a new mode of D L D formation. This mode is temperature dependent and related to stress at the dielectric-metal interface. Analysis shows that a 25 ",~ freak population gives ~<40 FITS at 70°C. Accelerated aging studies of clear devices are complicated by two competing processes: a slow degradation in light output and a slow increase which dominates at high temperatures. Activation energies for the two processes are 0.65 and 0.75 eV, respectively. Projected values of M T T F are 9 x 107h at 25°C and 4 × 106h at 70°C.
1981 ). A degradation mechanism found at high temperatures in a commercial silver-loaded polyimide chip adhesive is discussed. The adhesive was used to attach semiconductor diodes to headers for potential use in the geothermal well probe program. Aging the mounted devices at 300°C for 1100h resulted in a bias dependent migration of the silver out of the adhesive. This effect was accompanied by an increased series resistance and weakened bond strength.
Gettering processes for defect control. JOSEPH R. MONKOWSKL Solid-State Technology 44 (July 1981 ). As a result of the need for very low defect and contamination levels in today's silicon, many different types of gettering techniques have been established. These gettering techniques include backsurface damage, intrinsic gettering, chlorine-oxidation, diffusion, and annealing. In this article the techniques are explained, and some of the literature dealing with each technique is reviewed. In addition, an account is given of the most deleterious defects and their effects on device performance. S E M / E D A X analysis of pind test failures. J. F. DAL PORTO, D. H. LOESCHER, H. C. OLSON and P. V. PLUNKETT. IEEE/ Proc. IRPS 163 (1981). Packaged LSI and hybrid devices used in high reliability military and space applications must pass a rigorous series of screens defined by Method 5004 of Mil Standard 883B. One of these screens is the Particle Impact Noise Detection (PIND) test. This test uses a very sensitive acoustic transducer to listen for particles within the package while the package is vibrated and shocked. We have used SEM, EDAX, and optical microscopy to analyze the particles from P I N D failures. From these analyses we have identified the primary sources of P I N D failures and have developed procedures that yield a low reject rate at P1ND test. The device used in this investigation was a 1 K RAM die eutectically attached to a 24-pin leadless hermetic package (LHP). The package is solder sealed in a belt furnace with a gold-tin eutectic preform and a gold-plated cover. We have recovered the particles from P I N D test failures by placing lead tape over a punched hole in the gold plated Kovar lid. The package is then vibrated until the particles pass through the hole and are attached to the adhesive on the tape. From the analyses we have identified many sources of particles that cause P I N D test failures; the main source being the gold-tin solder preform used in the sealing process. We have investigated the effect of sealing materials, furnace temperature, furnace ambient, and package orientation on the number of gold-tin solder spheres. The best results were obtained with a nonoxidizing furnace ambient with the packages placed lid down and angled at 45 degrees during sealing. These improved assembly processes have led to P I N D test yields of better than 90 percent.
How parts fail. EDGAR A. DOYLE, JR. IEEE Spectrum 36 (October 1981). A fundamental explanation for any part failure exists, and it's up to the failure analyst to find the cause with modern sleuthing.
Temperature dependent defect level for an ionic failure mechanism. RICHARD S. HEMMERT. IEEE/Proc. IRPS 172 (1981). O n N-channel M O S F E T devices, phosphosilicate glass maintains threshold stability by gettering ionic (sodium) contaminants, typically to 250°C. However, defects can affect the phosphosilicate glass and substantially reduce its gettering ability. The defect level then becomes temperature
Electrostatic discharge failures of semiconductor devices. B. A. UNGER. IEEE/Proc. IRPS 193 (1981). ESD (Electrostatic Discharge) is a significant cause of device failures at all stages of device and equipment production, assembly, test, installation and field use. Even though device designs include protection circuitry, it is relatively easy to generate static potentials during handling and shipping that exceed the limits of the protection networks. D a m a g e from ESDs can cause either complete device failure by parametric shifts, or device weakness by locally heating, melting, or otherwise damaging oxides, junctions or device components. There are three principal sources of charge which can give rise to damaging ESD events. 1. A charged person touches a device and discharges the stored charge to or through the device to ground. 2. The device itself acting as one plate of a capacitor can store charge. Upon contact with an effective ground the discharge pulse can create damage. 3. An electrostatic field is always associated with charged objects. Under particular circumstances, a device inserted in this field can have a potential induced across an oxide that creates breakdown. All devices and technologies are susceptible to damaging ESDs. The difference is in their degree of susceptibility. MOS structures appear to be the most susceptible to ESD damage. The generation of charge varies with materials, environment, and conditions of contact. All materials can be charged, however with conductors the charge is readily dissipated by grounding. With insulators, the charge is immobile and not readily dissipated. Two basic measures for avoiding ESD damage and failures are: 1. Always wear a grounding strap when handling electronic components, 2. For transport, storage or assembly, a static-free environment must be created by selection of materials, shielding and proper grounding.
Reliability study of plastic encapsulated copper lead frame/ epoxy die attach packaging system. J. R. HOWELL. IEEE/Proc. IRPS 104 (1981). This paper presents the evaluation methods used to appraise the reliability of plastic/copper lead frame
0026-2714/82/040895-17503.00/0 © 1982PergamonPressLtd.
W O R L D ABSTRACTS O N M I C R O E L E C T R O N I C S A N D RELIABILITY The abstracts below are given in reasonable detail where necessary so that an appreciation can be made of the co~,erage of the article. They are probably the most comprehensive detailed abstracts published in these two fields and in general are all of articles published within the last 12 months. They are classified into the following sections. Subjects 1. Reliability--General. 2. Reliability of Components, Tubes, Transistors and ICs. 3. Circuit and Systems Reliability, Maintenance and Redundancy. 4. Microelectronics--General. 5. Microelectronics--Design and Construction. 6. Microelectronics--Components, Systems and Equipments. 7. Semiconductor Integrated Circuits, Devices and Materials. 8. Thick- and Thin-Film Components, Hybrid Circuits and Materials. 9. Electron, Ion and Laser Beams.
1. R E L I A B I L I T Y - - G E N E R A L The mission profile. ROBERT BERNARD and NICOLAS MOKHOEF. IEEE Spectrum, 47 (October 1981 ). Satisfying the "customer" entails balancing a product's reliability with availability and maintainability. 2. R E L I A B I L I T Y
OF COMPONENTS,
An evaluation of plastic coatings for high reliability microcircuits. NIHAL SINNADURAI. Microelectronics J. 12 (6), 30 (1981). A systematic evaluation of a range of plastic coatings, to identify those suitable for use on bare microcircuit dice for high reliability applications, has been conducted by materials analyses and by damp heat overstress of coated special test vehicles. Some promising junction coatings were first selected and then used in subsequent tests with added top coatings in order to evaluate a range of composite coatings. Over 4000 hours of overstress have been accumulated from tests on some 500 test vehicles and over 15 different coatings examined. The materials analyses provided a coarse screen and roughly correlated with the damp heat test results, which proved to be more discriminating. While some junction coatings gave excellent results, it was very apparent that their performance could be severely impaired by the addition of poor top coatings. Nevertheless the outcome from this exercise has been the identification of a number of promising pairs of coatings, with the caution that evaluations with more sensitive active elements have yet to be done. A note on lC-yield statistics. R. M. WARNER,JR. Solid-State Electronics 24 (11 ), 1045 (1981). Expressions given by Moore and by Dingwall for relating integrated-circuit yield to area are compared and are given a common interpretation in terms of the composite model. The issue of large-chip yield projection is discussed, a subject that is still unclear because of the concave-up projections of the empirical curves, the linear projection of the composite model, and the concavedown projections of recent analytical models. BS9000 components and reliability quality factors: suggested use of MIL-HDBK-217C factors based on a comparative product assurance analysis. J. G. GISSING, Microelectron. Reliab. 21 (5), 683 (1981). The calculation of electronic component failure rates using the MIL-HDBK-217C failure 895
Overlooking the obvious. ROBERT BERNARD.IEEE Spectrum, 85 (October 1981 ). In large, complex systems, even the most careful designer can lose sight of an obvious error.
TUBES,
TRANSISTORS
AND
ICs
rate model requires an assessment of component quality-the rcQ factor. Quality factors are not directly available for BS9000/CECC components and application of the MILHDBK-217C model becomes difficult. The paper makes a comparative analysis of the product assurance programmes of MIL-SPEC and BS/CECC components and suggests that quality factors as published in the MIL-HDBK can be assigned to UK approved components. Quality factors relevant to UK product assurance levels are tabled for all active and passive devices.in the BS9000 series. A more detailed comparison between UK passives and MIL-SPEC Established Reliability devices will require a Certified Test Record (CTR) analysis. Such an analysis is now becoming possible as CTR data is assembled on the M O D U S data bank of the University of Sheffield. Some of the problems and limitations of a CTR analysis are briefly mentioned. Reliability problems in TTL-LS devices. C. CANALI, F. FANTINI, S. GAVIRAGHI and A. SENIN. Microelectron. Reliab. 21 (5), 637 (1981). An analysis of the possible failure modes of TTL-LS was carried out, with particular emphasis on long term thermal stability of Schottky diodes, all realized by PtSi-Ti/W-AI metallization system. Only from one supplier were there diodes in which changes in the characteristics, due to metallization defects, were observed during accelerated thermal cycles. On the contrary, once its uniformity is guaranteed, the Ti/W barrier layer inhibits the Si-AI interdiffusion up to 550°C, 1 hr thermal annealing. Sensitivity to negative input pulses and electrical overstresses were also investigated. Scanning electron microscope and microprobe, and voltage contrast techniques seem to be more suitable instruments to investigate the reliability of such devices than the conventional life tests.
896
World Abstracts on Microelectronics and Reliability
The technology employed today seems to provide suitable reliability for T T L Low-Power Schottky devices,
dependent, which if not taken into account, results in erroneous reliability projections.
Migration of silver from silver-loaded polyimide adhesive chip bonds at high temperatures. ROGER J. CHAFFIN. IEEE Trans. Components, Hybrids, Mfi3 Teclmol. Chmt-4, (2) p. 214 (June
Reliability of D H Gal_~AI,As LEDs for lightwave communications. C. L. ZIPEEL, A. K. CHIN, V. G. KERAMIDASand R. H. SAUL. IEEE/Proc. IRPS 124 (1981). Double heterostructure Ga~_xAlxAs LEDs operated at high current densities (3 x 103 A/cm 2) are being used as sources in lightwave communication systems, for example in optical data links. This paper discusses the reliability of these devices, distinguishing between catastrophic degradation due to Dark Line Defect (DLD) formation and gradual aging mechanisms. Two modes of D L D formation are observed: ( 1) A certain percentage of devices fail in relatively short times by D L D formation at threading dislocations. The growth of these D L D s is strongly current dependent, but independent of temperature. A 100h, 100mA burn-in eliminates all of the devices which fail by this mode. Burn-in failures can be kept as Iow as 5%. (2) Under accelerated aging as many as 257"o of the devices which passed the burn-in fail after 103h by a new mode of D L D formation. This mode is temperature dependent and related to stress at the dielectric-metal interface. Analysis shows that a 25 ",~ freak population gives ~<40 FITS at 70°C. Accelerated aging studies of clear devices are complicated by two competing processes: a slow degradation in light output and a slow increase which dominates at high temperatures. Activation energies for the two processes are 0.65 and 0.75 eV, respectively. Projected values of M T T F are 9 x 107h at 25°C and 4 × 106h at 70°C.
1981 ). A degradation mechanism found at high temperatures in a commercial silver-loaded polyimide chip adhesive is discussed. The adhesive was used to attach semiconductor diodes to headers for potential use in the geothermal well probe program. Aging the mounted devices at 300°C for 1100h resulted in a bias dependent migration of the silver out of the adhesive. This effect was accompanied by an increased series resistance and weakened bond strength.
Gettering processes for defect control. JOSEPH R. MONKOWSKL Solid-State Technology 44 (July 1981 ). As a result of the need for very low defect and contamination levels in today's silicon, many different types of gettering techniques have been established. These gettering techniques include backsurface damage, intrinsic gettering, chlorine-oxidation, diffusion, and annealing. In this article the techniques are explained, and some of the literature dealing with each technique is reviewed. In addition, an account is given of the most deleterious defects and their effects on device performance. S E M / E D A X analysis of pind test failures. J. F. DAL PORTO, D. H. LOESCHER, H. C. OLSON and P. V. PLUNKETT. IEEE/ Proc. IRPS 163 (1981). Packaged LSI and hybrid devices used in high reliability military and space applications must pass a rigorous series of screens defined by Method 5004 of Mil Standard 883B. One of these screens is the Particle Impact Noise Detection (PIND) test. This test uses a very sensitive acoustic transducer to listen for particles within the package while the package is vibrated and shocked. We have used SEM, EDAX, and optical microscopy to analyze the particles from P I N D failures. From these analyses we have identified the primary sources of P I N D failures and have developed procedures that yield a low reject rate at P1ND test. The device used in this investigation was a 1 K RAM die eutectically attached to a 24-pin leadless hermetic package (LHP). The package is solder sealed in a belt furnace with a gold-tin eutectic preform and a gold-plated cover. We have recovered the particles from P I N D test failures by placing lead tape over a punched hole in the gold plated Kovar lid. The package is then vibrated until the particles pass through the hole and are attached to the adhesive on the tape. From the analyses we have identified many sources of particles that cause P I N D test failures; the main source being the gold-tin solder preform used in the sealing process. We have investigated the effect of sealing materials, furnace temperature, furnace ambient, and package orientation on the number of gold-tin solder spheres. The best results were obtained with a nonoxidizing furnace ambient with the packages placed lid down and angled at 45 degrees during sealing. These improved assembly processes have led to P I N D test yields of better than 90 percent.
How parts fail. EDGAR A. DOYLE, JR. IEEE Spectrum 36 (October 1981). A fundamental explanation for any part failure exists, and it's up to the failure analyst to find the cause with modern sleuthing.
Temperature dependent defect level for an ionic failure mechanism. RICHARD S. HEMMERT. IEEE/Proc. IRPS 172 (1981). O n N-channel M O S F E T devices, phosphosilicate glass maintains threshold stability by gettering ionic (sodium) contaminants, typically to 250°C. However, defects can affect the phosphosilicate glass and substantially reduce its gettering ability. The defect level then becomes temperature
Electrostatic discharge failures of semiconductor devices. B. A. UNGER. IEEE/Proc. IRPS 193 (1981). ESD (Electrostatic Discharge) is a significant cause of device failures at all stages of device and equipment production, assembly, test, installation and field use. Even though device designs include protection circuitry, it is relatively easy to generate static potentials during handling and shipping that exceed the limits of the protection networks. D a m a g e from ESDs can cause either complete device failure by parametric shifts, or device weakness by locally heating, melting, or otherwise damaging oxides, junctions or device components. There are three principal sources of charge which can give rise to damaging ESD events. 1. A charged person touches a device and discharges the stored charge to or through the device to ground. 2. The device itself acting as one plate of a capacitor can store charge. Upon contact with an effective ground the discharge pulse can create damage. 3. An electrostatic field is always associated with charged objects. Under particular circumstances, a device inserted in this field can have a potential induced across an oxide that creates breakdown. All devices and technologies are susceptible to damaging ESDs. The difference is in their degree of susceptibility. MOS structures appear to be the most susceptible to ESD damage. The generation of charge varies with materials, environment, and conditions of contact. All materials can be charged, however with conductors the charge is readily dissipated by grounding. With insulators, the charge is immobile and not readily dissipated. Two basic measures for avoiding ESD damage and failures are: 1. Always wear a grounding strap when handling electronic components, 2. For transport, storage or assembly, a static-free environment must be created by selection of materials, shielding and proper grounding.
Reliability study of plastic encapsulated copper lead frame/ epoxy die attach packaging system. J. R. HOWELL. IEEE/Proc. IRPS 104 (1981). This paper presents the evaluation methods used to appraise the reliability of plastic/copper lead frame