Reliable study of digital IC circuits with margin voltage among variable DC power supply, electromagnetic interference and conducting wire antenna

Microelectronics Reliability 43 (2003) 2001–2009 www.elsevier.com/locate/microrel

Reliable study of digital IC circuits with margin voltage among variable DC power supply, electromagnetic interference and conducting wire antenna Han-Chang Tsai

*

Department of Electronic Engineering, Cheng Shiu University, No. 840, Chengcing Rd. Niaosong, Kaohsiung, Taiwan 83305, ROC Received 26 December 2002; received in revised form 22 August 2003

Abstract This paper measures the margin voltage of a digital IC circuit in order to assess the deterioration of the margin voltage caused by variations in the DC power supply, electromagnetic interference (EMI), and the corresponding power induced in a conducting wire antenna (CWA). The present results confirm that these factors may influence the margin voltage to such an extent that the operation of the digital IC circuit may fail. This paper provides a theoretical analysis of the influence of these factors upon the margin voltage, and develops corresponding equations, which are then applied with appropriate parameter values to determine an optimal circuit operation. It is shown that the deteriorated margin voltage of the IC circuit is a function of the amplitude and frequency of the EMI source, and of the parasitic capacitance of the device, i.e. the greater the EMI amplitude and frequency, and the higher the capacitance of the device, the greater the likelihood that its operation will fail when subjected to a variable DC supply voltage, or to EMI and CWA effects. Furthermore, in the case of EMI, it is shown that an increased interference frequency will reduce the margin voltage of the device. Finally, it is noted that the smaller the input impedance of the IC device, the greater the influence of EMI is likely to be.
2003 Elsevier Ltd. All rights reserved.

1. Introduction Since digital circuits can only assume one of two binary states, i.e. ‘‘on and off’’ or ‘‘high and low’’, they are more reliable than their analogue counterparts, whose characteristics and states vary in a continuous manner. Therefore, a considerable effort has been expended in designing and manufacturing such devices, with the result that digital IC technologies are widely applied in numerous fields nowadays. In parallel with the continuous development of IC circuits, many researchers have investigated the potential influence on their operation of a variety of external variables, including component values, component aging, temperature, interference signals, EMI, and shielding.

*

Tel.: +886-7-7310606-531; fax: +886-7-7331758. E-mail address: [email protected] (H.-C. Tsai).

Although circuit designs generally do not allow for a failed operation to take place, failures may nevertheless occur as a result of an unstable DC power supply, AC interference, or ambient EMI. Long before governmental regulations were imposed governing the interference aspects of IC devices, designers were already addressing interference concerns. However, at that time, they tended to focus solely upon the potential influence of EMI and failed operations between circuits within an individual system. In practice however, interference may also occur between circuits within different systems, e.g. as a result of crosstalk between neighboring communication wires, or due to power induction or reception from a CWA component. In these situations, the IC device is far more likely to fall victim to EMI effects. Therefore, when considering the potential influence of external interference sources on the reliable operation of the proposed IC device, the designer must seek to achieve an electromagnetic compatibility (EMC) with the external environment.

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2003 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2003.08.010

2002

H.-C. Tsai / Microelectronics Reliability 43 (2003) 2001–2009

A review of the available literature pertaining to radio frequency interference in electronic devices reveals a number of investigations in the arenas of diodes [13,14], bipolar transistors [15–17], logic gates [18], operation amplifiers [19], and IC devices [20]. However, these studies generally focus upon the effects of an AC interference signal. Consequently, the present study develops a theoretical approach to assess the influence on the IC margin voltage of variations in the DC power supply, and considers the relative influences on the IC device reliability of EMI and CWA effects.

An EMI problem [1–12] comprises three basic elements, namely the interference source, the receiver, and the mechanism which couples the source and the receiver. In practice, an interference system may very well comprise several interference sources, several receivers and even several coupling mechanisms. Generally speaking, interference sources may be categorized as being one of two broad types, i.e. those in which the interference propagates along a conductor, and those in which it does not. Of the former type, direct AC interference is an obvious example, while interference arising from electric or magnetic fields, or in the form of plane waves, are typical examples of the latter. In the case of a conducted coupling, the designer can use an arrangement of filters and isolation mechanisms to reduce the interference effects. For example, when the interference frequency is significantly different from that of the signal, an appropriate filter can be employed which allows the signal to pass along the conductor, but which blocks the passage of the interference. Moreover, even in the case where both the interference and the signal frequencies fall within the same band, a precise filtering device with an asymmetrical transfer function can be used to shield the IC circuit. Regarding nonconducted couplings, the various circuit elements act as antennae which receive and propagate the interference. In this situation, the designer has at his disposal a number of alternative approaches to ameliorate the influence of this type of interference. These include

2. Theoretical analysis This section provides a theoretical analysis of the influences on the operation of the IC device of microvariations in the DC power supply, and of EMI and CWA effects. Detailed equations are developed to quantify the interference in each case. Specifically, this section addresses the case of interference coupling on a 7400 NAND gate. The TTL NAND gate circuit presented in Fig. 1 can be used to design basic logic gates, such as NOT gates, AND gates, OR gates, and multiharmonic oscillators of divided frequency. This NAND gate has been used within many TTL logic circuits, including the counter circuit presented in Fig. 2, whose operation under different forms of interference is considered in the present investigation. An abnormal counter operation is caused by the effects of propagation delays, the power delay product (PDP), or by some other form of interference. The PDP is the energy consumption per cycle per gate, and either represents the energy required to change the logic transition or the energy required for the logic decision. Consequently, it is desirable that the value of the PDP should be minimized. The PDP can be written in the following form [21]:

• shield arrangements, • decrease of undesired antenna effects between the transmitter and the receiver within a system, • decrease of induced effects, • increase of physical spacing between the antennae, • adoption of appropriate devices and structural properties, • proper cable layout, • proper circuit layout, • proper grounding layout.

PDP ffi K1 CL VDD ðVoH  VoL Þ; ðJÞ;

ð1Þ

VCC R1

R2

2

T3

4

T1 INPUT

R3 6

7

1

T2

3

D3 OUTPUT

8 D1

D2

T4

5 R4 0

Fig. 1. Interior circuit of 7400 NAND gate.

CL

H.-C. Tsai / Microelectronics Reliability 43 (2003) 2001–2009

2003

+5V 4.7M

5

CVolt

3

Q

W W'

X

X'

Y

Y'

Z

Z'

A

6

THR

B

9

5

7

DIS

3

555

1

TRIG

GND

R

2

VCC

8

4.7M 4

C

D

8

6

0.1uF

2

0.01uF

4

1

7404

A 1 3 2 +5V +5V 1

A 3

2 2 3

MR1 MR2

5

7493

Q0 Q1 Q2 Q3

B 4

12 9 8 11

6 4

5

B 6

5 14 1

CLK0 CLK1

10

8

C

9

A 8

1

10

6

f

e

d

Vcc

a

b

C 9 10

A

g +5V

5 4

W X'

2 1

Y Z'

74LS21

7 1 2 6 4 3 5

3

16 A B C D 7447 B1 LT RB1 8

a b c d e f g

13 12 11 10 9 15 14

2

1 2 13

A 7411

c

A 12 1 3 2

Fig. 2. Counter circuit.

where K1 is a constant, CL is the parasitic capacitance, VDD is the DC power supply voltage, VoH is the output high voltage, and VoL is the output low voltage. It is noted that a smaller PDP value is associated with a lower power supply voltage, less logic transition, and physically smaller gate structures, which can minimize the parasitic capacitance of the device. The oscillation frequency of the 555 IC in the counter circuit of Fig. 2 is given by f ¼

1:44 ; ðRa þ 2Rb ÞCt

ð2Þ

will start to transfer its state when VoL charges to VM , which represents the average value of VoH and VoL . When estimating the propagation delay of a typical TTL NAND gate, the internal transistor capacitance and the load-gate input capacitance can be combined into a single load capacitor, i.e. CL . The high-to-low and lowto-high propagation delays represent charging and discharging times, respectively, and can be denoted by tp1 and tp2 , respectively. The CL charging time, tp1 , is given by CL

1 t¼ ; f

VoH  VM VDD  0:9  VM ¼ IC ¼ : tp1 Rc

ð4Þ

ð3Þ

where Ra , Rb , and Ct are the external resistances and capacitance of the 555 IC during the charging and discharging operations. Furthermore, f is the oscillation frequency, which is adjusted to be approximately 1 Hz such that the output status of the counter is clearly identifiable. 2.1. Micro-variation of DC power supply It is assumed that the value of the DC charging voltage, VDD , is close to VoH , and that the logical output

Meanwhile, the CL discharging time, tp2 , can be expressed as CL

VM  VoL VM ¼ ID ¼ : tp2 Rf

ð5Þ

It is clear that the total propagation delay, tp , is given by tp ¼ tp1 þ tp2 , which can be expressed in the following form: tp ¼

Rc CL ðVoH  VM Þ Rf CL ðVM  VoL Þ þ : VDD  0:9  VM VM

ð6Þ

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H.-C. Tsai / Microelectronics Reliability 43 (2003) 2001–2009

In Eqs. (4)–(6), IC and ID denote the charging current and the discharging current, respectively, Rc represents the bias resistance of the collector, and Rf is the saturated resistance of the transistor. Under the influence of a micro-variation in the DC power supply, or an interfering AC current, the system output may become abnormal. If tp0 represents the total propagation delay in the event of an abnormal operation, then tp0 is given by tp0 ¼

0 0 Rc CL ðVoH  VM0 Þ Rf CL ðVM0  VoL Þ þ ; 0 0 VDD  0:9  VM VM

ð7Þ

where the parameters assigned a prime mark (0 ) are associated with the abnormal counter operation. Therefore, the increment in the total propagation delay caused by the DC power supply variation or by the external interference can be expressed as jDtj ¼ K2 ðtp0  tp Þ;

ð8Þ

where K2 is a constant equal to the total number of 7400 IC devices within the counter circuit. From Eqs. (6)–(8), it can be seen that the increase in the total propagation delay time when the counter operation becomes abnormal is a function of VDD , CL , Rc , Rf , VoH , and VoL , and of the number of 7400 IC devices within the counter circuit. 2.2. Electromagnetic interference (EMI) Fig. 3 shows an interference source in the form of a coil wound on a ferromagnetic toroid with an air gap. The magnetic field intensity (Hg ) in the air gap can be written as [22] Hg ¼

lNI0 : l0 ð2pr0  lg Þ þ llg

ð9Þ

Furthermore, the magnetic flux density (Bg ) is given

Bg ¼ l0 Hg :

ð10Þ

In Eqs. (9) and (10), l0 is the permeability of the free space, l is the permeability of the ferromagnetic material, I0 is the current flowing within the coil, r0 is the mean radius of the toroid, and lg is the width of the narrow air gap. The magnetic energy (PrB ) in the air gap can be expressed as PrB ¼

Z

1 l H 2 dv ¼ 2 0 g

Z

1 Hg Bg dv: 2

ð11Þ

The value of PrB represents the average energy per second of the interference on the CWA discussed in Section 2.3 below, and can either be calculated from Eq. (11) or can be measured directly. 2.3. Induced power in straight conducting wire antenna (CWA) The present study adopts a bare CWA to investigate the effects of an EMI source on the input of an IC device. The superposition theorem is adopted to analyze the IC circuit under these conditions. Since this theorem allows the effects of each voltage source within the circuit to be analyzed independently, and then combines the individual effects to determine the overall effect, it is possible to consider the effects of the CWA-induced interference voltage, Veff , in isolation. Fig. 4 presents the equivalent circuit model for the antenna-receiver combination used in this study to measure the resulting field intensity. The time-averaged induced power can be written as [23] Pr ¼ DI 2 ðRr þ Rin Þ ¼ DIVeff ¼

by

2 Veff ; Rr þ Rin

ð12aÞ

∆I

Veff

Vin

Rin

Rr

Antenna

Fig. 3. Coil on ferromagnetic toroid with air gap.

Receiver

Fig. 4. Equivalent circuit model for antenna-receiver combination used to measure field intensity.

H.-C. Tsai / Microelectronics Reliability 43 (2003) 2001–2009

where Veff DI ¼ ; Rr þ Rin

ð12bÞ

Rin ¼ Rohmic þ Rinput ; Rohmic ¼ Rs

Rs ¼

ð13Þ

DZ ; 2pa

ð14Þ

rffiffiffiffiffiffiffiffi xl0 : 2r

ð15Þ

In Eqs. (12a), (12b), (13)–(15), Veff and DI are the induced interference voltage and current in the device, respectively, and can be obtained directly by measurement, Rin is the input resistance of the device and includes the ohmic resistance of the CWA (Rohmic ) and the dynamic input resistance of the counter (Rinput ), a is the radius of the CWA wire, DZ is the length of the CWA wire, Rs is the surface resistance, x is the angular frequency which is given by 2pf where f is the frequency in Hertz, l0 is the permeability of the free space, r is the conductivity of the conducting wire, and Rr is the radiation resistance of the short dipole [22,23]. It is noted that  2 DZ for 0 < DZ < k=4 ð16aÞ Rr ¼ 20p2 k

   L IðZÞ ¼ Im sin b  jZj ; 2

L jZj < ; 2

Az ¼

ejbr 4pr

Z

L=2

IðZÞejbZ cos h dz:

ð20Þ

L=2

Substituting Eq. (19) into Eq. (20), and then substituting Eq. (20) into Eq. (17) gives the electric field as



 cos h  cos bL ejbr cos bL 2 2 Eh ¼ jg Im : ð21Þ 2pr sin h The radiated power is given by Z Z 1 s ðE H  Þ d~ Pr ¼ Re 2 Z Z 1 ðjEh j2 þ jE/ j2 Þr2 dX ¼ 2g " #2

 Z 2p Z p cos bL cos h  cos bL 1 Im2 2 2 2 g r2 ¼ 2g 0 sin h ð2prÞ2 0

sin h dh d/:

for k=4 < DZ < k=2;

ð16bÞ

where k is the wavelength of the EMI. By applying Maxwell’s electromagnetic field equations, it can be shown that the wire antenna was left along the z-axis. Additionally, if the theoretical analysis is simplified by considering only the far-field region, the ! ! induced electric field ( Eh ) and magnetic field ( HU ) of the z-directed interference source can be expressed as [22,23] ~ Eh ¼ h^jxl sin hAz ;

ð17Þ

~/ ¼ /^jb sin hAz ¼ ~ Eh =g; H

ð18Þ

where Az is the vector of the potential along the z-axis, h is the directional angle of thepradiation wave with ffiffiffiffiffiffiffi respect to the z-axis, and g ¼ l=e is the intrinsic impedance of the medium. In the current study, it was assumed that the inductive conducting wire was a straight dipole antenna, and that the currents induced in the wire were equal in magnitude, but opposite in terms of direction. Furthermore, the distribution of the currents along the wire antenna was assumed to be sinusoidal and hence can be written as

ð19Þ

where Im is the maximum induced current within the dipole, L is the length of the dipole, and b ¼ 2p=k is a phase constant. To obtain the dipole radiation pattern, it is first necessary to define a radiation integral for the z-directed wire antenna, i.e.

and  2:4 DZ Rr ¼ 24:7 p k

2005

ð22Þ

Since the total length of an induced wire antenna in any normal circuit may reach L ¼ k=2, when bL ¼ p2, 2 Eq. (22) can be re-written as Pr ¼

g 2 I 8p m

Z

2p

0

1  cos t dt p

2p k g 2X t2n  nþ1 I ð  1Þ ¼  8p m n¼1 2nðn!Þ  0

g Veff2 ¼ 2:44 Im2 ¼ ; 8p Rr þ Rin

Veff2 ¼

ð23Þ

2:44 gðRr þ Rin ÞIm2 ; 8p

Veff ¼ 0:3117Im

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi gðRr þ Rin Þ ¼ c1 Im gðRr þ Rin Þ;

ð24Þ

where c1 is a proportionality constant. The value of Veff can be obtained from Eqs. (16b) and (24). Veff is a function of the interference frequency, f , i.e. if f is increased, Veff will also increase. If a short dipole is considered, and the cosine function of Eq. (22) is expanded as a Taylor series with the higher-order terms neglected, then it can be shown that

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H.-C. Tsai / Microelectronics Reliability 43 (2003) 2001–2009



 bL bL cos h  cos 2 2  2 "  2 # 1 bL 1 bL ¼1 cos h  1  2 2 2 2  2 1 bL sin2 h: ¼ 2 2

3. Results and discussion

cos

ð25Þ

Eq. (22) can then be written as "  #2 Z 2p Z p 2 1 Im2 1 bL 2 Pr ¼ g sin h r2 sin h dh d/ 2g 0 ð2prÞ2 2 2 0 ¼

g 2 4 4 Veff2 ; Im b L ¼ Rr þ Rin 192p

ð26Þ

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Veff ¼ 0:0407Im b2 L2 gðRr þ Rin Þ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ c2 Im b2 L2 gðRr þ Rin Þ;

ð27Þ

where c2 is a proportionality constant. From Eqs. (16a), (24) and (27), it can be shown that the magnitude of the induced interference is proportional to the interference frequency, even when DZ L. Eq. (12b) shows that the magnitude of DI is inversely proportional to Rin , i.e. the lower the value of Rin , the higher the magnitude of DI. The discussions presented above relate to the reception issues associated with RF wave interference. Subsequently, a coupling efficiency constant between the interference source and the CWA can then be defined as follows: K¼

Pr ; PrB

ð28Þ

where PrB is the magnetic energy in the coil gap presented previously in Eq. (11).

To demonstrate the influence of variations of the DC power supply on the counter circuit, the highest and the higher margin voltages of the counter were measured using an oscilloscope. The results are presented in Table 1(panels A and B), respectively, together with the corresponding amplitudes and frequencies of the square waves at Pin 11 of the 7493 chip and at Pin 6 of the 7447 chip. The counter status at each DC supply voltage is also noted. From the results, it is noted that the highest and the higher margin voltages of the counter are 6.66 and 2.7 V, respectively. The counter system was operated at its margin voltage, and if there is a significant variation in the DC power supply voltage, the counter operation will fail. In a standard circuit operation, it is permissible for the interference frequency to vary within a tolerable margin, as described later in Fig. 6. The acceptable delay time of a standard 7400 IC device varies from 1.5 to 10 ns. Therefore, the total delay time, which includes the additional delay induced by EMI interference, should fall within this range. Some parameters were obtained as follows: Rc ¼ 130 X; Rf ¼ 21:6 X; VCQ3 ¼ 5:46 V; VoH ¼ 5:75 V; VoL ¼ 0:2 V; CL ¼ 20 Pf; 0 ¼ 5:812 V; VoH

0 VoL ¼ 0:2 V:

Adopting these parameters values, it can be shown from Eqs. (6) and (7), respectively, that the corresponding normal and abnormal operation propagation delays are tp ¼ 2:994 ns and tp0 ¼ 3:102 ns. Therefore, from Eq. (8), Dt ¼ 1:08 1010 K2 s, i.e. Dtp ¼ 1:08

1010 s, where Dtp , t represents the additional delay time in the circuit of a 7400 IC device when the change of the margin voltage is equal to 0.01 V (i.e. 6.67 ) 6.66 V ¼ 0.01 V). If K2 ¼ 100, then Dt ¼ 10:8 ns. If this delay is added to the standard propagation delay time of the

Table 1 Measurement results for highest (panel A) and higher (panel B) margin voltage Supply DC (V)

7493

7447

AMP.PIN11

FREQ.PIN11 (m)

AMP.PIN6

FREQ.PIN6 (m)

Segment count sequence

Panel A 6.61 6.62 6.63 6.66 6.67

6.125 6.125 6.125 6.125 6.187

120.2 120.2 121.0 201.6 330.0

5.687 5.750 5.750 5.750 5.812

402.4 403.2 404.0 520.8 202.6

Normal Normal Normal Normal 58503230 Abnormal 53230

Panel B 2.80 2.74 2.72 2.70 2.69

2.188 2.125 2.125 2.094 2.032

162.2 139.6 180.8 264.9 151.4

1.937 1.812 1.812 1.781 1.719

380.2 386.1 215.5 214.1 209.4

Normal Normal Normal Normal 58503230 Abnormal random

H.-C. Tsai / Microelectronics Reliability 43 (2003) 2001–2009

2007

7400 IC device, it is clear that the total delay time exceeds the acceptable range, and therefore abnormal counter operation will result. Similarly, for the results presented in Table 1(panel B), it can be shown that Dt ¼ 16:4 ns, which again exceeds the acceptable delay of the 7400 IC device. From these results, it is clear that variations in the DC power supply have a significant influence upon the performance of the counter operation. Therefore, establishing a stable DC power supply is of fundamental importance. In investigating the influence of interference caused by an electromagnetic field, the present study used a wire antenna as the CWA device, and adopted a CWA length of Dz ¼ 1 cm. 7400 IC devices were tested directly in the experiment. An AC current in the range of 0–1.6 A and with a frequency of 6 MHz was passed through the coil wrapped around the ferromagnetic toroid shown in Fig. 3. Fig. 5(a) plots the variation in the output voltage of the 7400 IC device for DC input voltages in the first pin of the 7400 IC in the range of 0–5 V for the different interference currents. The electromagnetic field intensity caused by the wire antenna can be calculated by determining the value of Veff from Eq. (27). However, in the present study, it was measured directly. Fig. 5(b) and (c), respectively, present enlarged views of the high (Veff from 0.004 to 0.01) and low functions (Veff from 0.0017 to 0.0026) for Veff ¼ 0:01 V (high) and Veff ¼ 0:0026 V (low). Meanwhile, the impedance of the 7400 IC input pin was 70 X. Therefore, the corresponding values of the induced interference current and the radiated power can be calculated to be DI ¼

0:01 ¼ 14:3 mA 70

and

DI ¼

0:0026 ¼ 37:1 lA; 70

and Pr ¼ 1:43 lW and

Pr ¼ 0:097 lW:

It is noted that these values represent a significant impact upon a single 7400 IC device. If the input impedance of the counter is taken to be 114K, then the corresponding values of the actual interference currents become DI ¼

0:01 ¼ 0:088 lA 114K

and

DI ¼

0:0026 ¼ 0:023 lA: 114K

These interfered values are too small to cause an abnormal counter operation. From Eq. (28), it can be shown that the coupling efficiency constant between the interference source and the CWA, i.e. K is equal to 1 · 102 and 6.8 · 104 for radiated powers of Pr ¼ 1:43 lW and Pr ¼ 0:097 lW, respectively, when the magnetic energy in the coil gap is given by PrB ¼ 143 lW. Although the induced currents do not cause an abnor-

Fig. 5. (a) Input electromagnetic interference of the 7400 device. Enlargement of the figure: (b) high function, (c) low function.

mal counter operation under these conditions, it was determined that when the interference signal was transmitted to an amplifier and then coupled to the 7400 device, an abnormal counter operation occurred. Fig. 6 presents the relationship between the output voltage of the 7400 IC device and its input DC voltage for different interference frequencies. When the EMI of the CWA interference current increased at pin 6 of the 7447 IC (Rinput ¼ 75 X) and when the counter was operated at normal margin voltage, the frequency of the

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H.-C. Tsai / Microelectronics Reliability 43 (2003) 2001–2009

Fig. 6. Correlation between output voltage and input DC voltage for different interference frequencies.

EMI interference was increased. When the counter operation became abnormal, the amplitude of the EMI interference signal was lowered such that the interference current reduced and the counter regained a normal operation. Subsequently, the frequency of the EMI interference was once again increased until the counter operation failed, at which point the amplitude was once more reduced. This process was repeated to generate the results presented in Fig. 6, in which it can be seen that the margin voltage of the counter operation is not only related to the value of DC power supply, but also to the amplitude and the frequency of the EMI interference signal. Specifically, the higher the value of the EMI frequency, the lower the margin voltage. In other words, the results reveal that the deterioration in the margin voltage is a function of the amplitude and the frequency of the EMI.

4. Conclusions The present study has demonstrated experimentally the reliability of digital IC circuits when the margin voltage of the device is influenced by variations in the DC power supply, or when it is subjected to EMI interference of different amplitudes and frequencies. Regarding the influence of the DC power supply, it has been shown that the additional propagation time delay which may result in a failed counter operation is a function of VDD , CL , VoH , VoL , Rc , and Rf . Specifically, the higher the parasitic capacitance of the device, the more likely it is that the operation will fail. Regarding the influence of EMI, the results have indicated that the deterioration in the margin voltage is a function of the amplitude and frequency of the EMI source, i.e. the greater the amplitude and the higher the frequency of the EMI, the more probable it is that the counter operation will become abnormal. For EMI, the interference of a wire antenna is induced in nature. If the length of a CWA on the PC board is excessive, or if the induced

interference signal is enlarged through an amplifier, it is highly probable that the system operation will become abnormal. The experimental results and theoretical analysis have shown that the magnitude of the EMI interference induced within the CWA is a function of f , Rin; , Rr , L, Pr , PrB , and Veff . Furthermore, it has been suggested that while the influence of the interference induced in the CWA by the EMI source may be too weak to have any significant impact on the digital circuit operation if the input impedance is high, if the input impedance is lowered, there will be an EMI influence to be considered. Consequently, when designing a digital circuit, the designer must not only consider the eight approaches to reducing the non-conducted coupling effects outlined in the Introduction of this paper, but should also ensure a stable DC power supply and should aim to decrease the parasitic capacitance of the circuit. In addition, the margin voltage of digital IC circuits which ought to have a more bigger than 5 V of basic high level of digital signal as possible, the exposed conducting wire on a PC board should be as short as possible.

Acknowledgements The current authors wish to express their sincere gratitude to Tzy-Yi Liaw for his invaluable assistance and contributions during the course of this study.

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