Removal of surface contamination after reactive ion etching of silicon dioxide

Vacuum/volume45/number 5/pages 519 to 524/1994

~

Elsevier Science Ltd

Pergamon

Printedin GreatBritain 0042-207X/94S7.00+.00

Removal of surface c o n t a m i n a t i o n after reactive ion etching of silicon dioxide R Jackson, A J

Pidduck and

M A Green,Defence Research Agency, StAndrews Road, Malvern, Worcs.

WR 14 3PS, UK

Reactive Ion Etching (R/E) during semiconductor device fabrication can cause surface and near-surface damage or contamination which may degrade electrical performance. We have investigated methods of removing this damage and contamination prior to further device processing. Using X-ray photoelectron spectroscopy we have analysed the surface residue remaining after a CHF3-based RIE process used for the removal of thermal oxide on Si substrates. The dry etched wafer surface was studied before and after wet chemical cleaning or UV/Oa exposure. Surface morphology was investigated using atomic force and scanning optical microscopy. Thicknesses of thermal oxides grown upon dry etched and subsequently treated wafer surfaces were measured. The results indicate the formation of a modified Si surface region underlying a residue layer formed during the RIE process. We report an investigation of the composition and oxidation behaviour as a function of depth through this near-surface region. This was performed by chemical depth profiling using a sequence of room temperature UV/03 oxidation and dilute HF oxide removal steps.

1. Introduction The reduction in the size of semiconductor devices has led to the increased use of plasma-assisted processing techniques. Reactive Ion Etching (RIE) is probably the most popular dry etching technique in semiconductor processing capable of defining submicron patterns in a variety of semiconductor materials, metals and dielectrics. RIE relies on both dry chemical etching and physical sputtering to obtain the desired etch profile. By careful consideration of the etch gas composition and applied potential between the substrate and plasma a highly anisotropic and selective etch can be achieved. It is essential, however, that the plasma process does not introduce damage or contamination into the semiconductor material which can impede device performance. It has been shown by several groups that the optimum etch characteristics may only be obtained at a sacrifice to performance. Incorporation of damage and contamination into the lattice of the semiconductor nearsurface region may occur through ion bombardment L'2, while partial masking of the etched surfaces by residues, particulates and impurities can lead to surface roughening3. For fluorine based RIE it is well known that surface contamination may occur, often in the form of a residue layer consisting of reaction species or reaction by-products 2'4. Oxides subsequently grown upon dry etched surfaces have shown increased interface state densities 5 and low breakdown voltages 6'7. It is, therefore, necessary to characterize each etch process and to remove any contamination and damage prior to further device processing. Several post etch treatments have previously been examined but nearly all have their own limitations in removing the damage and contamination. The growth of a sacrificial oxide may remove both damage and contamination8 but this usually includes the use of wet chemistry to remove the sacrificial oxide and may, therefore, not be suitable for fine geometry processes. A strong oxidizing agent such as an 02 plasma is capable of removing

contamination but cannot remove sub-surface damage 4'7. Exposure to UV/O3 has been reported to enhance the removal of any residue layer but again cannot completely restore the surface or sub-surface propertiesL We have studied the removal of thermal oxide on silicon substrates by RIE using an etch chemistry based on CHF3 and 02. The resultant surface layer chemistry and topography has been investigated by X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM) and scanning optical microscopy (SOM). Attempts to remove the surface and near-surface damaged Si region have been made using either an RCA wet chemical clean TM, exposure to a pure oxygen plasma or a combination of UV/O3 exposure and HF oxide etch. The impact upon the growth of subsequently grown thin gate oxides has been assessed.

2. Experimental Dry etching was performed in an Applied Materials AME 8111 RIE system which has a hexode configuration capable of etching 24 wafers at any one time. The anisotropic SiOz etch parameters were 4-sccm 02, 75 sccm CHF3, 50 mT pressure and 500 V bias. A 25% over-etch was performed on all substrates except where indi:ated. Approximately 1.5 nm of Si was removed during the oven-etch. To study the impact of the RIE process upon the Si surface exposed during etching a simple process was established based upon that for an aluminium contacted capacitor structure. The process used was : 1. RCA clean as-received (AR) substrates. 2. Grow 25 nm thermal oxide (protective oxide). 3. Etch oxide by RIE or dilute HF/H20 solution. 4. Perform various post oxide etch treatments (as detailed below). 5. Grow 25 nm thermal gate oxide. 519

R Jackson et al: Removal of surface contamination

The surface chemical state and topography were investigated after steps 3 and 4. Control samples which only received an R C A clean prior to gate oxidation were also compared. All Si substrates were 3" CZ (100). Both n and p type wafers were evaluated with resistivities of 0.08-0,5 ohm cm and 0.2-1.0 ohm cm, respectively. The RCA clean 10 consisted of immersing the substrates in two separate solutions each being followed by a dump rinse in ultra-pure de-ionized water. Solution 1 was a mixture of NH~OH/H202/H20 [1 : l :5] at 80°C for 15 rain and solution 2 HCI/H2OJH20 [1 : 1 : 5] at 80°C for l0 min. Wafers were finally rinsed and dried in N2. Thermal oxides were grown in a horizontal quartz furnace at 900"C in dry 02 for 105 rain immediately followed by an in situ 30 min N2 anneal. Wafer loading was carried out in N 2 at 900uC. An automatic optical measuring system assuming a refractive index of 1.46 was used for the determination of thermal oxide thicknesses. These values were confirmed by electrical measurements of oxide thicknesses derived from the quasi-static capacitance-voltage characteristics of completed capacitor structures. Post dry etch treatments used were: (i) an RCA clean as detailed above (RCA); (ii) a UV/Os exposure for 10 min in a stainless steel reactor (Uvocs Inc T16x 16/OES/E UV/O3 cleaning system) (UV/O3) ; (iii) a cycle of UV/O3 exposure and dilute HF etch steps (10 : 1 solution at 25°C followed by a dump rinse and spin dry) ( U V + HF), or (iv) plasma ashing in a barrel asher (Plasma Technology PRS 800) for 20 rain (plasma ash). Surface chemical residues after each dry etch and post dry etch treatment were examined by XPS using a hemispherical analyser (VSW HA150) with a multichannel detector and MgKct incident radiation (1253.6 eV, 300 W) at a fixed normal take-off angle. Substrates were loaded into the uhv system within 30 min of the dry etch or post dry etch treatment. Oxygen, carbon and fluorine coverages were measured from the areas of the Ols, Cls, and F 1s photoelectron peaks relative to that of the Si2p (Si) peak, using relative sensitivity factors given by Briggs and Seah t t. SiO~ layer thicknesses were measured from the relative areas of the Si2p (oxide) and Si2p (Si) photoelectron peaks using a value of 3.0 nm for the electron inelastic mean free path in the oxide re. Peak areas were calculated after linear background subtraction. Surface topography was investigated using either SOM operating in differential phase contrast mode or AFM. The SOM technique is similar to Nomarski microscopy with the image contrast being proportional to surface slope. Lateral resolution of ~0.4 #m and a vertical sensitivity of ~0.2 nm has been demonstrated ' 3. AFM images were obtained in air using a Digital Instruments Nanoscope lIl with a micro-fabricated Si3N4 cantilever and stylus. The net forced exerted on the surface by the stylus was approximately l0 150 nN.

. ~ A R + UV/O3

(a)

FIs RIE only

.E

(b)

-

Y2 E E

~¢

OIs

800

400

0

Figure 1. XPS raw data survey spectra from as-labelled surfaces.

UV/O3 for 10 rain the Fls and Cls photoemission intensity had reduced, as shown in spectrum (c). Figure 2 shows high resolution spectra of the Cls peak after the RIE process and after a subsequent 10 min UV/O3 exposure. After the dry etch process the Cls spectra was seen to consist of four major peaks at binding energies 284.8, 287.3, 289.7 and 292.2 eV which have been identified as C-C, CF, CF2 and CF 3 groups, respectively L4. After a 10 rain UV/O3 exposure the Cls photoemission intensity was dramatically reduced, all C - F bonds had disappeared, leaving a peak at low binding energy (282.6 eV) typical of SiC. The high resolution Si2p spectra shown in Figure 3 comprises a major peak due to the Si substrate photoemission (Si2p(Si)) and a chemically shifted component arising from SiOx binding states (Si2p(oxide)). From the attenuation of the Si2p(Si) peak in the RIE spectrum the fluorocarbon layer thickness was esti-

.J'< .5

52O

.

Binding energy (eV)

RIE only

3. Results 3.1. Surface chemistry. XPS spectra from three processed wafer surfaces are displayed in Figure 1. Spectrum (a) was obtained from an as-received wafer exposed to UV/O3 for 10 rain. The only detectable elements were oxygen and silicon. Carbon was not observed above the detection limit of 0.2 monolayers suggesting that minimal contamination of the surface occurred during the transfer process. The chemical state of the surface directly after the RIE process is shown in spectrum (b). The prominent peaks observed were F ls and C 1s photoemissions associated with a fluorocarbon residue layer 4. After exposing the RIE surface to

Cls

'=-E

RIE + UV/O3

291

281

Binding energy (eV)

Figure 2. High resolution Cls spectra after R|E (top panel) and RIE + UV/O3 (lower panel) (raw data).

R Jackson et al: Removal of surface contamination

xil

TaMe 2. AFM derived root mean square roughness (a) of Si surface after processing (evaluation area = 4 #m :) Process

a (nm)

A R + 2 5 nm SiO2+HF A R + 2 5 nm SiO2+ RIE+25 nm SiO2+HF AR + 25 nm SiO2 + RIE + UV/O3 + HF + UV/O3 + H F + UV/O3+25 nm SiO2+HF

0.11 0.12 0.16

..= RIE only level. The fluorine concentration was only slightly further reduced after the H F etch but a significant reduction was observed after a second UV/O3 exposure.

o

103

98

93

Binding energy (eV) Figure 3. High resolution Si2p spectra from as-labelled surfaces (raw data).

mated to be approximately 4 nm, using an electron inelastic mean free path o f 3 nm ~5. In the A R + U V / O 3 and R I E + U V / O 3 spectra the d o m i n a n t Si2p(oxide) component was shifted by approximately 4 eV, which is consistent with SIO2. The thickness of the SiO2 overlayer for the R I E + UV/O3 sample was, however, larger than that for the A R + U V / O 3 sample, 2.1 nm compared with 1.1 nm, respectively. A smaller chemical shift was observed directly after RIE, indicating the presence of suboxide bonding states. Table I lists the relative surface atomic concentrations o f oxygen, carbon and fluorine normalized to Si (Si2p(Si)) area = 1.0) as a function of surface treatment. After R1E a high carbon-fluorine coverage was observed as noted above, probably in the form of a polymeric layer. The R C A clean failed to remove this layer completely. The fluorocarbon layer was, however, removed by a 10 min UV/O3 exposure. After this process, C (in the form of SiC) and F impurities remained at the monolayer

3.2. Surface topography. Figure 4 displays SOM images of the as-etched and treated wafer surfaces. N o significant difference in surface texture was observed between the A R and as-etched surfaces with only a small increase in roughness observed after the U V / O 3+ H F + UV/O3 + H F + U V / O 3 treatment. N o differences were observed in the surface texture prior to or after gate oxidation, or after removing the gate oxide in dilute HF. A F M measurements of the rms surface roughness (a calculated over a 2 #m x 2 pm area) are given in Table 2. The A F M images in Figure 5 show that the observed roughness was on a finer length scale than in the S O M images. As with the S O M images the surface roughness was only seen to change significantly after the full UV/O3 and H F etch cycle. 3.3. Thermal oxide growth. Table 3 displays the thickness of the thermal gate oxides grown after R I E and various post-etch treatments. The growth of thermal oxide was retarded by R1E though was not dependent upon the thickness of the fluorocarbon over-layer. When the fluorocarbon layer had been completely removed, as after a U V / O 3 exposure, the oxide thickness was still low. An increase was observed only after the UV/O3 generated oxide had been removed in dilute HF. An oxide thickness equal to that for an A R wafer surface was only obtained after either a plasma ash or UV/O3 + H F + UV/O3 + H F + UV/O3 treatment.

4. Discussion The XPS data are consistent with the simple model proposed in Figure 6 depicting the surface region of the substrate after RIE. A thick fluorocarbon layer exists after the RIE process which cannot be completely removed by a standard R C A clean. A successful treatment for the removal of the fluorocarbon layer is

Table 1. Calculated relative surface atomic concentrations from XPS data after surface treatment (normalized to Si = 1.0) Sample treatment

O

C

F

As-received + UV/O3 RIE end point etch RIE only RIE + RCA clean RIE + UV/O3 RIE+ UV/O3+HF RIE + UV/O3 + HF + UV/O3 RIE + UV/O3 + HF + UV/O3 + HF RIE + UV/O 3+ HF + UV/O3 + HF + UV/O 3 RIE +plasma ash

0.65 0.41 0.59 1.1 1.1 0.16 1.1 0.13 0.82

<0.04 2.0 4.4 1.6 0.16 0.14 < 0.04 0.07 < 0.04

<0.02 2.4 4.1 0.60 0.25 0.09 0.05 0.02 0.02

2.8

<0.04

0.02

Table 3. Thicknesses of gate oxides grown on treated surfaces Sample treatment

Oxide thickness (nm)

As-received + RCA RIE + RCA R1E + UV/O3 RIE + UV/O3 + HF RIE + UV/O3 + HF + UV/O 3 R1E + UV/O 3+ HF + UV/O 3+ HF RIE + UV/O3 + H F + UV/O3 + HF + UV/O3 RIE + plasma ash

27.1 22.5 22.6 24.4 24.5 26.7 26.8 26.4 521

R Jackson et al: Removal of surface contamination

AS-RECEIVED

+ RCA CLEAN

PIE + UV/03

RIE + RCA CLEAN

PIE + UV/0 3 + HF + UV/0 3 + HF + UV/0 3

Figure 4. SOM images of Si surface after surface processing.

exposure t o UV/O 3 as previously reported 9 but we have found that this cannot restore the surface and near-surface oxidation properties. After removal of the fluorocarbon layer, a thin surface oxide remains, and in the near surface Si region under this, there are embedded C and F impurities. The implanted C : F concentration ratio in the Si near-surface region is lower than in the fluorocarbon over-layer. The detection limit of C species is significantly higher than that of F and so the true ratio in Si cannot be determined. The depth of the F and C penetration can be estimated from the amount of Si removed in the UV/O3 and HF etch cycles. No C is detected by XPS after approximately 1.6 nm of Si has been removed while F exists beyond 2.3 nm. Two main points of interest have been observed in this study. Firstly, the enhanced room temperature oxidation of a surface subjected to the RIE process ; and secondly, the retarded thermal 522

oxidation of the RIE surface. The oxidation rate of Si can be affected by several factors including surface roughness, damage and chemistry. We have seen that the surface roughness is not increased significantly by the RIE process and so is not a factor to consider. We will first consider the enhanced room temperature oxidation. The incorporation of C and F impurities into the nearsurface region suggests that the Si lattice has incurred damage through shallow ion bombardment. Such damage may increase the reactivity of the Si and hence increase the room temperature oxidation in comparison with the control sample. The post etch treatments which consume the near-surface Si region would change this oxidation behaviour. As small amounts of the Si surface are removed by the UV/O3 and H F process the enhanced oxidation becomes less pronounced, indicating that the affected

R Jackson et al. Removal of surface contamination .....

RIE

3.0 nN

ONLY 1.5 nN

0,0 n. ~..00

L l 0

1. O0

~

~

J

t

~

/~-z.uu

2.00

R I E + U V + H F + U V + HF + U V

3 . 0 n.

1,5 nw

2. O0

2,00

0.0 nM

kin

Figure 5. AFM images of Si surface after the removal of 25 nm oxide by RIE, surface treatment as-labelled, re-growth of 25 nm oxide and subsequent removal in 10 : 1 HF.

depth is in the region of 1-2 nm. Silicon lattice damage may, therefore, explain the observed increase in the room temperature oxide thickness if the damaged zone is very shallow. Secondly, we consider the retarded thermal oxidation. A previous report has suggested that normal thermal oxidation after CHF3-based RIE can only be recovered after the growth and wet etch of a 7.5 nm sacrificial oxide ~6. During this process, approximately 3 nm of the near surface Si region is consumed. We have observed that approximately 2 nm of the Si near-surface

region needs to be consumed (as in the plasma ash process and UV/O3 + H F etch cycles) before normal oxidation occurs. The decrease in the thermal oxidation rate after RIE has previously been associated with C lattice contamination' 7. This is a result of the consumption of O by the C contamination in creating volatile COx species which, once removed, restores the oxidation growth rate. Residual fluorine is unlikely to be responsible for the reduced thermal oxide thickness because of the literature evidence that F can, if anything, tend to cause an increase in oxide thickness ~s. It has been shown that a fluorocarbon overlayer can be removed by a short high temperature anneal TM and so it is anticipated that the thin layer existing after the RCA clean is removed in our case during the short anneal step prior to oxidation. It is also possible that the sub-surface damage responsible for the enhanced room temperature oxidation may be annealed out at this stage. Therefore, the near-surface implanted C may well be responsible for the reduced thermal oxide growth. We note, however, that a significantly reduced oxide thickness is still observed after a UV/O3q-HFq-UV/O3 cycle even though the level of C remaining is below our XPS detection limit. 5. C o n c l u s i o n

A highly anisotropic CHF3-based RIE process used for the etching of SiO2 on Si substrates has been evaluated. During overetch a fluorocarbon residue layer forms which cannot be removed by a standard RCA type clean. We have found that the residue layer may be removed by exposure to UV/O3, although C and F contamination is still observed in the Si near-surface region. The growth of a room temperature UV/O3 oxide after RIE is enhanced in comparison with that found on an as-received surface. This may be due to lattice damage of the Si near-surface region. Oxides grown upon the RIE surfaces at elevated temperatures in pure 02 have a reduced oxide thickness compared with AR surfaces, possibly due to C contamination of the Si lattice. The oxidation properties can be restored by two UV/O3 exposures and HF cycles or by exposing the surface to a 20 min 02 plasma ash process. In both cases approximately 2 nm of the Si surface region is consumed. Acknowledgements

The authors would like to thank K M Brunson and F D J Boller for their assistance with the electrical characterization and the members of the Si processing laboratory at DRA, Malvern, for their assistance in fabricating the test structures. This work was partly funded under the DTI lED 2/1/1769 project. References

I-Wen, H Connick, A Bhattacharyya, K N Ritz and W Lee Smith, J Appl Phys, 64, 2059 (1988). 2j H Thomas III, J Vac Sci Technol, B7, 1236 (1989).

Fluorocarbon residue layer aDadn~f~dSinlaye~at~

--

--

Figure

6. Model of the wafer surface after RIE.

Thin SiOx layer

Bulk silicon

3D J Thomas, P Southworth, M C Flowers and R Greef, J Vac Sci Technol, BS, 516 (1990). 4G S Oehrlein, S W Robey, J L Lindstrom, K K Chan, M A Jaso and G J Scilla, J Electrochem Soc, 136, 2050 (1989). 5S W Pang, Solid St Technol, April, 249 (1984). 6F K Moghadam and Xiao-Chun Mu, IEEE Trans Electron Devices, 36, 1602 (1989). 7L M Ephrath and R S Bennett, J Electrochem Soc, 129, 1822 (1982). 8N Lifshitz, J Electrochem Soc, 130, 1549 (1983). 9j Ruzyllo, G T Duranko, J T Kennedy and C G Pantano, ULSI Sci Technol, 281 (1987). ]°W Kern and D A Poutinen, RCA Rev, 31, 187 (1970).

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R Jackson et al: Removal of surface contamination

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524

6A Bhattacharyya, T Bril, C Vorst, B Westlund and F Van Roosmalen, J Electrochem Soc, 133, 1670 (1986). 17E Ikawa, N Endo, M Tajima and Y Kurogi, Surface Sci, 172, 763 (1986). ~G Q Lo, W Ting, J H A h n and Dim-Lee Kwong, IEEE Trans Electron Devices, 39, 148 (1992). ~9G S Oehrlein, J G Clabes and P Spirito, J Electroehem Soc, 133, 1002 (1986).