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Research and development for a free-running readout system for the ATLAS LAr Calorimeters at the high luminosity LHC
Nuclear Instruments and Methods in Physics Research A ∎ (∎∎∎∎) ∎∎∎–∎∎∎
Contents lists available at ScienceDirect
Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima
Research and development for a free-running readout system for the ATLAS LAr Calorimeters at the high luminosity LHC Maximilian Hils Institut fur Kern- und Teilchenphysik, Technische Universitat Dresden, Zellescher Weg 19, D-01069 Dresden, Germany
On behalf of the ATLAS Liquid Argon Calorimeter Group art ic l e i nf o
Keywords: ATLAS Liquid Argon Calorimeter Phase-II upgrade Readout electronics
a b s t r a c t The ATLAS Liquid Argon (LAr) Calorimeters were designed and built to measure electromagnetic and hadronic energy in proton–proton collisions produced at the Large Hadron Collider (LHC) at centre-ofmass energies up to 14 TeV and instantaneous luminosities up to 1034 cm 2 s 1. The High Luminosity LHC (HL-LHC) programme is now developed for up to 5–7 times the design luminosity, with the goal of accumulating an integrated luminosity of 3000 fb 1. In the HL-LHC phase, the increased radiation levels and an improved ATLAS trigger system require a replacement of the Front-end (FE) and Back-end (BE) electronics of the LAr Calorimeters. Results from research and development of individual components and their radiation qualification as well as the overall system design will be presented. & 2015 The Authors. Published by Elsevier B.V. All rights reserved.
1. Introduction For 2024 an upgrade of the LHC is planned which foresees a further increase in luminosity. During the high luminosity phase of the LHC integrated and instantaneous luminosities of 3000 fb 1 and 7 1034 cm 1 are assumed. The ATLAS detector [1] is planned to be operated with Level-0 and Level-1 trigger accept rates of 1 MHz and 400 kHz and trigger latencies of 6 μs and 30 μs, respectively. These conditions will bring the current readout electronics of the ATLAS LAr Calorimeter system beyond their design specifications. A complete replacement of the LAr Calorimeter FE and BE electronics, during the so-called Phase-II upgrade, is therefore foreseen which provides larger data buffers, a highbandwidth data transmission and an improved radiation tolerance of the FE components.
2. Architecture of the Phase-II readout system Fig. 1 shows an overview of the Phase-II FE and BE electronics. The new FE boards will first amplify and shape the analog signal and digitize the signal with a 40–80 MHz sampling frequency. The digital signal will be serialized and sent out via fast optical links to E-mail address: [email protected]
the BE Pre-Processor (PP) system. The PP applies digital filter algorithms to reconstruct the deposited energy.
3. Radiation tolerance criteria and design parameters for middle layer electronics Since the FE electronics of the LAr Calorimeters are located on the calorimeter cryostats they are subject to significant radiation exposure. The radiation tolerance criteria for the ASICs for Phase-II are total ionization dose of 1.74 kGy, non-ionizing energy loss of 5.0 1013neq/cm2, single event effects with 9.6 1013h/cm2, all values include a safety factor of 5 [2]. The radiation background in the ATLAS cavern has been measured recently [3] and good agreement with simulation is observed. Final radiation qualification criteria will be determined once the detector choices for the HL-LHC operation of ATLAS are made. Besides the radiation tolerance, there are several other design parameters which should be met by the new electronics. In order to capture the expected range of deposited energies per calorimeter cell, a dynamic range of 16.25 bits per channel is required. The maximum input current per channel is about 10 mA and the noise should therefore not exceed 100 nA. Cooling capabilities require the power per channel to be less than 50 mW. Furthermore, the serializer and the optical transmitter should provide a data rate of at least 9 GB/s per fiber excluding data packaging and forward error corrections.
http://dx.doi.org/10.1016/j.nima.2015.10.038 0168-9002/& 2015 The Authors. Published by Elsevier B.V. All rights reserved.
Please cite this article as: M. Hils, Nuclear Instruments & Methods in Physics Research A (2015), http://dx.doi.org/10.1016/j. nima.2015.10.038i
M. Hils / Nuclear Instruments and Methods in Physics Research A ∎ (∎∎∎∎) ∎∎∎–∎∎∎
2
Fig. 1. Phase-II readout architecture, the new modules are indicated in red [2]. (For interpretation of the references to color in this figure caption, the reader is referred to the web version of this paper.)
Table 1 Summary of technologies which are under investigation. Characteristics
Plan I
Plan II
Gain segmentation ADC resolution Sample rate Technology
4 scale 10/12 bits 40/80 MS/s CMOS
2 scale 14 bits SiGe/CMOS Fig. 2. Schematic overview of the future FE, which may be integrated in a single Front-end System-on-Chip (FESOC).
4. Technologies under investigation Table 1 gives a summary of different technologies under investigation which include 65 nm CMOS and 180 nm SiGe technologies. The goal is to use a single technology for the preamplifier, shaper and ADC, in order to reduce power and complexity of the system (as shown in Fig. 2). A gain selection may be applied on the digital data in the BE processing. A design study in 180 nm SiGe technology shows that 2 gain stages combined with 14-bit ADCs fulfill the requirements on noise, dynamic range and radiation tolerance. A programmable shaping furthermore allows a better pile-up mitigation. The benefits of a smaller feature size are reduced power consumption and improved radiation robustness. An example layout in 65 nm CMOS technology implements 10-bit ADCs and four gain stages, but other designs are also possible. The 65 nm technology
would allow an integration with the serializer and optical link components, which are foreseen to be developed in this technology within the CERN lpGBT project [4].
5. Back-end electronics The BE PP system will apply digital filter algorithms for energy reconstruction and will prepare the input to the Level-1 trigger system and the data acquisition. The FPGA-based processing boards will be an evolution of the currently developed LAr Digital Processing System (LDPS) [5], for which a demonstrator board is shown in Fig. 3. In the so-called Phase-I upgrade the LAr trigger readout will be improved to read out 34 000 trigger channels. In Phase-II, at the HL-LHC, all
Please cite this article as: M. Hils, Nuclear Instruments & Methods in Physics Research A (2015), http://dx.doi.org/10.1016/j. nima.2015.10.038i
M. Hils / Nuclear Instruments and Methods in Physics Research A ∎ (∎∎∎∎) ∎∎∎–∎∎∎
3
LHC phase. System optimization and further prototyping will be performed to define the final design parameters and to prepare the complete readout system for installation in 2024.
Acknowledgements This work was supported in part by the German Bundesministerium für Bildung und Forschung (BMBF) within the research network FSP-101 Physics on the TeV Scale with ATLAS at the LHC.
References
Fig. 3. Demonstrator board of the future LDPS.
Table 2 Overview of the BE configuration in the upcoming upgrade phases. Characteristics
Phase-I LDPS
Phase-II PP
# of channels ADC number of bits Sampling rate Rate from FE Fiber speed from FE Channels per FPGA Input speed per FPGA Output speed per FPGA
34 000 12 40 MHz 25 TB/s 5.12 GB/s 320 205 GB/s 280 GB/s
183 000 12–14 þ gain bits 40–80 MHz 200–300 TB/s 10 GB/s 380–640 400–800 GB/s 4 30 GB=s
[1] ATLAS Collaboration, Journal of Instrumentation 3 (2008) S08003. [2] ATLAS Collaboration, Letter of Intent for the Phase-II Upgrade of the ATLAS Experiment, CERN-LHCC-2012-022, 2012. [3] ATLAS Collaboration, Report of the Radiation Estimate Task Force, CERN 2013, ATU-GE-ER-0005, EDMS 1293497, 2013. [4] Paulo Moreira, GBT Project: Present & Future, ACES 2014 – Fourth Common ATLAS CMS Electronics Workshop for LHC Upgrades, CERN, 2014. [5] ATLAS Collaboration, ATLAS Liquid Argon Calorimeter Phase-I Upgrade Technical Design Report, CERN-LHCC-2013-017, 2013.
183 000 channels are processed digitally (see Table 2). Energy reconstruction and regional pile-up suppression algorithms are planned to be executed on about 100 PP blades each equipped with 4 FPGAs.
6. Summary and outlook Components for the analog and digital signal processing of the ATLAS LAr Calorimeter readout are being developed for the HL-
Please cite this article as: M. Hils, Nuclear Instruments & Methods in Physics Research A (2015), http://dx.doi.org/10.1016/j. nima.2015.10.038i
Contents lists available at ScienceDirect
Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima
Research and development for a free-running readout system for the ATLAS LAr Calorimeters at the high luminosity LHC Maximilian Hils Institut fur Kern- und Teilchenphysik, Technische Universitat Dresden, Zellescher Weg 19, D-01069 Dresden, Germany
On behalf of the ATLAS Liquid Argon Calorimeter Group art ic l e i nf o
Keywords: ATLAS Liquid Argon Calorimeter Phase-II upgrade Readout electronics
a b s t r a c t The ATLAS Liquid Argon (LAr) Calorimeters were designed and built to measure electromagnetic and hadronic energy in proton–proton collisions produced at the Large Hadron Collider (LHC) at centre-ofmass energies up to 14 TeV and instantaneous luminosities up to 1034 cm 2 s 1. The High Luminosity LHC (HL-LHC) programme is now developed for up to 5–7 times the design luminosity, with the goal of accumulating an integrated luminosity of 3000 fb 1. In the HL-LHC phase, the increased radiation levels and an improved ATLAS trigger system require a replacement of the Front-end (FE) and Back-end (BE) electronics of the LAr Calorimeters. Results from research and development of individual components and their radiation qualification as well as the overall system design will be presented. & 2015 The Authors. Published by Elsevier B.V. All rights reserved.
1. Introduction For 2024 an upgrade of the LHC is planned which foresees a further increase in luminosity. During the high luminosity phase of the LHC integrated and instantaneous luminosities of 3000 fb 1 and 7 1034 cm 1 are assumed. The ATLAS detector [1] is planned to be operated with Level-0 and Level-1 trigger accept rates of 1 MHz and 400 kHz and trigger latencies of 6 μs and 30 μs, respectively. These conditions will bring the current readout electronics of the ATLAS LAr Calorimeter system beyond their design specifications. A complete replacement of the LAr Calorimeter FE and BE electronics, during the so-called Phase-II upgrade, is therefore foreseen which provides larger data buffers, a highbandwidth data transmission and an improved radiation tolerance of the FE components.
2. Architecture of the Phase-II readout system Fig. 1 shows an overview of the Phase-II FE and BE electronics. The new FE boards will first amplify and shape the analog signal and digitize the signal with a 40–80 MHz sampling frequency. The digital signal will be serialized and sent out via fast optical links to E-mail address: [email protected]
the BE Pre-Processor (PP) system. The PP applies digital filter algorithms to reconstruct the deposited energy.
3. Radiation tolerance criteria and design parameters for middle layer electronics Since the FE electronics of the LAr Calorimeters are located on the calorimeter cryostats they are subject to significant radiation exposure. The radiation tolerance criteria for the ASICs for Phase-II are total ionization dose of 1.74 kGy, non-ionizing energy loss of 5.0 1013neq/cm2, single event effects with 9.6 1013h/cm2, all values include a safety factor of 5 [2]. The radiation background in the ATLAS cavern has been measured recently [3] and good agreement with simulation is observed. Final radiation qualification criteria will be determined once the detector choices for the HL-LHC operation of ATLAS are made. Besides the radiation tolerance, there are several other design parameters which should be met by the new electronics. In order to capture the expected range of deposited energies per calorimeter cell, a dynamic range of 16.25 bits per channel is required. The maximum input current per channel is about 10 mA and the noise should therefore not exceed 100 nA. Cooling capabilities require the power per channel to be less than 50 mW. Furthermore, the serializer and the optical transmitter should provide a data rate of at least 9 GB/s per fiber excluding data packaging and forward error corrections.
http://dx.doi.org/10.1016/j.nima.2015.10.038 0168-9002/& 2015 The Authors. Published by Elsevier B.V. All rights reserved.
Please cite this article as: M. Hils, Nuclear Instruments & Methods in Physics Research A (2015), http://dx.doi.org/10.1016/j. nima.2015.10.038i
M. Hils / Nuclear Instruments and Methods in Physics Research A ∎ (∎∎∎∎) ∎∎∎–∎∎∎
2
Fig. 1. Phase-II readout architecture, the new modules are indicated in red [2]. (For interpretation of the references to color in this figure caption, the reader is referred to the web version of this paper.)
Table 1 Summary of technologies which are under investigation. Characteristics
Plan I
Plan II
Gain segmentation ADC resolution Sample rate Technology
4 scale 10/12 bits 40/80 MS/s CMOS
2 scale 14 bits SiGe/CMOS Fig. 2. Schematic overview of the future FE, which may be integrated in a single Front-end System-on-Chip (FESOC).
4. Technologies under investigation Table 1 gives a summary of different technologies under investigation which include 65 nm CMOS and 180 nm SiGe technologies. The goal is to use a single technology for the preamplifier, shaper and ADC, in order to reduce power and complexity of the system (as shown in Fig. 2). A gain selection may be applied on the digital data in the BE processing. A design study in 180 nm SiGe technology shows that 2 gain stages combined with 14-bit ADCs fulfill the requirements on noise, dynamic range and radiation tolerance. A programmable shaping furthermore allows a better pile-up mitigation. The benefits of a smaller feature size are reduced power consumption and improved radiation robustness. An example layout in 65 nm CMOS technology implements 10-bit ADCs and four gain stages, but other designs are also possible. The 65 nm technology
would allow an integration with the serializer and optical link components, which are foreseen to be developed in this technology within the CERN lpGBT project [4].
5. Back-end electronics The BE PP system will apply digital filter algorithms for energy reconstruction and will prepare the input to the Level-1 trigger system and the data acquisition. The FPGA-based processing boards will be an evolution of the currently developed LAr Digital Processing System (LDPS) [5], for which a demonstrator board is shown in Fig. 3. In the so-called Phase-I upgrade the LAr trigger readout will be improved to read out 34 000 trigger channels. In Phase-II, at the HL-LHC, all
Please cite this article as: M. Hils, Nuclear Instruments & Methods in Physics Research A (2015), http://dx.doi.org/10.1016/j. nima.2015.10.038i
M. Hils / Nuclear Instruments and Methods in Physics Research A ∎ (∎∎∎∎) ∎∎∎–∎∎∎
3
LHC phase. System optimization and further prototyping will be performed to define the final design parameters and to prepare the complete readout system for installation in 2024.
Acknowledgements This work was supported in part by the German Bundesministerium für Bildung und Forschung (BMBF) within the research network FSP-101 Physics on the TeV Scale with ATLAS at the LHC.
References
Fig. 3. Demonstrator board of the future LDPS.
Table 2 Overview of the BE configuration in the upcoming upgrade phases. Characteristics
Phase-I LDPS
Phase-II PP
# of channels ADC number of bits Sampling rate Rate from FE Fiber speed from FE Channels per FPGA Input speed per FPGA Output speed per FPGA
34 000 12 40 MHz 25 TB/s 5.12 GB/s 320 205 GB/s 280 GB/s
183 000 12–14 þ gain bits 40–80 MHz 200–300 TB/s 10 GB/s 380–640 400–800 GB/s 4 30 GB=s
[1] ATLAS Collaboration, Journal of Instrumentation 3 (2008) S08003. [2] ATLAS Collaboration, Letter of Intent for the Phase-II Upgrade of the ATLAS Experiment, CERN-LHCC-2012-022, 2012. [3] ATLAS Collaboration, Report of the Radiation Estimate Task Force, CERN 2013, ATU-GE-ER-0005, EDMS 1293497, 2013. [4] Paulo Moreira, GBT Project: Present & Future, ACES 2014 – Fourth Common ATLAS CMS Electronics Workshop for LHC Upgrades, CERN, 2014. [5] ATLAS Collaboration, ATLAS Liquid Argon Calorimeter Phase-I Upgrade Technical Design Report, CERN-LHCC-2013-017, 2013.
183 000 channels are processed digitally (see Table 2). Energy reconstruction and regional pile-up suppression algorithms are planned to be executed on about 100 PP blades each equipped with 4 FPGAs.
6. Summary and outlook Components for the analog and digital signal processing of the ATLAS LAr Calorimeter readout are being developed for the HL-
Please cite this article as: M. Hils, Nuclear Instruments & Methods in Physics Research A (2015), http://dx.doi.org/10.1016/j. nima.2015.10.038i